1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/pcs/pcs-xpcs.h> 11 #include <linux/mdio.h> 12 #include <linux/phylink.h> 13 #include <linux/workqueue.h> 14 15 #define SYNOPSYS_XPCS_USXGMII_ID 0x7996ced0 16 #define SYNOPSYS_XPCS_10GKR_ID 0x7996ced0 17 #define SYNOPSYS_XPCS_XLGMII_ID 0x7996ced0 18 #define SYNOPSYS_XPCS_SGMII_ID 0x7996ced0 19 #define SYNOPSYS_XPCS_MASK 0xffffffff 20 21 /* Vendor regs access */ 22 #define DW_VENDOR BIT(15) 23 24 /* VR_XS_PCS */ 25 #define DW_USXGMII_RST BIT(10) 26 #define DW_USXGMII_EN BIT(9) 27 #define DW_VR_XS_PCS_DIG_STS 0x0010 28 #define DW_RXFIFO_ERR GENMASK(6, 5) 29 30 /* SR_MII */ 31 #define DW_USXGMII_FULL BIT(8) 32 #define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5)) 33 #define DW_USXGMII_10000 (BIT(13) | BIT(6)) 34 #define DW_USXGMII_5000 (BIT(13) | BIT(5)) 35 #define DW_USXGMII_2500 (BIT(5)) 36 #define DW_USXGMII_1000 (BIT(6)) 37 #define DW_USXGMII_100 (BIT(13)) 38 #define DW_USXGMII_10 (0) 39 40 /* SR_AN */ 41 #define DW_SR_AN_ADV1 0x10 42 #define DW_SR_AN_ADV2 0x11 43 #define DW_SR_AN_ADV3 0x12 44 #define DW_SR_AN_LP_ABL1 0x13 45 #define DW_SR_AN_LP_ABL2 0x14 46 #define DW_SR_AN_LP_ABL3 0x15 47 48 /* Clause 73 Defines */ 49 /* AN_LP_ABL1 */ 50 #define DW_C73_PAUSE BIT(10) 51 #define DW_C73_ASYM_PAUSE BIT(11) 52 #define DW_C73_AN_ADV_SF 0x1 53 /* AN_LP_ABL2 */ 54 #define DW_C73_1000KX BIT(5) 55 #define DW_C73_10000KX4 BIT(6) 56 #define DW_C73_10000KR BIT(7) 57 /* AN_LP_ABL3 */ 58 #define DW_C73_2500KX BIT(0) 59 #define DW_C73_5000KR BIT(1) 60 61 /* Clause 37 Defines */ 62 /* VR MII MMD registers offsets */ 63 #define DW_VR_MII_DIG_CTRL1 0x8000 64 #define DW_VR_MII_AN_CTRL 0x8001 65 #define DW_VR_MII_AN_INTR_STS 0x8002 66 /* EEE Mode Control Register */ 67 #define DW_VR_MII_EEE_MCTRL0 0x8006 68 #define DW_VR_MII_EEE_MCTRL1 0x800b 69 70 /* VR_MII_DIG_CTRL1 */ 71 #define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9) 72 73 /* VR_MII_AN_CTRL */ 74 #define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3 75 #define DW_VR_MII_TX_CONFIG_MASK BIT(3) 76 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1 77 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0 78 #define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1 79 #define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1) 80 #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 81 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 82 83 /* VR_MII_AN_INTR_STS */ 84 #define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1) 85 #define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2 86 #define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2) 87 #define DW_VR_MII_C37_ANSGM_SP_10 0x0 88 #define DW_VR_MII_C37_ANSGM_SP_100 0x1 89 #define DW_VR_MII_C37_ANSGM_SP_1000 0x2 90 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4) 91 92 /* VR MII EEE Control 0 defines */ 93 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */ 94 #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */ 95 #define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */ 96 #define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */ 97 #define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */ 98 #define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */ 99 100 #define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8 101 #define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8) 102 103 /* VR MII EEE Control 1 defines */ 104 #define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */ 105 106 static const int xpcs_usxgmii_features[] = { 107 ETHTOOL_LINK_MODE_Pause_BIT, 108 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 109 ETHTOOL_LINK_MODE_Autoneg_BIT, 110 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 111 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 112 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 113 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 114 __ETHTOOL_LINK_MODE_MASK_NBITS, 115 }; 116 117 static const int xpcs_10gkr_features[] = { 118 ETHTOOL_LINK_MODE_Pause_BIT, 119 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 120 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 121 __ETHTOOL_LINK_MODE_MASK_NBITS, 122 }; 123 124 static const int xpcs_xlgmii_features[] = { 125 ETHTOOL_LINK_MODE_Pause_BIT, 126 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 128 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 129 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 130 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 131 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 132 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 133 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 134 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 136 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 137 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 138 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 139 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 140 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 141 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 142 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 143 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 144 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 145 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 146 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 147 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 148 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 149 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 150 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 151 __ETHTOOL_LINK_MODE_MASK_NBITS, 152 }; 153 154 static const int xpcs_sgmii_features[] = { 155 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 156 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 157 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 158 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 159 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 160 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 161 __ETHTOOL_LINK_MODE_MASK_NBITS, 162 }; 163 164 static const phy_interface_t xpcs_usxgmii_interfaces[] = { 165 PHY_INTERFACE_MODE_USXGMII, 166 PHY_INTERFACE_MODE_MAX, 167 }; 168 169 static const phy_interface_t xpcs_10gkr_interfaces[] = { 170 PHY_INTERFACE_MODE_10GKR, 171 PHY_INTERFACE_MODE_MAX, 172 }; 173 174 static const phy_interface_t xpcs_xlgmii_interfaces[] = { 175 PHY_INTERFACE_MODE_XLGMII, 176 PHY_INTERFACE_MODE_MAX, 177 }; 178 179 static const phy_interface_t xpcs_sgmii_interfaces[] = { 180 PHY_INTERFACE_MODE_SGMII, 181 PHY_INTERFACE_MODE_MAX, 182 }; 183 184 static struct xpcs_id { 185 u32 id; 186 u32 mask; 187 const int *supported; 188 const phy_interface_t *interface; 189 int an_mode; 190 } xpcs_id_list[] = { 191 { 192 .id = SYNOPSYS_XPCS_USXGMII_ID, 193 .mask = SYNOPSYS_XPCS_MASK, 194 .supported = xpcs_usxgmii_features, 195 .interface = xpcs_usxgmii_interfaces, 196 .an_mode = DW_AN_C73, 197 }, { 198 .id = SYNOPSYS_XPCS_10GKR_ID, 199 .mask = SYNOPSYS_XPCS_MASK, 200 .supported = xpcs_10gkr_features, 201 .interface = xpcs_10gkr_interfaces, 202 .an_mode = DW_AN_C73, 203 }, { 204 .id = SYNOPSYS_XPCS_XLGMII_ID, 205 .mask = SYNOPSYS_XPCS_MASK, 206 .supported = xpcs_xlgmii_features, 207 .interface = xpcs_xlgmii_interfaces, 208 .an_mode = DW_AN_C73, 209 }, { 210 .id = SYNOPSYS_XPCS_SGMII_ID, 211 .mask = SYNOPSYS_XPCS_MASK, 212 .supported = xpcs_sgmii_features, 213 .interface = xpcs_sgmii_interfaces, 214 .an_mode = DW_AN_C37_SGMII, 215 }, 216 }; 217 218 static int xpcs_read(struct mdio_xpcs_args *xpcs, int dev, u32 reg) 219 { 220 u32 reg_addr = MII_ADDR_C45 | dev << 16 | reg; 221 222 return mdiobus_read(xpcs->bus, xpcs->addr, reg_addr); 223 } 224 225 static int xpcs_write(struct mdio_xpcs_args *xpcs, int dev, u32 reg, u16 val) 226 { 227 u32 reg_addr = MII_ADDR_C45 | dev << 16 | reg; 228 229 return mdiobus_write(xpcs->bus, xpcs->addr, reg_addr, val); 230 } 231 232 static int xpcs_read_vendor(struct mdio_xpcs_args *xpcs, int dev, u32 reg) 233 { 234 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 235 } 236 237 static int xpcs_write_vendor(struct mdio_xpcs_args *xpcs, int dev, int reg, 238 u16 val) 239 { 240 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 241 } 242 243 static int xpcs_read_vpcs(struct mdio_xpcs_args *xpcs, int reg) 244 { 245 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 246 } 247 248 static int xpcs_write_vpcs(struct mdio_xpcs_args *xpcs, int reg, u16 val) 249 { 250 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 251 } 252 253 static int xpcs_poll_reset(struct mdio_xpcs_args *xpcs, int dev) 254 { 255 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ 256 unsigned int retries = 12; 257 int ret; 258 259 do { 260 msleep(50); 261 ret = xpcs_read(xpcs, dev, MDIO_CTRL1); 262 if (ret < 0) 263 return ret; 264 } while (ret & MDIO_CTRL1_RESET && --retries); 265 266 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; 267 } 268 269 static int xpcs_soft_reset(struct mdio_xpcs_args *xpcs) 270 { 271 int ret, dev; 272 273 switch (xpcs->an_mode) { 274 case DW_AN_C73: 275 dev = MDIO_MMD_PCS; 276 break; 277 case DW_AN_C37_SGMII: 278 dev = MDIO_MMD_VEND2; 279 break; 280 default: 281 return -1; 282 } 283 284 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); 285 if (ret < 0) 286 return ret; 287 288 return xpcs_poll_reset(xpcs, dev); 289 } 290 291 #define xpcs_warn(__xpcs, __state, __args...) \ 292 ({ \ 293 if ((__state)->link) \ 294 dev_warn(&(__xpcs)->bus->dev, ##__args); \ 295 }) 296 297 static int xpcs_read_fault_c73(struct mdio_xpcs_args *xpcs, 298 struct phylink_link_state *state) 299 { 300 int ret; 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_STAT1_FAULT) { 307 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 308 return -EFAULT; 309 } 310 311 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 312 if (ret < 0) 313 return ret; 314 315 if (ret & MDIO_STAT2_RXFAULT) 316 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 317 if (ret & MDIO_STAT2_TXFAULT) 318 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 319 320 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 321 if (ret < 0) 322 return ret; 323 324 if (ret & DW_RXFIFO_ERR) { 325 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 326 return -EFAULT; 327 } 328 329 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 330 if (ret < 0) 331 return ret; 332 333 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 334 xpcs_warn(xpcs, state, "Link is not locked!\n"); 335 336 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 337 if (ret < 0) 338 return ret; 339 340 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 341 xpcs_warn(xpcs, state, "Link has errors!\n"); 342 return -EFAULT; 343 } 344 345 return 0; 346 } 347 348 static int xpcs_read_link_c73(struct mdio_xpcs_args *xpcs, bool an) 349 { 350 bool link = true; 351 int ret; 352 353 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 354 if (ret < 0) 355 return ret; 356 357 if (!(ret & MDIO_STAT1_LSTATUS)) 358 link = false; 359 360 if (an) { 361 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 362 if (ret < 0) 363 return ret; 364 365 if (!(ret & MDIO_STAT1_LSTATUS)) 366 link = false; 367 } 368 369 return link; 370 } 371 372 static int xpcs_get_max_usxgmii_speed(const unsigned long *supported) 373 { 374 int max = SPEED_UNKNOWN; 375 376 if (phylink_test(supported, 1000baseKX_Full)) 377 max = SPEED_1000; 378 if (phylink_test(supported, 2500baseX_Full)) 379 max = SPEED_2500; 380 if (phylink_test(supported, 10000baseKX4_Full)) 381 max = SPEED_10000; 382 if (phylink_test(supported, 10000baseKR_Full)) 383 max = SPEED_10000; 384 385 return max; 386 } 387 388 static int xpcs_config_usxgmii(struct mdio_xpcs_args *xpcs, int speed) 389 { 390 int ret, speed_sel; 391 392 switch (speed) { 393 case SPEED_10: 394 speed_sel = DW_USXGMII_10; 395 break; 396 case SPEED_100: 397 speed_sel = DW_USXGMII_100; 398 break; 399 case SPEED_1000: 400 speed_sel = DW_USXGMII_1000; 401 break; 402 case SPEED_2500: 403 speed_sel = DW_USXGMII_2500; 404 break; 405 case SPEED_5000: 406 speed_sel = DW_USXGMII_5000; 407 break; 408 case SPEED_10000: 409 speed_sel = DW_USXGMII_10000; 410 break; 411 default: 412 /* Nothing to do here */ 413 return -EINVAL; 414 } 415 416 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 417 if (ret < 0) 418 return ret; 419 420 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); 421 if (ret < 0) 422 return ret; 423 424 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 425 if (ret < 0) 426 return ret; 427 428 ret &= ~DW_USXGMII_SS_MASK; 429 ret |= speed_sel | DW_USXGMII_FULL; 430 431 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 432 if (ret < 0) 433 return ret; 434 435 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 436 if (ret < 0) 437 return ret; 438 439 return xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); 440 } 441 442 static int _xpcs_config_aneg_c73(struct mdio_xpcs_args *xpcs) 443 { 444 int ret, adv; 445 446 /* By default, in USXGMII mode XPCS operates at 10G baud and 447 * replicates data to achieve lower speeds. Hereby, in this 448 * default configuration we need to advertise all supported 449 * modes and not only the ones we want to use. 450 */ 451 452 /* SR_AN_ADV3 */ 453 adv = 0; 454 if (phylink_test(xpcs->supported, 2500baseX_Full)) 455 adv |= DW_C73_2500KX; 456 457 /* TODO: 5000baseKR */ 458 459 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 460 if (ret < 0) 461 return ret; 462 463 /* SR_AN_ADV2 */ 464 adv = 0; 465 if (phylink_test(xpcs->supported, 1000baseKX_Full)) 466 adv |= DW_C73_1000KX; 467 if (phylink_test(xpcs->supported, 10000baseKX4_Full)) 468 adv |= DW_C73_10000KX4; 469 if (phylink_test(xpcs->supported, 10000baseKR_Full)) 470 adv |= DW_C73_10000KR; 471 472 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 473 if (ret < 0) 474 return ret; 475 476 /* SR_AN_ADV1 */ 477 adv = DW_C73_AN_ADV_SF; 478 if (phylink_test(xpcs->supported, Pause)) 479 adv |= DW_C73_PAUSE; 480 if (phylink_test(xpcs->supported, Asym_Pause)) 481 adv |= DW_C73_ASYM_PAUSE; 482 483 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 484 } 485 486 static int xpcs_config_aneg_c73(struct mdio_xpcs_args *xpcs) 487 { 488 int ret; 489 490 ret = _xpcs_config_aneg_c73(xpcs); 491 if (ret < 0) 492 return ret; 493 494 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); 495 if (ret < 0) 496 return ret; 497 498 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; 499 500 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); 501 } 502 503 static int xpcs_aneg_done_c73(struct mdio_xpcs_args *xpcs, 504 struct phylink_link_state *state) 505 { 506 int ret; 507 508 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 509 if (ret < 0) 510 return ret; 511 512 if (ret & MDIO_AN_STAT1_COMPLETE) { 513 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); 514 if (ret < 0) 515 return ret; 516 517 /* Check if Aneg outcome is valid */ 518 if (!(ret & DW_C73_AN_ADV_SF)) { 519 xpcs_config_aneg_c73(xpcs); 520 return 0; 521 } 522 523 return 1; 524 } 525 526 return 0; 527 } 528 529 static int xpcs_read_lpa_c73(struct mdio_xpcs_args *xpcs, 530 struct phylink_link_state *state) 531 { 532 int ret; 533 534 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 535 if (ret < 0) 536 return ret; 537 538 if (!(ret & MDIO_AN_STAT1_LPABLE)) { 539 phylink_clear(state->lp_advertising, Autoneg); 540 return 0; 541 } 542 543 phylink_set(state->lp_advertising, Autoneg); 544 545 /* Clause 73 outcome */ 546 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3); 547 if (ret < 0) 548 return ret; 549 550 if (ret & DW_C73_2500KX) 551 phylink_set(state->lp_advertising, 2500baseX_Full); 552 553 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2); 554 if (ret < 0) 555 return ret; 556 557 if (ret & DW_C73_1000KX) 558 phylink_set(state->lp_advertising, 1000baseKX_Full); 559 if (ret & DW_C73_10000KX4) 560 phylink_set(state->lp_advertising, 10000baseKX4_Full); 561 if (ret & DW_C73_10000KR) 562 phylink_set(state->lp_advertising, 10000baseKR_Full); 563 564 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); 565 if (ret < 0) 566 return ret; 567 568 if (ret & DW_C73_PAUSE) 569 phylink_set(state->lp_advertising, Pause); 570 if (ret & DW_C73_ASYM_PAUSE) 571 phylink_set(state->lp_advertising, Asym_Pause); 572 573 linkmode_and(state->lp_advertising, state->lp_advertising, 574 state->advertising); 575 return 0; 576 } 577 578 static void xpcs_resolve_lpa_c73(struct mdio_xpcs_args *xpcs, 579 struct phylink_link_state *state) 580 { 581 int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising); 582 583 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 584 state->speed = max_speed; 585 state->duplex = DUPLEX_FULL; 586 } 587 588 static int xpcs_get_max_xlgmii_speed(struct mdio_xpcs_args *xpcs, 589 struct phylink_link_state *state) 590 { 591 unsigned long *adv = state->advertising; 592 int speed = SPEED_UNKNOWN; 593 int bit; 594 595 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 596 int new_speed = SPEED_UNKNOWN; 597 598 switch (bit) { 599 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 600 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 601 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 602 new_speed = SPEED_25000; 603 break; 604 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 605 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 606 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 607 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 608 new_speed = SPEED_40000; 609 break; 610 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 611 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 612 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 613 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 614 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 615 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 616 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 617 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 618 new_speed = SPEED_50000; 619 break; 620 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 621 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 622 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 623 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 624 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 625 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 626 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 627 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 628 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 629 new_speed = SPEED_100000; 630 break; 631 default: 632 continue; 633 } 634 635 if (new_speed > speed) 636 speed = new_speed; 637 } 638 639 return speed; 640 } 641 642 static void xpcs_resolve_pma(struct mdio_xpcs_args *xpcs, 643 struct phylink_link_state *state) 644 { 645 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 646 state->duplex = DUPLEX_FULL; 647 648 switch (state->interface) { 649 case PHY_INTERFACE_MODE_10GKR: 650 state->speed = SPEED_10000; 651 break; 652 case PHY_INTERFACE_MODE_XLGMII: 653 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 654 break; 655 default: 656 state->speed = SPEED_UNKNOWN; 657 break; 658 } 659 } 660 661 static int xpcs_validate(struct mdio_xpcs_args *xpcs, 662 unsigned long *supported, 663 struct phylink_link_state *state) 664 { 665 linkmode_and(supported, supported, xpcs->supported); 666 linkmode_and(state->advertising, state->advertising, xpcs->supported); 667 return 0; 668 } 669 670 static int xpcs_config_eee(struct mdio_xpcs_args *xpcs, int mult_fact_100ns, 671 int enable) 672 { 673 int ret; 674 675 if (enable) { 676 /* Enable EEE */ 677 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 678 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 679 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 680 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT; 681 } else { 682 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); 683 if (ret < 0) 684 return ret; 685 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 686 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 687 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 688 DW_VR_MII_EEE_MULT_FACT_100NS); 689 } 690 691 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); 692 if (ret < 0) 693 return ret; 694 695 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); 696 if (ret < 0) 697 return ret; 698 699 ret |= DW_VR_MII_EEE_TRN_LPI; 700 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); 701 } 702 703 static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs) 704 { 705 int ret; 706 707 /* For AN for C37 SGMII mode, the settings are :- 708 * 1) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 709 * 2) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 710 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 711 * 3) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 712 * speed/duplex mode change by HW after SGMII AN complete) 713 * 714 * Note: Since it is MAC side SGMII, there is no need to set 715 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 716 * PHY about the link state change after C28 AN is completed 717 * between PHY and Link Partner. There is also no need to 718 * trigger AN restart for MAC-side SGMII. 719 */ 720 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); 721 if (ret < 0) 722 return ret; 723 724 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); 725 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII << 726 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT & 727 DW_VR_MII_PCS_MODE_MASK); 728 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII << 729 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT & 730 DW_VR_MII_TX_CONFIG_MASK); 731 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 732 if (ret < 0) 733 return ret; 734 735 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); 736 if (ret < 0) 737 return ret; 738 739 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 740 741 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); 742 } 743 744 static int xpcs_config(struct mdio_xpcs_args *xpcs, 745 const struct phylink_link_state *state) 746 { 747 int ret; 748 749 switch (xpcs->an_mode) { 750 case DW_AN_C73: 751 if (state->an_enabled) { 752 ret = xpcs_config_aneg_c73(xpcs); 753 if (ret) 754 return ret; 755 } 756 break; 757 case DW_AN_C37_SGMII: 758 ret = xpcs_config_aneg_c37_sgmii(xpcs); 759 if (ret) 760 return ret; 761 break; 762 default: 763 return -1; 764 } 765 766 return 0; 767 } 768 769 static int xpcs_get_state_c73(struct mdio_xpcs_args *xpcs, 770 struct phylink_link_state *state) 771 { 772 int ret; 773 774 /* Link needs to be read first ... */ 775 state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0; 776 777 /* ... and then we check the faults. */ 778 ret = xpcs_read_fault_c73(xpcs, state); 779 if (ret) { 780 ret = xpcs_soft_reset(xpcs); 781 if (ret) 782 return ret; 783 784 state->link = 0; 785 786 return xpcs_config(xpcs, state); 787 } 788 789 if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state)) { 790 state->an_complete = true; 791 xpcs_read_lpa_c73(xpcs, state); 792 xpcs_resolve_lpa_c73(xpcs, state); 793 } else if (state->an_enabled) { 794 state->link = 0; 795 } else if (state->link) { 796 xpcs_resolve_pma(xpcs, state); 797 } 798 799 return 0; 800 } 801 802 static int xpcs_get_state_c37_sgmii(struct mdio_xpcs_args *xpcs, 803 struct phylink_link_state *state) 804 { 805 int ret; 806 807 /* Reset link_state */ 808 state->link = false; 809 state->speed = SPEED_UNKNOWN; 810 state->duplex = DUPLEX_UNKNOWN; 811 state->pause = 0; 812 813 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 814 * status, speed and duplex. 815 */ 816 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 817 if (ret < 0) 818 return false; 819 820 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 821 int speed_value; 822 823 state->link = true; 824 825 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >> 826 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT; 827 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 828 state->speed = SPEED_1000; 829 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 830 state->speed = SPEED_100; 831 else 832 state->speed = SPEED_10; 833 834 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 835 state->duplex = DUPLEX_FULL; 836 else 837 state->duplex = DUPLEX_HALF; 838 } 839 840 return 0; 841 } 842 843 static int xpcs_get_state(struct mdio_xpcs_args *xpcs, 844 struct phylink_link_state *state) 845 { 846 int ret; 847 848 switch (xpcs->an_mode) { 849 case DW_AN_C73: 850 ret = xpcs_get_state_c73(xpcs, state); 851 if (ret) 852 return ret; 853 break; 854 case DW_AN_C37_SGMII: 855 ret = xpcs_get_state_c37_sgmii(xpcs, state); 856 if (ret) 857 return ret; 858 break; 859 default: 860 return -1; 861 } 862 863 return 0; 864 } 865 866 static int xpcs_link_up(struct mdio_xpcs_args *xpcs, int speed, 867 phy_interface_t interface) 868 { 869 if (interface == PHY_INTERFACE_MODE_USXGMII) 870 return xpcs_config_usxgmii(xpcs, speed); 871 872 return 0; 873 } 874 875 static u32 xpcs_get_id(struct mdio_xpcs_args *xpcs) 876 { 877 int ret; 878 u32 id; 879 880 /* First, search C73 PCS using PCS MMD */ 881 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 882 if (ret < 0) 883 return 0xffffffff; 884 885 id = ret << 16; 886 887 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 888 if (ret < 0) 889 return 0xffffffff; 890 891 /* If Device IDs are not all zeros, we found C73 AN-type device */ 892 if (id | ret) 893 return id | ret; 894 895 /* Next, search C37 PCS using Vendor-Specific MII MMD */ 896 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 897 if (ret < 0) 898 return 0xffffffff; 899 900 id = ret << 16; 901 902 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 903 if (ret < 0) 904 return 0xffffffff; 905 906 /* If Device IDs are not all zeros, we found C37 AN-type device */ 907 if (id | ret) 908 return id | ret; 909 910 return 0xffffffff; 911 } 912 913 static bool xpcs_check_features(struct mdio_xpcs_args *xpcs, 914 struct xpcs_id *match, 915 phy_interface_t interface) 916 { 917 int i; 918 919 for (i = 0; match->interface[i] != PHY_INTERFACE_MODE_MAX; i++) { 920 if (match->interface[i] == interface) 921 break; 922 } 923 924 if (match->interface[i] == PHY_INTERFACE_MODE_MAX) 925 return false; 926 927 for (i = 0; match->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 928 set_bit(match->supported[i], xpcs->supported); 929 930 xpcs->an_mode = match->an_mode; 931 932 return true; 933 } 934 935 static int xpcs_probe(struct mdio_xpcs_args *xpcs, phy_interface_t interface) 936 { 937 u32 xpcs_id = xpcs_get_id(xpcs); 938 struct xpcs_id *match = NULL; 939 int i; 940 941 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) { 942 struct xpcs_id *entry = &xpcs_id_list[i]; 943 944 if ((xpcs_id & entry->mask) == entry->id) { 945 match = entry; 946 947 if (xpcs_check_features(xpcs, match, interface)) 948 return xpcs_soft_reset(xpcs); 949 } 950 } 951 952 return -ENODEV; 953 } 954 955 static struct mdio_xpcs_ops xpcs_ops = { 956 .validate = xpcs_validate, 957 .config = xpcs_config, 958 .get_state = xpcs_get_state, 959 .link_up = xpcs_link_up, 960 .probe = xpcs_probe, 961 .config_eee = xpcs_config_eee, 962 }; 963 964 struct mdio_xpcs_ops *mdio_xpcs_get_ops(void) 965 { 966 return &xpcs_ops; 967 } 968 EXPORT_SYMBOL_GPL(mdio_xpcs_get_ops); 969 970 MODULE_LICENSE("GPL v2"); 971