1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/pcs/pcs-xpcs.h> 11 #include <linux/mdio.h> 12 #include <linux/phylink.h> 13 #include <linux/workqueue.h> 14 #include "pcs-xpcs.h" 15 16 #define phylink_pcs_to_xpcs(pl_pcs) \ 17 container_of((pl_pcs), struct dw_xpcs, pcs) 18 19 static const int xpcs_usxgmii_features[] = { 20 ETHTOOL_LINK_MODE_Pause_BIT, 21 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 22 ETHTOOL_LINK_MODE_Autoneg_BIT, 23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 27 __ETHTOOL_LINK_MODE_MASK_NBITS, 28 }; 29 30 static const int xpcs_10gkr_features[] = { 31 ETHTOOL_LINK_MODE_Pause_BIT, 32 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 34 __ETHTOOL_LINK_MODE_MASK_NBITS, 35 }; 36 37 static const int xpcs_xlgmii_features[] = { 38 ETHTOOL_LINK_MODE_Pause_BIT, 39 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 64 __ETHTOOL_LINK_MODE_MASK_NBITS, 65 }; 66 67 static const int xpcs_10gbaser_features[] = { 68 ETHTOOL_LINK_MODE_Pause_BIT, 69 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 70 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 71 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 72 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 73 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 74 __ETHTOOL_LINK_MODE_MASK_NBITS, 75 }; 76 77 static const int xpcs_sgmii_features[] = { 78 ETHTOOL_LINK_MODE_Pause_BIT, 79 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 80 ETHTOOL_LINK_MODE_Autoneg_BIT, 81 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 82 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 83 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 84 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 85 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 86 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 87 __ETHTOOL_LINK_MODE_MASK_NBITS, 88 }; 89 90 static const int xpcs_1000basex_features[] = { 91 ETHTOOL_LINK_MODE_Pause_BIT, 92 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 93 ETHTOOL_LINK_MODE_Autoneg_BIT, 94 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 95 __ETHTOOL_LINK_MODE_MASK_NBITS, 96 }; 97 98 static const int xpcs_2500basex_features[] = { 99 ETHTOOL_LINK_MODE_Pause_BIT, 100 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 101 ETHTOOL_LINK_MODE_Autoneg_BIT, 102 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 103 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 104 __ETHTOOL_LINK_MODE_MASK_NBITS, 105 }; 106 107 static const phy_interface_t xpcs_usxgmii_interfaces[] = { 108 PHY_INTERFACE_MODE_USXGMII, 109 }; 110 111 static const phy_interface_t xpcs_10gkr_interfaces[] = { 112 PHY_INTERFACE_MODE_10GKR, 113 }; 114 115 static const phy_interface_t xpcs_xlgmii_interfaces[] = { 116 PHY_INTERFACE_MODE_XLGMII, 117 }; 118 119 static const phy_interface_t xpcs_10gbaser_interfaces[] = { 120 PHY_INTERFACE_MODE_10GBASER, 121 }; 122 123 static const phy_interface_t xpcs_sgmii_interfaces[] = { 124 PHY_INTERFACE_MODE_SGMII, 125 }; 126 127 static const phy_interface_t xpcs_1000basex_interfaces[] = { 128 PHY_INTERFACE_MODE_1000BASEX, 129 }; 130 131 static const phy_interface_t xpcs_2500basex_interfaces[] = { 132 PHY_INTERFACE_MODE_2500BASEX, 133 PHY_INTERFACE_MODE_MAX, 134 }; 135 136 enum { 137 DW_XPCS_USXGMII, 138 DW_XPCS_10GKR, 139 DW_XPCS_XLGMII, 140 DW_XPCS_10GBASER, 141 DW_XPCS_SGMII, 142 DW_XPCS_1000BASEX, 143 DW_XPCS_2500BASEX, 144 DW_XPCS_INTERFACE_MAX, 145 }; 146 147 struct xpcs_compat { 148 const int *supported; 149 const phy_interface_t *interface; 150 int num_interfaces; 151 int an_mode; 152 int (*pma_config)(struct dw_xpcs *xpcs); 153 }; 154 155 struct xpcs_id { 156 u32 id; 157 u32 mask; 158 const struct xpcs_compat *compat; 159 }; 160 161 static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id, 162 phy_interface_t interface) 163 { 164 int i, j; 165 166 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) { 167 const struct xpcs_compat *compat = &id->compat[i]; 168 169 for (j = 0; j < compat->num_interfaces; j++) 170 if (compat->interface[j] == interface) 171 return compat; 172 } 173 174 return NULL; 175 } 176 177 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 178 { 179 const struct xpcs_compat *compat; 180 181 compat = xpcs_find_compat(xpcs->id, interface); 182 if (!compat) 183 return -ENODEV; 184 185 return compat->an_mode; 186 } 187 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 188 189 static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat, 190 enum ethtool_link_mode_bit_indices linkmode) 191 { 192 int i; 193 194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 195 if (compat->supported[i] == linkmode) 196 return true; 197 198 return false; 199 } 200 201 #define xpcs_linkmode_supported(compat, mode) \ 202 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 203 204 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 205 { 206 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 207 } 208 209 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 210 { 211 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 212 } 213 214 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 215 u16 mask, u16 set) 216 { 217 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 218 } 219 220 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 221 { 222 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 223 } 224 225 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 226 u16 val) 227 { 228 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 229 } 230 231 static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 232 { 233 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 234 } 235 236 static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 237 { 238 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 239 } 240 241 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 242 { 243 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ 244 unsigned int retries = 12; 245 int ret; 246 247 do { 248 msleep(50); 249 ret = xpcs_read(xpcs, dev, MDIO_CTRL1); 250 if (ret < 0) 251 return ret; 252 } while (ret & MDIO_CTRL1_RESET && --retries); 253 254 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; 255 } 256 257 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 258 const struct xpcs_compat *compat) 259 { 260 int ret, dev; 261 262 switch (compat->an_mode) { 263 case DW_AN_C73: 264 case DW_10GBASER: 265 dev = MDIO_MMD_PCS; 266 break; 267 case DW_AN_C37_SGMII: 268 case DW_2500BASEX: 269 case DW_AN_C37_1000BASEX: 270 dev = MDIO_MMD_VEND2; 271 break; 272 default: 273 return -1; 274 } 275 276 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); 277 if (ret < 0) 278 return ret; 279 280 return xpcs_poll_reset(xpcs, dev); 281 } 282 283 #define xpcs_warn(__xpcs, __state, __args...) \ 284 ({ \ 285 if ((__state)->link) \ 286 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 287 }) 288 289 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 290 struct phylink_link_state *state, 291 u16 pcs_stat1) 292 { 293 int ret; 294 295 if (pcs_stat1 & MDIO_STAT1_FAULT) { 296 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 297 return -EFAULT; 298 } 299 300 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 301 if (ret < 0) 302 return ret; 303 304 if (ret & MDIO_STAT2_RXFAULT) 305 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 306 if (ret & MDIO_STAT2_TXFAULT) 307 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 308 309 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 310 if (ret < 0) 311 return ret; 312 313 if (ret & DW_RXFIFO_ERR) { 314 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 315 return -EFAULT; 316 } 317 318 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 319 if (ret < 0) 320 return ret; 321 322 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 323 xpcs_warn(xpcs, state, "Link is not locked!\n"); 324 325 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 326 if (ret < 0) 327 return ret; 328 329 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 330 xpcs_warn(xpcs, state, "Link has errors!\n"); 331 return -EFAULT; 332 } 333 334 return 0; 335 } 336 337 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed) 338 { 339 int ret, speed_sel; 340 341 switch (speed) { 342 case SPEED_10: 343 speed_sel = DW_USXGMII_10; 344 break; 345 case SPEED_100: 346 speed_sel = DW_USXGMII_100; 347 break; 348 case SPEED_1000: 349 speed_sel = DW_USXGMII_1000; 350 break; 351 case SPEED_2500: 352 speed_sel = DW_USXGMII_2500; 353 break; 354 case SPEED_5000: 355 speed_sel = DW_USXGMII_5000; 356 break; 357 case SPEED_10000: 358 speed_sel = DW_USXGMII_10000; 359 break; 360 default: 361 /* Nothing to do here */ 362 return; 363 } 364 365 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 366 if (ret < 0) 367 goto out; 368 369 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); 370 if (ret < 0) 371 goto out; 372 373 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 374 if (ret < 0) 375 goto out; 376 377 ret &= ~DW_USXGMII_SS_MASK; 378 ret |= speed_sel | DW_USXGMII_FULL; 379 380 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 381 if (ret < 0) 382 goto out; 383 384 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); 385 if (ret < 0) 386 goto out; 387 388 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); 389 if (ret < 0) 390 goto out; 391 392 return; 393 394 out: 395 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret)); 396 } 397 398 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 399 const struct xpcs_compat *compat) 400 { 401 int ret, adv; 402 403 /* By default, in USXGMII mode XPCS operates at 10G baud and 404 * replicates data to achieve lower speeds. Hereby, in this 405 * default configuration we need to advertise all supported 406 * modes and not only the ones we want to use. 407 */ 408 409 /* SR_AN_ADV3 */ 410 adv = 0; 411 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 412 adv |= DW_C73_2500KX; 413 414 /* TODO: 5000baseKR */ 415 416 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 417 if (ret < 0) 418 return ret; 419 420 /* SR_AN_ADV2 */ 421 adv = 0; 422 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 423 adv |= DW_C73_1000KX; 424 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 425 adv |= DW_C73_10000KX4; 426 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 427 adv |= DW_C73_10000KR; 428 429 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 430 if (ret < 0) 431 return ret; 432 433 /* SR_AN_ADV1 */ 434 adv = DW_C73_AN_ADV_SF; 435 if (xpcs_linkmode_supported(compat, Pause)) 436 adv |= DW_C73_PAUSE; 437 if (xpcs_linkmode_supported(compat, Asym_Pause)) 438 adv |= DW_C73_ASYM_PAUSE; 439 440 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 441 } 442 443 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 444 const struct xpcs_compat *compat) 445 { 446 int ret; 447 448 ret = _xpcs_config_aneg_c73(xpcs, compat); 449 if (ret < 0) 450 return ret; 451 452 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); 453 if (ret < 0) 454 return ret; 455 456 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; 457 458 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); 459 } 460 461 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 462 struct phylink_link_state *state, 463 const struct xpcs_compat *compat, u16 an_stat1) 464 { 465 int ret; 466 467 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 468 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 469 if (ret < 0) 470 return ret; 471 472 /* Check if Aneg outcome is valid */ 473 if (!(ret & DW_C73_AN_ADV_SF)) { 474 xpcs_config_aneg_c73(xpcs, compat); 475 return 0; 476 } 477 478 return 1; 479 } 480 481 return 0; 482 } 483 484 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 485 struct phylink_link_state *state, u16 an_stat1) 486 { 487 u16 lpa[3]; 488 int i, ret; 489 490 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 491 phylink_clear(state->lp_advertising, Autoneg); 492 return 0; 493 } 494 495 phylink_set(state->lp_advertising, Autoneg); 496 497 /* Read Clause 73 link partner advertisement */ 498 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 499 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 500 if (ret < 0) 501 return ret; 502 503 lpa[i] = ret; 504 } 505 506 mii_c73_mod_linkmode(state->lp_advertising, lpa); 507 508 return 0; 509 } 510 511 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 512 struct phylink_link_state *state) 513 { 514 unsigned long *adv = state->advertising; 515 int speed = SPEED_UNKNOWN; 516 int bit; 517 518 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 519 int new_speed = SPEED_UNKNOWN; 520 521 switch (bit) { 522 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 523 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 524 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 525 new_speed = SPEED_25000; 526 break; 527 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 528 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 529 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 530 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 531 new_speed = SPEED_40000; 532 break; 533 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 534 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 535 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 536 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 537 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 538 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 539 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 540 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 541 new_speed = SPEED_50000; 542 break; 543 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 544 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 545 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 546 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 547 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 548 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 549 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 550 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 551 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 552 new_speed = SPEED_100000; 553 break; 554 default: 555 continue; 556 } 557 558 if (new_speed > speed) 559 speed = new_speed; 560 } 561 562 return speed; 563 } 564 565 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 566 struct phylink_link_state *state) 567 { 568 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 569 state->duplex = DUPLEX_FULL; 570 571 switch (state->interface) { 572 case PHY_INTERFACE_MODE_10GKR: 573 state->speed = SPEED_10000; 574 break; 575 case PHY_INTERFACE_MODE_XLGMII: 576 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 577 break; 578 default: 579 state->speed = SPEED_UNKNOWN; 580 break; 581 } 582 } 583 584 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 585 const struct phylink_link_state *state) 586 { 587 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 588 const struct xpcs_compat *compat; 589 struct dw_xpcs *xpcs; 590 int i; 591 592 xpcs = phylink_pcs_to_xpcs(pcs); 593 compat = xpcs_find_compat(xpcs->id, state->interface); 594 595 /* Populate the supported link modes for this PHY interface type. 596 * FIXME: what about the port modes and autoneg bit? This masks 597 * all those away. 598 */ 599 if (compat) 600 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 601 set_bit(compat->supported[i], xpcs_supported); 602 603 linkmode_and(supported, supported, xpcs_supported); 604 605 return 0; 606 } 607 608 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 609 { 610 int i, j; 611 612 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) { 613 const struct xpcs_compat *compat = &xpcs->id->compat[i]; 614 615 for (j = 0; j < compat->num_interfaces; j++) 616 if (compat->interface[j] < PHY_INTERFACE_MODE_MAX) 617 __set_bit(compat->interface[j], interfaces); 618 } 619 } 620 EXPORT_SYMBOL_GPL(xpcs_get_interfaces); 621 622 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) 623 { 624 int ret; 625 626 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); 627 if (ret < 0) 628 return ret; 629 630 if (enable) { 631 /* Enable EEE */ 632 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 633 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 634 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 635 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT; 636 } else { 637 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 638 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 639 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 640 DW_VR_MII_EEE_MULT_FACT_100NS); 641 } 642 643 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); 644 if (ret < 0) 645 return ret; 646 647 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); 648 if (ret < 0) 649 return ret; 650 651 if (enable) 652 ret |= DW_VR_MII_EEE_TRN_LPI; 653 else 654 ret &= ~DW_VR_MII_EEE_TRN_LPI; 655 656 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); 657 } 658 EXPORT_SYMBOL_GPL(xpcs_config_eee); 659 660 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode) 661 { 662 int ret, mdio_ctrl; 663 664 /* For AN for C37 SGMII mode, the settings are :- 665 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 666 it is already enabled) 667 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 668 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 669 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 670 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 671 * speed/duplex mode change by HW after SGMII AN complete) 672 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 673 * 674 * Note: Since it is MAC side SGMII, there is no need to set 675 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 676 * PHY about the link state change after C28 AN is completed 677 * between PHY and Link Partner. There is also no need to 678 * trigger AN restart for MAC-side SGMII. 679 */ 680 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 681 if (mdio_ctrl < 0) 682 return mdio_ctrl; 683 684 if (mdio_ctrl & AN_CL37_EN) { 685 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 686 mdio_ctrl & ~AN_CL37_EN); 687 if (ret < 0) 688 return ret; 689 } 690 691 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); 692 if (ret < 0) 693 return ret; 694 695 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); 696 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII << 697 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT & 698 DW_VR_MII_PCS_MODE_MASK); 699 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII << 700 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT & 701 DW_VR_MII_TX_CONFIG_MASK); 702 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 703 if (ret < 0) 704 return ret; 705 706 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); 707 if (ret < 0) 708 return ret; 709 710 if (phylink_autoneg_inband(mode)) 711 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 712 else 713 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 714 715 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); 716 if (ret < 0) 717 return ret; 718 719 if (phylink_autoneg_inband(mode)) 720 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 721 mdio_ctrl | AN_CL37_EN); 722 723 return ret; 724 } 725 726 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, unsigned int mode, 727 const unsigned long *advertising) 728 { 729 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 730 int ret, mdio_ctrl, adv; 731 bool changed = 0; 732 733 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 734 * be disabled first:- 735 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 736 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 737 */ 738 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 739 if (mdio_ctrl < 0) 740 return mdio_ctrl; 741 742 if (mdio_ctrl & AN_CL37_EN) { 743 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 744 mdio_ctrl & ~AN_CL37_EN); 745 if (ret < 0) 746 return ret; 747 } 748 749 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); 750 if (ret < 0) 751 return ret; 752 753 ret &= ~DW_VR_MII_PCS_MODE_MASK; 754 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); 755 if (ret < 0) 756 return ret; 757 758 /* Check for advertising changes and update the C45 MII ADV 759 * register accordingly. 760 */ 761 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 762 advertising); 763 if (adv >= 0) { 764 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 765 MII_ADVERTISE, 0xffff, adv); 766 if (ret < 0) 767 return ret; 768 769 changed = ret; 770 } 771 772 /* Clear CL37 AN complete status */ 773 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 774 if (ret < 0) 775 return ret; 776 777 if (phylink_autoneg_inband(mode) && 778 linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) { 779 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 780 mdio_ctrl | AN_CL37_EN); 781 if (ret < 0) 782 return ret; 783 } 784 785 return changed; 786 } 787 788 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 789 { 790 int ret; 791 792 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); 793 if (ret < 0) 794 return ret; 795 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN; 796 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 797 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); 798 if (ret < 0) 799 return ret; 800 801 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 802 if (ret < 0) 803 return ret; 804 ret &= ~AN_CL37_EN; 805 ret |= SGMII_SPEED_SS6; 806 ret &= ~SGMII_SPEED_SS13; 807 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret); 808 } 809 810 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 811 unsigned int mode, const unsigned long *advertising) 812 { 813 const struct xpcs_compat *compat; 814 int ret; 815 816 compat = xpcs_find_compat(xpcs->id, interface); 817 if (!compat) 818 return -ENODEV; 819 820 switch (compat->an_mode) { 821 case DW_10GBASER: 822 break; 823 case DW_AN_C73: 824 if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) { 825 ret = xpcs_config_aneg_c73(xpcs, compat); 826 if (ret) 827 return ret; 828 } 829 break; 830 case DW_AN_C37_SGMII: 831 ret = xpcs_config_aneg_c37_sgmii(xpcs, mode); 832 if (ret) 833 return ret; 834 break; 835 case DW_AN_C37_1000BASEX: 836 ret = xpcs_config_aneg_c37_1000basex(xpcs, mode, 837 advertising); 838 if (ret) 839 return ret; 840 break; 841 case DW_2500BASEX: 842 ret = xpcs_config_2500basex(xpcs); 843 if (ret) 844 return ret; 845 break; 846 default: 847 return -1; 848 } 849 850 if (compat->pma_config) { 851 ret = compat->pma_config(xpcs); 852 if (ret) 853 return ret; 854 } 855 856 return 0; 857 } 858 EXPORT_SYMBOL_GPL(xpcs_do_config); 859 860 static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode, 861 phy_interface_t interface, 862 const unsigned long *advertising, 863 bool permit_pause_to_mac) 864 { 865 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 866 867 return xpcs_do_config(xpcs, interface, mode, advertising); 868 } 869 870 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 871 struct phylink_link_state *state, 872 const struct xpcs_compat *compat) 873 { 874 bool an_enabled; 875 int pcs_stat1; 876 int an_stat1; 877 int ret; 878 879 /* The link status bit is latching-low, so it is important to 880 * avoid unnecessary re-reads of this register to avoid missing 881 * a link-down event. 882 */ 883 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 884 if (pcs_stat1 < 0) { 885 state->link = false; 886 return pcs_stat1; 887 } 888 889 /* Link needs to be read first ... */ 890 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 891 892 /* ... and then we check the faults. */ 893 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 894 if (ret) { 895 ret = xpcs_soft_reset(xpcs, compat); 896 if (ret) 897 return ret; 898 899 state->link = 0; 900 901 return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL); 902 } 903 904 /* There is no point doing anything else if the link is down. */ 905 if (!state->link) 906 return 0; 907 908 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 909 state->advertising); 910 if (an_enabled) { 911 /* The link status bit is latching-low, so it is important to 912 * avoid unnecessary re-reads of this register to avoid missing 913 * a link-down event. 914 */ 915 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 916 if (an_stat1 < 0) { 917 state->link = false; 918 return an_stat1; 919 } 920 921 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 922 an_stat1); 923 if (!state->an_complete) { 924 state->link = false; 925 return 0; 926 } 927 928 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 929 if (ret < 0) { 930 state->link = false; 931 return ret; 932 } 933 934 phylink_resolve_c73(state); 935 } else { 936 xpcs_resolve_pma(xpcs, state); 937 } 938 939 return 0; 940 } 941 942 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 943 struct phylink_link_state *state) 944 { 945 int ret; 946 947 /* Reset link_state */ 948 state->link = false; 949 state->speed = SPEED_UNKNOWN; 950 state->duplex = DUPLEX_UNKNOWN; 951 state->pause = 0; 952 953 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 954 * status, speed and duplex. 955 */ 956 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 957 if (ret < 0) 958 return ret; 959 960 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 961 int speed_value; 962 963 state->link = true; 964 965 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >> 966 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT; 967 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 968 state->speed = SPEED_1000; 969 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 970 state->speed = SPEED_100; 971 else 972 state->speed = SPEED_10; 973 974 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 975 state->duplex = DUPLEX_FULL; 976 else 977 state->duplex = DUPLEX_HALF; 978 } 979 980 return 0; 981 } 982 983 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 984 struct phylink_link_state *state) 985 { 986 int lpa, bmsr; 987 988 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 989 state->advertising)) { 990 /* Reset link state */ 991 state->link = false; 992 993 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 994 if (lpa < 0 || lpa & LPA_RFAULT) 995 return lpa; 996 997 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 998 if (bmsr < 0) 999 return bmsr; 1000 1001 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static void xpcs_get_state(struct phylink_pcs *pcs, 1008 struct phylink_link_state *state) 1009 { 1010 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1011 const struct xpcs_compat *compat; 1012 int ret; 1013 1014 compat = xpcs_find_compat(xpcs->id, state->interface); 1015 if (!compat) 1016 return; 1017 1018 switch (compat->an_mode) { 1019 case DW_10GBASER: 1020 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1021 break; 1022 case DW_AN_C73: 1023 ret = xpcs_get_state_c73(xpcs, state, compat); 1024 if (ret) { 1025 pr_err("xpcs_get_state_c73 returned %pe\n", 1026 ERR_PTR(ret)); 1027 return; 1028 } 1029 break; 1030 case DW_AN_C37_SGMII: 1031 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1032 if (ret) { 1033 pr_err("xpcs_get_state_c37_sgmii returned %pe\n", 1034 ERR_PTR(ret)); 1035 } 1036 break; 1037 case DW_AN_C37_1000BASEX: 1038 ret = xpcs_get_state_c37_1000basex(xpcs, state); 1039 if (ret) { 1040 pr_err("xpcs_get_state_c37_1000basex returned %pe\n", 1041 ERR_PTR(ret)); 1042 } 1043 break; 1044 default: 1045 return; 1046 } 1047 } 1048 1049 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode, 1050 int speed, int duplex) 1051 { 1052 int val, ret; 1053 1054 if (phylink_autoneg_inband(mode)) 1055 return; 1056 1057 val = mii_bmcr_encode_fixed(speed, duplex); 1058 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); 1059 if (ret) 1060 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); 1061 } 1062 1063 static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int mode, 1064 int speed, int duplex) 1065 { 1066 int val, ret; 1067 1068 if (phylink_autoneg_inband(mode)) 1069 return; 1070 1071 switch (speed) { 1072 case SPEED_1000: 1073 val = BMCR_SPEED1000; 1074 break; 1075 case SPEED_100: 1076 case SPEED_10: 1077 default: 1078 pr_err("%s: speed = %d\n", __func__, speed); 1079 return; 1080 } 1081 1082 if (duplex == DUPLEX_FULL) 1083 val |= BMCR_FULLDPLX; 1084 else 1085 pr_err("%s: half duplex not supported\n", __func__); 1086 1087 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); 1088 if (ret) 1089 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); 1090 } 1091 1092 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 1093 phy_interface_t interface, int speed, int duplex) 1094 { 1095 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1096 1097 if (interface == PHY_INTERFACE_MODE_USXGMII) 1098 return xpcs_config_usxgmii(xpcs, speed); 1099 if (interface == PHY_INTERFACE_MODE_SGMII) 1100 return xpcs_link_up_sgmii(xpcs, mode, speed, duplex); 1101 if (interface == PHY_INTERFACE_MODE_1000BASEX) 1102 return xpcs_link_up_1000basex(xpcs, mode, speed, duplex); 1103 } 1104 EXPORT_SYMBOL_GPL(xpcs_link_up); 1105 1106 static void xpcs_an_restart(struct phylink_pcs *pcs) 1107 { 1108 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1109 int ret; 1110 1111 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 1112 if (ret >= 0) { 1113 ret |= BMCR_ANRESTART; 1114 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 1115 } 1116 } 1117 1118 static u32 xpcs_get_id(struct dw_xpcs *xpcs) 1119 { 1120 int ret; 1121 u32 id; 1122 1123 /* First, search C73 PCS using PCS MMD */ 1124 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1125 if (ret < 0) 1126 return 0xffffffff; 1127 1128 id = ret << 16; 1129 1130 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1131 if (ret < 0) 1132 return 0xffffffff; 1133 1134 /* If Device IDs are not all zeros or all ones, 1135 * we found C73 AN-type device 1136 */ 1137 if ((id | ret) && (id | ret) != 0xffffffff) 1138 return id | ret; 1139 1140 /* Next, search C37 PCS using Vendor-Specific MII MMD */ 1141 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1142 if (ret < 0) 1143 return 0xffffffff; 1144 1145 id = ret << 16; 1146 1147 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1148 if (ret < 0) 1149 return 0xffffffff; 1150 1151 /* If Device IDs are not all zeros, we found C37 AN-type device */ 1152 if (id | ret) 1153 return id | ret; 1154 1155 return 0xffffffff; 1156 } 1157 1158 static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { 1159 [DW_XPCS_USXGMII] = { 1160 .supported = xpcs_usxgmii_features, 1161 .interface = xpcs_usxgmii_interfaces, 1162 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces), 1163 .an_mode = DW_AN_C73, 1164 }, 1165 [DW_XPCS_10GKR] = { 1166 .supported = xpcs_10gkr_features, 1167 .interface = xpcs_10gkr_interfaces, 1168 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces), 1169 .an_mode = DW_AN_C73, 1170 }, 1171 [DW_XPCS_XLGMII] = { 1172 .supported = xpcs_xlgmii_features, 1173 .interface = xpcs_xlgmii_interfaces, 1174 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces), 1175 .an_mode = DW_AN_C73, 1176 }, 1177 [DW_XPCS_10GBASER] = { 1178 .supported = xpcs_10gbaser_features, 1179 .interface = xpcs_10gbaser_interfaces, 1180 .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces), 1181 .an_mode = DW_10GBASER, 1182 }, 1183 [DW_XPCS_SGMII] = { 1184 .supported = xpcs_sgmii_features, 1185 .interface = xpcs_sgmii_interfaces, 1186 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), 1187 .an_mode = DW_AN_C37_SGMII, 1188 }, 1189 [DW_XPCS_1000BASEX] = { 1190 .supported = xpcs_1000basex_features, 1191 .interface = xpcs_1000basex_interfaces, 1192 .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces), 1193 .an_mode = DW_AN_C37_1000BASEX, 1194 }, 1195 [DW_XPCS_2500BASEX] = { 1196 .supported = xpcs_2500basex_features, 1197 .interface = xpcs_2500basex_interfaces, 1198 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), 1199 .an_mode = DW_2500BASEX, 1200 }, 1201 }; 1202 1203 static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { 1204 [DW_XPCS_SGMII] = { 1205 .supported = xpcs_sgmii_features, 1206 .interface = xpcs_sgmii_interfaces, 1207 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), 1208 .an_mode = DW_AN_C37_SGMII, 1209 .pma_config = nxp_sja1105_sgmii_pma_config, 1210 }, 1211 }; 1212 1213 static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { 1214 [DW_XPCS_SGMII] = { 1215 .supported = xpcs_sgmii_features, 1216 .interface = xpcs_sgmii_interfaces, 1217 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), 1218 .an_mode = DW_AN_C37_SGMII, 1219 .pma_config = nxp_sja1110_sgmii_pma_config, 1220 }, 1221 [DW_XPCS_2500BASEX] = { 1222 .supported = xpcs_2500basex_features, 1223 .interface = xpcs_2500basex_interfaces, 1224 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), 1225 .an_mode = DW_2500BASEX, 1226 .pma_config = nxp_sja1110_2500basex_pma_config, 1227 }, 1228 }; 1229 1230 static const struct xpcs_id xpcs_id_list[] = { 1231 { 1232 .id = SYNOPSYS_XPCS_ID, 1233 .mask = SYNOPSYS_XPCS_MASK, 1234 .compat = synopsys_xpcs_compat, 1235 }, { 1236 .id = NXP_SJA1105_XPCS_ID, 1237 .mask = SYNOPSYS_XPCS_MASK, 1238 .compat = nxp_sja1105_xpcs_compat, 1239 }, { 1240 .id = NXP_SJA1110_XPCS_ID, 1241 .mask = SYNOPSYS_XPCS_MASK, 1242 .compat = nxp_sja1110_xpcs_compat, 1243 }, 1244 }; 1245 1246 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1247 .pcs_validate = xpcs_validate, 1248 .pcs_config = xpcs_config, 1249 .pcs_get_state = xpcs_get_state, 1250 .pcs_an_restart = xpcs_an_restart, 1251 .pcs_link_up = xpcs_link_up, 1252 }; 1253 1254 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev, 1255 phy_interface_t interface) 1256 { 1257 struct dw_xpcs *xpcs; 1258 u32 xpcs_id; 1259 int i, ret; 1260 1261 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1262 if (!xpcs) 1263 return ERR_PTR(-ENOMEM); 1264 1265 mdio_device_get(mdiodev); 1266 xpcs->mdiodev = mdiodev; 1267 1268 xpcs_id = xpcs_get_id(xpcs); 1269 1270 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) { 1271 const struct xpcs_id *entry = &xpcs_id_list[i]; 1272 const struct xpcs_compat *compat; 1273 1274 if ((xpcs_id & entry->mask) != entry->id) 1275 continue; 1276 1277 xpcs->id = entry; 1278 1279 compat = xpcs_find_compat(entry, interface); 1280 if (!compat) { 1281 ret = -ENODEV; 1282 goto out; 1283 } 1284 1285 xpcs->pcs.ops = &xpcs_phylink_ops; 1286 if (compat->an_mode == DW_10GBASER) 1287 return xpcs; 1288 1289 xpcs->pcs.poll = true; 1290 1291 ret = xpcs_soft_reset(xpcs, compat); 1292 if (ret) 1293 goto out; 1294 1295 return xpcs; 1296 } 1297 1298 ret = -ENODEV; 1299 1300 out: 1301 mdio_device_put(mdiodev); 1302 kfree(xpcs); 1303 1304 return ERR_PTR(ret); 1305 } 1306 1307 void xpcs_destroy(struct dw_xpcs *xpcs) 1308 { 1309 if (xpcs) 1310 mdio_device_put(xpcs->mdiodev); 1311 kfree(xpcs); 1312 } 1313 EXPORT_SYMBOL_GPL(xpcs_destroy); 1314 1315 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr, 1316 phy_interface_t interface) 1317 { 1318 struct mdio_device *mdiodev; 1319 struct dw_xpcs *xpcs; 1320 1321 mdiodev = mdio_device_create(bus, addr); 1322 if (IS_ERR(mdiodev)) 1323 return ERR_CAST(mdiodev); 1324 1325 xpcs = xpcs_create(mdiodev, interface); 1326 1327 /* xpcs_create() has taken a refcount on the mdiodev if it was 1328 * successful. If xpcs_create() fails, this will free the mdio 1329 * device here. In any case, we don't need to hold our reference 1330 * anymore, and putting it here will allow mdio_device_put() in 1331 * xpcs_destroy() to automatically free the mdio device. 1332 */ 1333 mdio_device_put(mdiodev); 1334 1335 return xpcs; 1336 } 1337 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1338 1339 MODULE_LICENSE("GPL v2"); 1340