1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/mdio.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pcs-rzn1-miic.h> 14 #include <linux/phylink.h> 15 #include <linux/pm_runtime.h> 16 #include <dt-bindings/net/pcs-rzn1-miic.h> 17 18 #define MIIC_PRCMD 0x0 19 #define MIIC_ESID_CODE 0x4 20 21 #define MIIC_MODCTRL 0x20 22 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) 23 24 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 25 26 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 27 #define CONV_MODE_10MBPS 0 28 #define CONV_MODE_100MBPS 1 29 #define CONV_MODE_1000MBPS 2 30 31 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 32 #define CONV_MODE_MII 0 33 #define CONV_MODE_RMII 1 34 #define CONV_MODE_RGMII 2 35 36 #define MIIC_CONVCTRL_FULLD BIT(8) 37 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 38 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 39 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 40 41 #define MIIC_CONVRST 0x114 42 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 43 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 44 45 #define MIIC_SWCTRL 0x304 46 #define MIIC_SWDUPC 0x308 47 48 #define MIIC_MAX_NR_PORTS 5 49 50 #define MIIC_MODCTRL_CONF_CONV_NUM 6 51 #define MIIC_MODCTRL_CONF_NONE -1 52 53 /** 54 * struct modctrl_match - Matching table entry for convctrl configuration 55 * See section 8.2.1 of manual. 56 * @mode_cfg: Configuration value for convctrl 57 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 58 * then index 1 - 5 are CONV1 - CONV5. 59 */ 60 struct modctrl_match { 61 u32 mode_cfg; 62 u8 conv[MIIC_MODCTRL_CONF_CONV_NUM]; 63 }; 64 65 static struct modctrl_match modctrl_match_table[] = { 66 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 67 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 68 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 69 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 70 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 71 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 72 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 73 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 74 75 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 76 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 77 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 78 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 79 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 80 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 81 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 82 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 83 84 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 85 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 86 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 87 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 88 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 89 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 90 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 91 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 92 }; 93 94 static const char * const conf_to_string[] = { 95 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 96 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 97 [MIIC_RTOS_PORT] = "RTOS_PORT", 98 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 99 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 100 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 101 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 102 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 103 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 104 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 105 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 106 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 107 [MIIC_HSR_PORTA] = "HSR_PORTA", 108 [MIIC_HSR_PORTB] = "HSR_PORTB", 109 }; 110 111 static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = { 112 "SWITCH_PORTIN", 113 "CONV1", 114 "CONV2", 115 "CONV3", 116 "CONV4", 117 "CONV5", 118 }; 119 120 /** 121 * struct miic - MII converter structure 122 * @base: base address of the MII converter 123 * @dev: Device associated to the MII converter 124 * @clks: Clocks used for this device 125 * @nclk: Number of clocks 126 * @lock: Lock used for read-modify-write access 127 */ 128 struct miic { 129 void __iomem *base; 130 struct device *dev; 131 struct clk_bulk_data *clks; 132 int nclk; 133 spinlock_t lock; 134 }; 135 136 /** 137 * struct miic_port - Per port MII converter struct 138 * @miic: backiling to MII converter structure 139 * @pcs: PCS structure associated to the port 140 * @port: port number 141 * @interface: interface mode of the port 142 */ 143 struct miic_port { 144 struct miic *miic; 145 struct phylink_pcs pcs; 146 int port; 147 phy_interface_t interface; 148 }; 149 150 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 151 { 152 return container_of(pcs, struct miic_port, pcs); 153 } 154 155 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 156 { 157 writel(value, miic->base + offset); 158 } 159 160 static u32 miic_reg_readl(struct miic *miic, int offset) 161 { 162 return readl(miic->base + offset); 163 } 164 165 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 166 { 167 u32 reg; 168 169 spin_lock(&miic->lock); 170 171 reg = miic_reg_readl(miic, offset); 172 reg &= ~mask; 173 reg |= val; 174 miic_reg_writel(miic, offset, reg); 175 176 spin_unlock(&miic->lock); 177 } 178 179 static void miic_converter_enable(struct miic *miic, int port, int enable) 180 { 181 u32 val = 0; 182 183 if (enable) 184 val = MIIC_CONVRST_PHYIF_RST(port); 185 186 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 187 } 188 189 static int miic_config(struct phylink_pcs *pcs, unsigned int mode, 190 phy_interface_t interface, 191 const unsigned long *advertising, bool permit) 192 { 193 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 194 struct miic *miic = miic_port->miic; 195 u32 speed, conv_mode, val, mask; 196 int port = miic_port->port; 197 198 switch (interface) { 199 case PHY_INTERFACE_MODE_RMII: 200 conv_mode = CONV_MODE_RMII; 201 speed = CONV_MODE_100MBPS; 202 break; 203 case PHY_INTERFACE_MODE_RGMII: 204 case PHY_INTERFACE_MODE_RGMII_ID: 205 case PHY_INTERFACE_MODE_RGMII_TXID: 206 case PHY_INTERFACE_MODE_RGMII_RXID: 207 conv_mode = CONV_MODE_RGMII; 208 speed = CONV_MODE_1000MBPS; 209 break; 210 case PHY_INTERFACE_MODE_MII: 211 conv_mode = CONV_MODE_MII; 212 /* When in MII mode, speed should be set to 0 (which is actually 213 * CONV_MODE_10MBPS) 214 */ 215 speed = CONV_MODE_10MBPS; 216 break; 217 default: 218 return -EOPNOTSUPP; 219 } 220 221 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 222 mask = MIIC_CONVCTRL_CONV_MODE; 223 224 /* Update speed only if we are going to change the interface because 225 * the link might already be up and it would break it if the speed is 226 * changed. 227 */ 228 if (interface != miic_port->interface) { 229 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 230 mask |= MIIC_CONVCTRL_CONV_SPEED; 231 miic_port->interface = interface; 232 } 233 234 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 235 miic_converter_enable(miic_port->miic, miic_port->port, 1); 236 237 return 0; 238 } 239 240 static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, 241 phy_interface_t interface, int speed, int duplex) 242 { 243 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 244 struct miic *miic = miic_port->miic; 245 u32 conv_speed = 0, val = 0; 246 int port = miic_port->port; 247 248 if (duplex == DUPLEX_FULL) 249 val |= MIIC_CONVCTRL_FULLD; 250 251 /* No speed in MII through-mode */ 252 if (interface != PHY_INTERFACE_MODE_MII) { 253 switch (speed) { 254 case SPEED_1000: 255 conv_speed = CONV_MODE_1000MBPS; 256 break; 257 case SPEED_100: 258 conv_speed = CONV_MODE_100MBPS; 259 break; 260 case SPEED_10: 261 conv_speed = CONV_MODE_10MBPS; 262 break; 263 default: 264 return; 265 } 266 } 267 268 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 269 270 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 271 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 272 } 273 274 static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, 275 const struct phylink_link_state *state) 276 { 277 if (phy_interface_mode_is_rgmii(state->interface) || 278 state->interface == PHY_INTERFACE_MODE_RMII || 279 state->interface == PHY_INTERFACE_MODE_MII) 280 return 1; 281 282 return -EINVAL; 283 } 284 285 static const struct phylink_pcs_ops miic_phylink_ops = { 286 .pcs_validate = miic_validate, 287 .pcs_config = miic_config, 288 .pcs_link_up = miic_link_up, 289 }; 290 291 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 292 { 293 struct platform_device *pdev; 294 struct miic_port *miic_port; 295 struct device_node *pcs_np; 296 struct miic *miic; 297 u32 port; 298 299 if (!of_device_is_available(np)) 300 return ERR_PTR(-ENODEV); 301 302 if (of_property_read_u32(np, "reg", &port)) 303 return ERR_PTR(-EINVAL); 304 305 if (port > MIIC_MAX_NR_PORTS || port < 1) 306 return ERR_PTR(-EINVAL); 307 308 /* The PCS pdev is attached to the parent node */ 309 pcs_np = of_get_parent(np); 310 if (!pcs_np) 311 return ERR_PTR(-ENODEV); 312 313 if (!of_device_is_available(pcs_np)) { 314 of_node_put(pcs_np); 315 return ERR_PTR(-ENODEV); 316 } 317 318 pdev = of_find_device_by_node(pcs_np); 319 of_node_put(pcs_np); 320 if (!pdev || !platform_get_drvdata(pdev)) 321 return ERR_PTR(-EPROBE_DEFER); 322 323 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 324 if (!miic_port) 325 return ERR_PTR(-ENOMEM); 326 327 miic = platform_get_drvdata(pdev); 328 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 329 330 miic_port->miic = miic; 331 miic_port->port = port - 1; 332 miic_port->pcs.ops = &miic_phylink_ops; 333 334 return &miic_port->pcs; 335 } 336 EXPORT_SYMBOL(miic_create); 337 338 void miic_destroy(struct phylink_pcs *pcs) 339 { 340 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 341 342 miic_converter_enable(miic_port->miic, miic_port->port, 0); 343 kfree(miic_port); 344 } 345 EXPORT_SYMBOL(miic_destroy); 346 347 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 348 { 349 int port; 350 351 /* Unlock write access to accessory registers (cf datasheet). If this 352 * is going to be used in conjunction with the Cortex-M3, this sequence 353 * will have to be moved in register write 354 */ 355 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 356 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 357 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 358 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 359 360 miic_reg_writel(miic, MIIC_MODCTRL, 361 FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); 362 363 for (port = 0; port < MIIC_MAX_NR_PORTS; port++) { 364 miic_converter_enable(miic, port, 0); 365 /* Disable speed/duplex control from these registers, datasheet 366 * says switch registers should be used to setup switch port 367 * speed and duplex. 368 */ 369 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 370 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 371 } 372 373 return 0; 374 } 375 376 static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM], 377 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]) 378 { 379 int i; 380 381 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 382 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 383 continue; 384 385 if (dt_val[i] != table_val[i]) 386 return false; 387 } 388 389 return true; 390 } 391 392 static void miic_dump_conf(struct device *dev, 393 s8 conf[MIIC_MODCTRL_CONF_CONV_NUM]) 394 { 395 const char *conf_name; 396 int i; 397 398 for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { 399 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 400 conf_name = conf_to_string[conf[i]]; 401 else 402 conf_name = "NONE"; 403 404 dev_err(dev, "%s: %s\n", index_to_string[i], conf_name); 405 } 406 } 407 408 static int miic_match_dt_conf(struct device *dev, 409 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM], 410 u32 *mode_cfg) 411 { 412 struct modctrl_match *table_entry; 413 int i; 414 415 for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) { 416 table_entry = &modctrl_match_table[i]; 417 418 if (miic_modctrl_match(table_entry->conv, dt_val)) { 419 *mode_cfg = table_entry->mode_cfg; 420 return 0; 421 } 422 } 423 424 dev_err(dev, "Failed to apply requested configuration\n"); 425 miic_dump_conf(dev, dt_val); 426 427 return -EINVAL; 428 } 429 430 static int miic_parse_dt(struct device *dev, u32 *mode_cfg) 431 { 432 s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]; 433 struct device_node *np = dev->of_node; 434 struct device_node *conv; 435 u32 conf; 436 int port; 437 438 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val)); 439 440 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 441 dt_val[0] = conf; 442 443 for_each_child_of_node(np, conv) { 444 if (of_property_read_u32(conv, "reg", &port)) 445 continue; 446 447 if (!of_device_is_available(conv)) 448 continue; 449 450 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 451 dt_val[port] = conf; 452 } 453 454 return miic_match_dt_conf(dev, dt_val, mode_cfg); 455 } 456 457 static int miic_probe(struct platform_device *pdev) 458 { 459 struct device *dev = &pdev->dev; 460 struct miic *miic; 461 u32 mode_cfg; 462 int ret; 463 464 ret = miic_parse_dt(dev, &mode_cfg); 465 if (ret < 0) 466 return ret; 467 468 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 469 if (!miic) 470 return -ENOMEM; 471 472 spin_lock_init(&miic->lock); 473 miic->dev = dev; 474 miic->base = devm_platform_ioremap_resource(pdev, 0); 475 if (IS_ERR(miic->base)) 476 return PTR_ERR(miic->base); 477 478 ret = devm_pm_runtime_enable(dev); 479 if (ret < 0) 480 return ret; 481 482 ret = pm_runtime_resume_and_get(dev); 483 if (ret < 0) 484 return ret; 485 486 ret = miic_init_hw(miic, mode_cfg); 487 if (ret) 488 goto disable_runtime_pm; 489 490 /* miic_create() relies on that fact that data are attached to the 491 * platform device to determine if the driver is ready so this needs to 492 * be the last thing to be done after everything is initialized 493 * properly. 494 */ 495 platform_set_drvdata(pdev, miic); 496 497 return 0; 498 499 disable_runtime_pm: 500 pm_runtime_put(dev); 501 502 return ret; 503 } 504 505 static int miic_remove(struct platform_device *pdev) 506 { 507 pm_runtime_put(&pdev->dev); 508 509 return 0; 510 } 511 512 static const struct of_device_id miic_of_mtable[] = { 513 { .compatible = "renesas,rzn1-miic" }, 514 { /* sentinel */ }, 515 }; 516 MODULE_DEVICE_TABLE(of, miic_of_mtable); 517 518 static struct platform_driver miic_driver = { 519 .driver = { 520 .name = "rzn1_miic", 521 .suppress_bind_attrs = true, 522 .of_match_table = miic_of_mtable, 523 }, 524 .probe = miic_probe, 525 .remove = miic_remove, 526 }; 527 module_platform_driver(miic_driver); 528 529 MODULE_LICENSE("GPL"); 530 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 531 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 532