1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2020 NXP 3 * Lynx PCS MDIO helpers 4 */ 5 6 #include <linux/mdio.h> 7 #include <linux/phylink.h> 8 #include <linux/pcs-lynx.h> 9 10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */ 11 #define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS)) 12 13 #define SGMII_AN_LINK_TIMER_NS 1600000 /* defined by SGMII spec */ 14 #define IEEE8023_LINK_TIMER_NS 10000000 15 16 #define LINK_TIMER_LO 0x12 17 #define LINK_TIMER_HI 0x13 18 #define IF_MODE 0x14 19 #define IF_MODE_SGMII_EN BIT(0) 20 #define IF_MODE_USE_SGMII_AN BIT(1) 21 #define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2)) 22 #define IF_MODE_SPEED_MSK GENMASK(3, 2) 23 #define IF_MODE_HALF_DUPLEX BIT(4) 24 25 struct lynx_pcs { 26 struct phylink_pcs pcs; 27 struct mdio_device *mdio; 28 }; 29 30 enum sgmii_speed { 31 SGMII_SPEED_10 = 0, 32 SGMII_SPEED_100 = 1, 33 SGMII_SPEED_1000 = 2, 34 SGMII_SPEED_2500 = 2, 35 }; 36 37 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs) 38 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs) 39 40 struct mdio_device *lynx_get_mdio_device(struct phylink_pcs *pcs) 41 { 42 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 43 44 return lynx->mdio; 45 } 46 EXPORT_SYMBOL(lynx_get_mdio_device); 47 48 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, 49 struct phylink_link_state *state) 50 { 51 struct mii_bus *bus = pcs->bus; 52 int addr = pcs->addr; 53 int status, lpa; 54 55 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); 56 if (status < 0) 57 return; 58 59 state->link = !!(status & MDIO_STAT1_LSTATUS); 60 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); 61 if (!state->link || !state->an_complete) 62 return; 63 64 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); 65 if (lpa < 0) 66 return; 67 68 phylink_decode_usxgmii_word(state, lpa); 69 } 70 71 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, 72 struct phylink_link_state *state) 73 { 74 struct mii_bus *bus = pcs->bus; 75 int addr = pcs->addr; 76 int bmsr, lpa; 77 78 bmsr = mdiobus_read(bus, addr, MII_BMSR); 79 lpa = mdiobus_read(bus, addr, MII_LPA); 80 if (bmsr < 0 || lpa < 0) { 81 state->link = false; 82 return; 83 } 84 85 state->link = !!(bmsr & BMSR_LSTATUS); 86 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); 87 if (!state->link) 88 return; 89 90 state->speed = SPEED_2500; 91 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 92 state->duplex = DUPLEX_FULL; 93 } 94 95 static void lynx_pcs_get_state(struct phylink_pcs *pcs, 96 struct phylink_link_state *state) 97 { 98 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 99 100 switch (state->interface) { 101 case PHY_INTERFACE_MODE_1000BASEX: 102 case PHY_INTERFACE_MODE_SGMII: 103 case PHY_INTERFACE_MODE_QSGMII: 104 phylink_mii_c22_pcs_get_state(lynx->mdio, state); 105 break; 106 case PHY_INTERFACE_MODE_2500BASEX: 107 lynx_pcs_get_state_2500basex(lynx->mdio, state); 108 break; 109 case PHY_INTERFACE_MODE_USXGMII: 110 lynx_pcs_get_state_usxgmii(lynx->mdio, state); 111 break; 112 case PHY_INTERFACE_MODE_10GBASER: 113 phylink_mii_c45_pcs_get_state(lynx->mdio, state); 114 break; 115 default: 116 break; 117 } 118 119 dev_dbg(&lynx->mdio->dev, 120 "mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n", 121 phy_modes(state->interface), 122 phy_speed_to_str(state->speed), 123 phy_duplex_to_str(state->duplex), 124 state->link, state->an_enabled, state->an_complete); 125 } 126 127 static int lynx_pcs_config_1000basex(struct mdio_device *pcs, 128 unsigned int mode, 129 const unsigned long *advertising) 130 { 131 struct mii_bus *bus = pcs->bus; 132 int addr = pcs->addr; 133 u32 link_timer; 134 int err; 135 136 link_timer = LINK_TIMER_VAL(IEEE8023_LINK_TIMER_NS); 137 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff); 138 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16); 139 140 err = mdiobus_modify(bus, addr, IF_MODE, 141 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN, 142 0); 143 if (err) 144 return err; 145 146 return phylink_mii_c22_pcs_config(pcs, mode, 147 PHY_INTERFACE_MODE_1000BASEX, 148 advertising); 149 } 150 151 static int lynx_pcs_config_sgmii(struct mdio_device *pcs, unsigned int mode, 152 const unsigned long *advertising) 153 { 154 struct mii_bus *bus = pcs->bus; 155 int addr = pcs->addr; 156 u16 if_mode; 157 int err; 158 159 if_mode = IF_MODE_SGMII_EN; 160 if (mode == MLO_AN_INBAND) { 161 u32 link_timer; 162 163 if_mode |= IF_MODE_USE_SGMII_AN; 164 165 /* Adjust link timer for SGMII */ 166 link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS); 167 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff); 168 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16); 169 } 170 err = mdiobus_modify(bus, addr, IF_MODE, 171 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN, 172 if_mode); 173 if (err) 174 return err; 175 176 return phylink_mii_c22_pcs_config(pcs, mode, PHY_INTERFACE_MODE_SGMII, 177 advertising); 178 } 179 180 static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode, 181 const unsigned long *advertising) 182 { 183 struct mii_bus *bus = pcs->bus; 184 int addr = pcs->addr; 185 186 if (!phylink_autoneg_inband(mode)) { 187 dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n"); 188 return -EOPNOTSUPP; 189 } 190 191 /* Configure device ability for the USXGMII Replicator */ 192 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, 193 MDIO_USXGMII_10G | MDIO_USXGMII_LINK | 194 MDIO_USXGMII_FULL_DUPLEX | 195 ADVERTISE_SGMII | ADVERTISE_LPACK); 196 } 197 198 static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 199 phy_interface_t ifmode, 200 const unsigned long *advertising, 201 bool permit) 202 { 203 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 204 205 switch (ifmode) { 206 case PHY_INTERFACE_MODE_1000BASEX: 207 return lynx_pcs_config_1000basex(lynx->mdio, mode, advertising); 208 case PHY_INTERFACE_MODE_SGMII: 209 case PHY_INTERFACE_MODE_QSGMII: 210 return lynx_pcs_config_sgmii(lynx->mdio, mode, advertising); 211 case PHY_INTERFACE_MODE_2500BASEX: 212 if (phylink_autoneg_inband(mode)) { 213 dev_err(&lynx->mdio->dev, 214 "AN not supported on 3.125GHz SerDes lane\n"); 215 return -EOPNOTSUPP; 216 } 217 break; 218 case PHY_INTERFACE_MODE_USXGMII: 219 return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising); 220 case PHY_INTERFACE_MODE_10GBASER: 221 /* Nothing to do here for 10GBASER */ 222 break; 223 default: 224 return -EOPNOTSUPP; 225 } 226 227 return 0; 228 } 229 230 static void lynx_pcs_an_restart(struct phylink_pcs *pcs) 231 { 232 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 233 234 phylink_mii_c22_pcs_an_restart(lynx->mdio); 235 } 236 237 static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode, 238 int speed, int duplex) 239 { 240 struct mii_bus *bus = pcs->bus; 241 u16 if_mode = 0, sgmii_speed; 242 int addr = pcs->addr; 243 244 /* The PCS needs to be configured manually only 245 * when not operating on in-band mode 246 */ 247 if (mode == MLO_AN_INBAND) 248 return; 249 250 if (duplex == DUPLEX_HALF) 251 if_mode |= IF_MODE_HALF_DUPLEX; 252 253 switch (speed) { 254 case SPEED_1000: 255 sgmii_speed = SGMII_SPEED_1000; 256 break; 257 case SPEED_100: 258 sgmii_speed = SGMII_SPEED_100; 259 break; 260 case SPEED_10: 261 sgmii_speed = SGMII_SPEED_10; 262 break; 263 case SPEED_UNKNOWN: 264 /* Silently don't do anything */ 265 return; 266 default: 267 dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed); 268 return; 269 } 270 if_mode |= IF_MODE_SPEED(sgmii_speed); 271 272 mdiobus_modify(bus, addr, IF_MODE, 273 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK, 274 if_mode); 275 } 276 277 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 278 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 279 * auto-negotiation of any link parameters. Electrically it is compatible with 280 * a single lane of XAUI. 281 * The hardware reference manual wants to call this mode SGMII, but it isn't 282 * really, since the fundamental features of SGMII: 283 * - Downgrading the link speed by duplicating symbols 284 * - Auto-negotiation 285 * are not there. 286 * The speed is configured at 1000 in the IF_MODE because the clock frequency 287 * is actually given by a PLL configured in the Reset Configuration Word (RCW). 288 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 289 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 290 * lower link speed on line side, the system-side interface remains fixed at 291 * 2500 Mbps and we do rate adaptation through pause frames. 292 */ 293 static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs, 294 unsigned int mode, 295 int speed, int duplex) 296 { 297 struct mii_bus *bus = pcs->bus; 298 int addr = pcs->addr; 299 u16 if_mode = 0; 300 301 if (mode == MLO_AN_INBAND) { 302 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n"); 303 return; 304 } 305 306 if (duplex == DUPLEX_HALF) 307 if_mode |= IF_MODE_HALF_DUPLEX; 308 if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500); 309 310 mdiobus_modify(bus, addr, IF_MODE, 311 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK, 312 if_mode); 313 } 314 315 static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 316 phy_interface_t interface, 317 int speed, int duplex) 318 { 319 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 320 321 switch (interface) { 322 case PHY_INTERFACE_MODE_SGMII: 323 case PHY_INTERFACE_MODE_QSGMII: 324 lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex); 325 break; 326 case PHY_INTERFACE_MODE_2500BASEX: 327 lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex); 328 break; 329 case PHY_INTERFACE_MODE_USXGMII: 330 /* At the moment, only in-band AN is supported for USXGMII 331 * so nothing to do in link_up 332 */ 333 break; 334 default: 335 break; 336 } 337 } 338 339 static const struct phylink_pcs_ops lynx_pcs_phylink_ops = { 340 .pcs_get_state = lynx_pcs_get_state, 341 .pcs_config = lynx_pcs_config, 342 .pcs_an_restart = lynx_pcs_an_restart, 343 .pcs_link_up = lynx_pcs_link_up, 344 }; 345 346 struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio) 347 { 348 struct lynx_pcs *lynx; 349 350 lynx = kzalloc(sizeof(*lynx), GFP_KERNEL); 351 if (!lynx) 352 return NULL; 353 354 lynx->mdio = mdio; 355 lynx->pcs.ops = &lynx_pcs_phylink_ops; 356 lynx->pcs.poll = true; 357 358 return lynx_to_phylink_pcs(lynx); 359 } 360 EXPORT_SYMBOL(lynx_pcs_create); 361 362 void lynx_pcs_destroy(struct phylink_pcs *pcs) 363 { 364 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 365 366 kfree(lynx); 367 } 368 EXPORT_SYMBOL(lynx_pcs_destroy); 369 370 MODULE_LICENSE("Dual BSD/GPL"); 371