1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2020 NXP 3 * Lynx PCS MDIO helpers 4 */ 5 6 #include <linux/mdio.h> 7 #include <linux/phylink.h> 8 #include <linux/pcs-lynx.h> 9 10 #define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */ 11 #define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS)) 12 13 #define SGMII_AN_LINK_TIMER_NS 1600000 /* defined by SGMII spec */ 14 15 #define LINK_TIMER_LO 0x12 16 #define LINK_TIMER_HI 0x13 17 #define IF_MODE 0x14 18 #define IF_MODE_SGMII_EN BIT(0) 19 #define IF_MODE_USE_SGMII_AN BIT(1) 20 #define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2)) 21 #define IF_MODE_SPEED_MSK GENMASK(3, 2) 22 #define IF_MODE_HALF_DUPLEX BIT(4) 23 24 enum sgmii_speed { 25 SGMII_SPEED_10 = 0, 26 SGMII_SPEED_100 = 1, 27 SGMII_SPEED_1000 = 2, 28 SGMII_SPEED_2500 = 2, 29 }; 30 31 #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs) 32 33 static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, 34 struct phylink_link_state *state) 35 { 36 struct mii_bus *bus = pcs->bus; 37 int addr = pcs->addr; 38 int status, lpa; 39 40 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); 41 if (status < 0) 42 return; 43 44 state->link = !!(status & MDIO_STAT1_LSTATUS); 45 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); 46 if (!state->link || !state->an_complete) 47 return; 48 49 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); 50 if (lpa < 0) 51 return; 52 53 phylink_decode_usxgmii_word(state, lpa); 54 } 55 56 static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, 57 struct phylink_link_state *state) 58 { 59 struct mii_bus *bus = pcs->bus; 60 int addr = pcs->addr; 61 int bmsr, lpa; 62 63 bmsr = mdiobus_read(bus, addr, MII_BMSR); 64 lpa = mdiobus_read(bus, addr, MII_LPA); 65 if (bmsr < 0 || lpa < 0) { 66 state->link = false; 67 return; 68 } 69 70 state->link = !!(bmsr & BMSR_LSTATUS); 71 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); 72 if (!state->link) 73 return; 74 75 state->speed = SPEED_2500; 76 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 77 state->duplex = DUPLEX_FULL; 78 } 79 80 static void lynx_pcs_get_state(struct phylink_pcs *pcs, 81 struct phylink_link_state *state) 82 { 83 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 84 85 switch (state->interface) { 86 case PHY_INTERFACE_MODE_SGMII: 87 case PHY_INTERFACE_MODE_QSGMII: 88 phylink_mii_c22_pcs_get_state(lynx->mdio, state); 89 break; 90 case PHY_INTERFACE_MODE_2500BASEX: 91 lynx_pcs_get_state_2500basex(lynx->mdio, state); 92 break; 93 case PHY_INTERFACE_MODE_USXGMII: 94 lynx_pcs_get_state_usxgmii(lynx->mdio, state); 95 break; 96 default: 97 break; 98 } 99 100 dev_dbg(&lynx->mdio->dev, 101 "mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n", 102 phy_modes(state->interface), 103 phy_speed_to_str(state->speed), 104 phy_duplex_to_str(state->duplex), 105 state->link, state->an_enabled, state->an_complete); 106 } 107 108 static int lynx_pcs_config_sgmii(struct mdio_device *pcs, unsigned int mode, 109 const unsigned long *advertising) 110 { 111 struct mii_bus *bus = pcs->bus; 112 int addr = pcs->addr; 113 u16 if_mode; 114 int err; 115 116 if_mode = IF_MODE_SGMII_EN; 117 if (mode == MLO_AN_INBAND) { 118 u32 link_timer; 119 120 if_mode |= IF_MODE_USE_SGMII_AN; 121 122 /* Adjust link timer for SGMII */ 123 link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS); 124 mdiobus_write(bus, addr, LINK_TIMER_LO, link_timer & 0xffff); 125 mdiobus_write(bus, addr, LINK_TIMER_HI, link_timer >> 16); 126 } 127 err = mdiobus_modify(bus, addr, IF_MODE, 128 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN, 129 if_mode); 130 if (err) 131 return err; 132 133 return phylink_mii_c22_pcs_config(pcs, mode, PHY_INTERFACE_MODE_SGMII, 134 advertising); 135 } 136 137 static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode, 138 const unsigned long *advertising) 139 { 140 struct mii_bus *bus = pcs->bus; 141 int addr = pcs->addr; 142 143 if (!phylink_autoneg_inband(mode)) { 144 dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n"); 145 return -EOPNOTSUPP; 146 } 147 148 /* Configure device ability for the USXGMII Replicator */ 149 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, 150 MDIO_USXGMII_10G | MDIO_USXGMII_LINK | 151 MDIO_USXGMII_FULL_DUPLEX | 152 ADVERTISE_SGMII | ADVERTISE_LPACK); 153 } 154 155 static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 156 phy_interface_t ifmode, 157 const unsigned long *advertising, 158 bool permit) 159 { 160 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 161 162 switch (ifmode) { 163 case PHY_INTERFACE_MODE_SGMII: 164 case PHY_INTERFACE_MODE_QSGMII: 165 return lynx_pcs_config_sgmii(lynx->mdio, mode, advertising); 166 case PHY_INTERFACE_MODE_2500BASEX: 167 if (phylink_autoneg_inband(mode)) { 168 dev_err(&lynx->mdio->dev, 169 "AN not supported on 3.125GHz SerDes lane\n"); 170 return -EOPNOTSUPP; 171 } 172 break; 173 case PHY_INTERFACE_MODE_USXGMII: 174 return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising); 175 default: 176 return -EOPNOTSUPP; 177 } 178 179 return 0; 180 } 181 182 static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode, 183 int speed, int duplex) 184 { 185 struct mii_bus *bus = pcs->bus; 186 u16 if_mode = 0, sgmii_speed; 187 int addr = pcs->addr; 188 189 /* The PCS needs to be configured manually only 190 * when not operating on in-band mode 191 */ 192 if (mode == MLO_AN_INBAND) 193 return; 194 195 if (duplex == DUPLEX_HALF) 196 if_mode |= IF_MODE_HALF_DUPLEX; 197 198 switch (speed) { 199 case SPEED_1000: 200 sgmii_speed = SGMII_SPEED_1000; 201 break; 202 case SPEED_100: 203 sgmii_speed = SGMII_SPEED_100; 204 break; 205 case SPEED_10: 206 sgmii_speed = SGMII_SPEED_10; 207 break; 208 case SPEED_UNKNOWN: 209 /* Silently don't do anything */ 210 return; 211 default: 212 dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed); 213 return; 214 } 215 if_mode |= IF_MODE_SPEED(sgmii_speed); 216 217 mdiobus_modify(bus, addr, IF_MODE, 218 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK, 219 if_mode); 220 } 221 222 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 223 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 224 * auto-negotiation of any link parameters. Electrically it is compatible with 225 * a single lane of XAUI. 226 * The hardware reference manual wants to call this mode SGMII, but it isn't 227 * really, since the fundamental features of SGMII: 228 * - Downgrading the link speed by duplicating symbols 229 * - Auto-negotiation 230 * are not there. 231 * The speed is configured at 1000 in the IF_MODE because the clock frequency 232 * is actually given by a PLL configured in the Reset Configuration Word (RCW). 233 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 234 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 235 * lower link speed on line side, the system-side interface remains fixed at 236 * 2500 Mbps and we do rate adaptation through pause frames. 237 */ 238 static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs, 239 unsigned int mode, 240 int speed, int duplex) 241 { 242 struct mii_bus *bus = pcs->bus; 243 int addr = pcs->addr; 244 u16 if_mode = 0; 245 246 if (mode == MLO_AN_INBAND) { 247 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n"); 248 return; 249 } 250 251 if (duplex == DUPLEX_HALF) 252 if_mode |= IF_MODE_HALF_DUPLEX; 253 if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500); 254 255 mdiobus_modify(bus, addr, IF_MODE, 256 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK, 257 if_mode); 258 } 259 260 static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 261 phy_interface_t interface, 262 int speed, int duplex) 263 { 264 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); 265 266 switch (interface) { 267 case PHY_INTERFACE_MODE_SGMII: 268 case PHY_INTERFACE_MODE_QSGMII: 269 lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex); 270 break; 271 case PHY_INTERFACE_MODE_2500BASEX: 272 lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex); 273 break; 274 case PHY_INTERFACE_MODE_USXGMII: 275 /* At the moment, only in-band AN is supported for USXGMII 276 * so nothing to do in link_up 277 */ 278 break; 279 default: 280 break; 281 } 282 } 283 284 static const struct phylink_pcs_ops lynx_pcs_phylink_ops = { 285 .pcs_get_state = lynx_pcs_get_state, 286 .pcs_config = lynx_pcs_config, 287 .pcs_link_up = lynx_pcs_link_up, 288 }; 289 290 struct lynx_pcs *lynx_pcs_create(struct mdio_device *mdio) 291 { 292 struct lynx_pcs *lynx_pcs; 293 294 lynx_pcs = kzalloc(sizeof(*lynx_pcs), GFP_KERNEL); 295 if (!lynx_pcs) 296 return NULL; 297 298 lynx_pcs->mdio = mdio; 299 lynx_pcs->pcs.ops = &lynx_pcs_phylink_ops; 300 lynx_pcs->pcs.poll = true; 301 302 return lynx_pcs; 303 } 304 EXPORT_SYMBOL(lynx_pcs_create); 305 306 void lynx_pcs_destroy(struct lynx_pcs *pcs) 307 { 308 kfree(pcs); 309 } 310 EXPORT_SYMBOL(lynx_pcs_destroy); 311 312 MODULE_LICENSE("Dual BSD/GPL"); 313