1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2016 Broadcom
4  */
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/device.h>
8 #include <linux/iopoll.h>
9 #include <linux/mdio-mux.h>
10 #include <linux/module.h>
11 #include <linux/of_mdio.h>
12 #include <linux/phy.h>
13 #include <linux/platform_device.h>
14 
15 #define MDIO_RATE_ADJ_EXT_OFFSET	0x000
16 #define MDIO_RATE_ADJ_INT_OFFSET	0x004
17 #define MDIO_RATE_ADJ_DIVIDENT_SHIFT	16
18 
19 #define MDIO_SCAN_CTRL_OFFSET		0x008
20 #define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR	28
21 
22 #define MDIO_PARAM_OFFSET		0x23c
23 #define MDIO_PARAM_MIIM_CYCLE		29
24 #define MDIO_PARAM_INTERNAL_SEL		25
25 #define MDIO_PARAM_BUS_ID		22
26 #define MDIO_PARAM_C45_SEL		21
27 #define MDIO_PARAM_PHY_ID		16
28 #define MDIO_PARAM_PHY_DATA		0
29 
30 #define MDIO_READ_OFFSET		0x240
31 #define MDIO_READ_DATA_MASK		0xffff
32 #define MDIO_ADDR_OFFSET		0x244
33 
34 #define MDIO_CTRL_OFFSET		0x248
35 #define MDIO_CTRL_WRITE_OP		0x1
36 #define MDIO_CTRL_READ_OP		0x2
37 
38 #define MDIO_STAT_OFFSET		0x24c
39 #define MDIO_STAT_DONE			1
40 
41 #define BUS_MAX_ADDR			32
42 #define EXT_BUS_START_ADDR		16
43 
44 #define MDIO_REG_ADDR_SPACE_SIZE	0x250
45 
46 #define MDIO_OPERATING_FREQUENCY	11000000
47 #define MDIO_RATE_ADJ_DIVIDENT		1
48 
49 struct iproc_mdiomux_desc {
50 	void *mux_handle;
51 	void __iomem *base;
52 	struct device *dev;
53 	struct mii_bus *mii_bus;
54 	struct clk *core_clk;
55 };
56 
57 static void mdio_mux_iproc_config(struct iproc_mdiomux_desc *md)
58 {
59 	u32 divisor;
60 	u32 val;
61 
62 	/* Disable external mdio master access */
63 	val = readl(md->base + MDIO_SCAN_CTRL_OFFSET);
64 	val |= BIT(MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR);
65 	writel(val, md->base + MDIO_SCAN_CTRL_OFFSET);
66 
67 	if (md->core_clk) {
68 		/* use rate adjust regs to derive the mdio's operating
69 		 * frequency from the specified core clock
70 		 */
71 		divisor = clk_get_rate(md->core_clk) / MDIO_OPERATING_FREQUENCY;
72 		divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1);
73 		val = divisor;
74 		val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT;
75 		writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET);
76 		writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET);
77 	}
78 }
79 
80 static int iproc_mdio_wait_for_idle(void __iomem *base, bool result)
81 {
82 	u32 val;
83 
84 	return readl_poll_timeout(base + MDIO_STAT_OFFSET, val,
85 				  (val & MDIO_STAT_DONE) == result,
86 				  2000, 1000000);
87 }
88 
89 /* start_miim_ops- Program and start MDIO transaction over mdio bus.
90  * @base: Base address
91  * @phyid: phyid of the selected bus.
92  * @reg: register offset to be read/written.
93  * @val :0 if read op else value to be written in @reg;
94  * @op: Operation that need to be carried out.
95  *      MDIO_CTRL_READ_OP: Read transaction.
96  *      MDIO_CTRL_WRITE_OP: Write transaction.
97  *
98  * Return value: Successful Read operation returns read reg values and write
99  *      operation returns 0. Failure operation returns negative error code.
100  */
101 static int start_miim_ops(void __iomem *base, bool c45,
102 			  u16 phyid, u32 reg, u16 val, u32 op)
103 {
104 	u32 param;
105 	int ret;
106 
107 	writel(0, base + MDIO_CTRL_OFFSET);
108 	ret = iproc_mdio_wait_for_idle(base, 0);
109 	if (ret)
110 		goto err;
111 
112 	param = readl(base + MDIO_PARAM_OFFSET);
113 	param |= phyid << MDIO_PARAM_PHY_ID;
114 	param |= val << MDIO_PARAM_PHY_DATA;
115 	if (c45)
116 		param |= BIT(MDIO_PARAM_C45_SEL);
117 
118 	writel(param, base + MDIO_PARAM_OFFSET);
119 
120 	writel(reg, base + MDIO_ADDR_OFFSET);
121 
122 	writel(op, base + MDIO_CTRL_OFFSET);
123 
124 	ret = iproc_mdio_wait_for_idle(base, 1);
125 	if (ret)
126 		goto err;
127 
128 	if (op == MDIO_CTRL_READ_OP)
129 		ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK;
130 err:
131 	return ret;
132 }
133 
134 static int iproc_mdiomux_read_c22(struct mii_bus *bus, int phyid, int reg)
135 {
136 	struct iproc_mdiomux_desc *md = bus->priv;
137 	int ret;
138 
139 	ret = start_miim_ops(md->base, false, phyid, reg, 0, MDIO_CTRL_READ_OP);
140 	if (ret < 0)
141 		dev_err(&bus->dev, "mdiomux c22 read operation failed!!!");
142 
143 	return ret;
144 }
145 
146 static int iproc_mdiomux_read_c45(struct mii_bus *bus, int phyid, int devad,
147 				  int reg)
148 {
149 	struct iproc_mdiomux_desc *md = bus->priv;
150 	int ret;
151 
152 	ret = start_miim_ops(md->base, true, phyid, reg | devad << 16, 0,
153 			     MDIO_CTRL_READ_OP);
154 	if (ret < 0)
155 		dev_err(&bus->dev, "mdiomux read c45 operation failed!!!");
156 
157 	return ret;
158 }
159 
160 static int iproc_mdiomux_write_c22(struct mii_bus *bus,
161 				   int phyid, int reg, u16 val)
162 {
163 	struct iproc_mdiomux_desc *md = bus->priv;
164 	int ret;
165 
166 	/* Write val at reg offset */
167 	ret = start_miim_ops(md->base, false, phyid, reg, val,
168 			     MDIO_CTRL_WRITE_OP);
169 	if (ret < 0)
170 		dev_err(&bus->dev, "mdiomux write c22 operation failed!!!");
171 
172 	return ret;
173 }
174 
175 static int iproc_mdiomux_write_c45(struct mii_bus *bus,
176 				   int phyid, int devad, int reg, u16 val)
177 {
178 	struct iproc_mdiomux_desc *md = bus->priv;
179 	int ret;
180 
181 	/* Write val at reg offset */
182 	ret = start_miim_ops(md->base, true, phyid, reg | devad << 16, val,
183 			     MDIO_CTRL_WRITE_OP);
184 	if (ret < 0)
185 		dev_err(&bus->dev, "mdiomux write c45 operation failed!!!");
186 
187 	return ret;
188 }
189 
190 static int mdio_mux_iproc_switch_fn(int current_child, int desired_child,
191 				    void *data)
192 {
193 	struct iproc_mdiomux_desc *md = data;
194 	u32 param, bus_id;
195 	bool bus_dir;
196 
197 	/* select bus and its properties */
198 	bus_dir = (desired_child < EXT_BUS_START_ADDR);
199 	bus_id = bus_dir ? desired_child : (desired_child - EXT_BUS_START_ADDR);
200 
201 	param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL;
202 	param |= (bus_id << MDIO_PARAM_BUS_ID);
203 
204 	writel(param, md->base + MDIO_PARAM_OFFSET);
205 	return 0;
206 }
207 
208 static int mdio_mux_iproc_probe(struct platform_device *pdev)
209 {
210 	struct iproc_mdiomux_desc *md;
211 	struct mii_bus *bus;
212 	struct resource *res;
213 	int rc;
214 
215 	md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);
216 	if (!md)
217 		return -ENOMEM;
218 	md->dev = &pdev->dev;
219 
220 	md->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
221 	if (IS_ERR(md->base))
222 		return PTR_ERR(md->base);
223 	if (res->start & 0xfff) {
224 		/* For backward compatibility in case the
225 		 * base address is specified with an offset.
226 		 */
227 		dev_info(&pdev->dev, "fix base address in dt-blob\n");
228 		res->start &= ~0xfff;
229 		res->end = res->start + MDIO_REG_ADDR_SPACE_SIZE - 1;
230 	}
231 
232 	md->mii_bus = devm_mdiobus_alloc(&pdev->dev);
233 	if (!md->mii_bus) {
234 		dev_err(&pdev->dev, "mdiomux bus alloc failed\n");
235 		return -ENOMEM;
236 	}
237 
238 	md->core_clk = devm_clk_get(&pdev->dev, NULL);
239 	if (md->core_clk == ERR_PTR(-ENOENT) ||
240 	    md->core_clk == ERR_PTR(-EINVAL))
241 		md->core_clk = NULL;
242 	else if (IS_ERR(md->core_clk))
243 		return PTR_ERR(md->core_clk);
244 
245 	rc = clk_prepare_enable(md->core_clk);
246 	if (rc) {
247 		dev_err(&pdev->dev, "failed to enable core clk\n");
248 		return rc;
249 	}
250 
251 	bus = md->mii_bus;
252 	bus->priv = md;
253 	bus->name = "iProc MDIO mux bus";
254 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
255 	bus->parent = &pdev->dev;
256 	bus->read = iproc_mdiomux_read_c22;
257 	bus->write = iproc_mdiomux_write_c22;
258 	bus->read_c45 = iproc_mdiomux_read_c45;
259 	bus->write_c45 = iproc_mdiomux_write_c45;
260 
261 	bus->phy_mask = ~0;
262 	bus->dev.of_node = pdev->dev.of_node;
263 	rc = mdiobus_register(bus);
264 	if (rc) {
265 		dev_err(&pdev->dev, "mdiomux registration failed\n");
266 		goto out_clk;
267 	}
268 
269 	platform_set_drvdata(pdev, md);
270 
271 	rc = mdio_mux_init(md->dev, md->dev->of_node, mdio_mux_iproc_switch_fn,
272 			   &md->mux_handle, md, md->mii_bus);
273 	if (rc) {
274 		dev_info(md->dev, "mdiomux initialization failed\n");
275 		goto out_register;
276 	}
277 
278 	mdio_mux_iproc_config(md);
279 
280 	dev_info(md->dev, "iProc mdiomux registered\n");
281 	return 0;
282 
283 out_register:
284 	mdiobus_unregister(bus);
285 out_clk:
286 	clk_disable_unprepare(md->core_clk);
287 	return rc;
288 }
289 
290 static int mdio_mux_iproc_remove(struct platform_device *pdev)
291 {
292 	struct iproc_mdiomux_desc *md = platform_get_drvdata(pdev);
293 
294 	mdio_mux_uninit(md->mux_handle);
295 	mdiobus_unregister(md->mii_bus);
296 	clk_disable_unprepare(md->core_clk);
297 
298 	return 0;
299 }
300 
301 #ifdef CONFIG_PM_SLEEP
302 static int mdio_mux_iproc_suspend(struct device *dev)
303 {
304 	struct iproc_mdiomux_desc *md = dev_get_drvdata(dev);
305 
306 	clk_disable_unprepare(md->core_clk);
307 
308 	return 0;
309 }
310 
311 static int mdio_mux_iproc_resume(struct device *dev)
312 {
313 	struct iproc_mdiomux_desc *md = dev_get_drvdata(dev);
314 	int rc;
315 
316 	rc = clk_prepare_enable(md->core_clk);
317 	if (rc) {
318 		dev_err(md->dev, "failed to enable core clk\n");
319 		return rc;
320 	}
321 	mdio_mux_iproc_config(md);
322 
323 	return 0;
324 }
325 #endif
326 
327 static SIMPLE_DEV_PM_OPS(mdio_mux_iproc_pm_ops,
328 			 mdio_mux_iproc_suspend, mdio_mux_iproc_resume);
329 
330 static const struct of_device_id mdio_mux_iproc_match[] = {
331 	{
332 		.compatible = "brcm,mdio-mux-iproc",
333 	},
334 	{},
335 };
336 MODULE_DEVICE_TABLE(of, mdio_mux_iproc_match);
337 
338 static struct platform_driver mdiomux_iproc_driver = {
339 	.driver = {
340 		.name		= "mdio-mux-iproc",
341 		.of_match_table = mdio_mux_iproc_match,
342 		.pm		= &mdio_mux_iproc_pm_ops,
343 	},
344 	.probe		= mdio_mux_iproc_probe,
345 	.remove		= mdio_mux_iproc_remove,
346 };
347 
348 module_platform_driver(mdiomux_iproc_driver);
349 
350 MODULE_DESCRIPTION("iProc MDIO Mux Bus Driver");
351 MODULE_AUTHOR("Pramod Kumar <pramod.kumar@broadcom.com>");
352 MODULE_LICENSE("GPL v2");
353