1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Driver for the MDIO interface of Microsemi network switches.
4  *
5  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
6  * Copyright (c) 2017 Microsemi Corporation
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mdio/mdio-mscc-miim.h>
14 #include <linux/module.h>
15 #include <linux/of_mdio.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 
20 #define MSCC_MIIM_REG_STATUS		0x0
21 #define		MSCC_MIIM_STATUS_STAT_PENDING	BIT(2)
22 #define		MSCC_MIIM_STATUS_STAT_BUSY	BIT(3)
23 #define MSCC_MIIM_REG_CMD		0x8
24 #define		MSCC_MIIM_CMD_OPR_WRITE		BIT(1)
25 #define		MSCC_MIIM_CMD_OPR_READ		BIT(2)
26 #define		MSCC_MIIM_CMD_WRDATA_SHIFT	4
27 #define		MSCC_MIIM_CMD_REGAD_SHIFT	20
28 #define		MSCC_MIIM_CMD_PHYAD_SHIFT	25
29 #define		MSCC_MIIM_CMD_VLD		BIT(31)
30 #define MSCC_MIIM_REG_DATA		0xC
31 #define		MSCC_MIIM_DATA_ERROR		(BIT(16) | BIT(17))
32 
33 #define MSCC_PHY_REG_PHY_CFG	0x0
34 #define		PHY_CFG_PHY_ENA		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
35 #define		PHY_CFG_PHY_COMMON_RESET BIT(4)
36 #define		PHY_CFG_PHY_RESET	(BIT(5) | BIT(6) | BIT(7) | BIT(8))
37 #define MSCC_PHY_REG_PHY_STATUS	0x4
38 
39 struct mscc_miim_dev {
40 	struct regmap *regs;
41 	int mii_status_offset;
42 	struct regmap *phy_regs;
43 	int phy_reset_offset;
44 };
45 
46 /* When high resolution timers aren't built-in: we can't use usleep_range() as
47  * we would sleep way too long. Use udelay() instead.
48  */
49 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
50 ({									  \
51 	if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS))			  \
52 		readx_poll_timeout_atomic(op, addr, val, cond, delay_us,  \
53 					  timeout_us);			  \
54 	readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us);	  \
55 })
56 
57 static int mscc_miim_status(struct mii_bus *bus)
58 {
59 	struct mscc_miim_dev *miim = bus->priv;
60 	int val, ret;
61 
62 	ret = regmap_read(miim->regs,
63 			  MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
64 	if (ret < 0) {
65 		WARN_ONCE(1, "mscc miim status read error %d\n", ret);
66 		return ret;
67 	}
68 
69 	return val;
70 }
71 
72 static int mscc_miim_wait_ready(struct mii_bus *bus)
73 {
74 	u32 val;
75 
76 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
77 				       !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
78 				       10000);
79 }
80 
81 static int mscc_miim_wait_pending(struct mii_bus *bus)
82 {
83 	u32 val;
84 
85 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
86 				       !(val & MSCC_MIIM_STATUS_STAT_PENDING),
87 				       50, 10000);
88 }
89 
90 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
91 {
92 	struct mscc_miim_dev *miim = bus->priv;
93 	u32 val;
94 	int ret;
95 
96 	ret = mscc_miim_wait_pending(bus);
97 	if (ret)
98 		goto out;
99 
100 	ret = regmap_write(miim->regs,
101 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
102 			   MSCC_MIIM_CMD_VLD |
103 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
104 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
105 			   MSCC_MIIM_CMD_OPR_READ);
106 
107 	if (ret < 0) {
108 		WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
109 		goto out;
110 	}
111 
112 	ret = mscc_miim_wait_ready(bus);
113 	if (ret)
114 		goto out;
115 
116 	ret = regmap_read(miim->regs,
117 			  MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
118 	if (ret < 0) {
119 		WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
120 		goto out;
121 	}
122 
123 	if (val & MSCC_MIIM_DATA_ERROR) {
124 		ret = -EIO;
125 		goto out;
126 	}
127 
128 	ret = val & 0xFFFF;
129 out:
130 	return ret;
131 }
132 
133 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
134 			   int regnum, u16 value)
135 {
136 	struct mscc_miim_dev *miim = bus->priv;
137 	int ret;
138 
139 	ret = mscc_miim_wait_pending(bus);
140 	if (ret < 0)
141 		goto out;
142 
143 	ret = regmap_write(miim->regs,
144 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
145 			   MSCC_MIIM_CMD_VLD |
146 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
147 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
148 			   (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
149 			   MSCC_MIIM_CMD_OPR_WRITE);
150 
151 	if (ret < 0)
152 		WARN_ONCE(1, "mscc miim write error %d\n", ret);
153 out:
154 	return ret;
155 }
156 
157 static int mscc_miim_reset(struct mii_bus *bus)
158 {
159 	struct mscc_miim_dev *miim = bus->priv;
160 	int offset = miim->phy_reset_offset;
161 	int ret;
162 
163 	if (miim->phy_regs) {
164 		ret = regmap_write(miim->phy_regs,
165 				   MSCC_PHY_REG_PHY_CFG + offset, 0);
166 		if (ret < 0) {
167 			WARN_ONCE(1, "mscc reset set error %d\n", ret);
168 			return ret;
169 		}
170 
171 		ret = regmap_write(miim->phy_regs,
172 				   MSCC_PHY_REG_PHY_CFG + offset, 0x1ff);
173 		if (ret < 0) {
174 			WARN_ONCE(1, "mscc reset clear error %d\n", ret);
175 			return ret;
176 		}
177 
178 		mdelay(500);
179 	}
180 
181 	return 0;
182 }
183 
184 static const struct regmap_config mscc_miim_regmap_config = {
185 	.reg_bits	= 32,
186 	.val_bits	= 32,
187 	.reg_stride	= 4,
188 };
189 
190 static const struct regmap_config mscc_miim_phy_regmap_config = {
191 	.reg_bits	= 32,
192 	.val_bits	= 32,
193 	.reg_stride	= 4,
194 	.name		= "phy",
195 };
196 
197 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
198 		    struct regmap *mii_regmap, int status_offset)
199 {
200 	struct mscc_miim_dev *miim;
201 	struct mii_bus *bus;
202 
203 	bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
204 	if (!bus)
205 		return -ENOMEM;
206 
207 	bus->name = name;
208 	bus->read = mscc_miim_read;
209 	bus->write = mscc_miim_write;
210 	bus->reset = mscc_miim_reset;
211 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
212 	bus->parent = dev;
213 
214 	miim = bus->priv;
215 
216 	*pbus = bus;
217 
218 	miim->regs = mii_regmap;
219 	miim->mii_status_offset = status_offset;
220 
221 	*pbus = bus;
222 
223 	return 0;
224 }
225 EXPORT_SYMBOL(mscc_miim_setup);
226 
227 static int mscc_miim_probe(struct platform_device *pdev)
228 {
229 	struct regmap *mii_regmap, *phy_regmap = NULL;
230 	void __iomem *regs, *phy_regs;
231 	struct mscc_miim_dev *miim;
232 	struct resource *res;
233 	struct mii_bus *bus;
234 	int ret;
235 
236 	regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
237 	if (IS_ERR(regs)) {
238 		dev_err(&pdev->dev, "Unable to map MIIM registers\n");
239 		return PTR_ERR(regs);
240 	}
241 
242 	mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
243 					   &mscc_miim_regmap_config);
244 
245 	if (IS_ERR(mii_regmap)) {
246 		dev_err(&pdev->dev, "Unable to create MIIM regmap\n");
247 		return PTR_ERR(mii_regmap);
248 	}
249 
250 	/* This resource is optional */
251 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
252 	if (res) {
253 		phy_regs = devm_ioremap_resource(&pdev->dev, res);
254 		if (IS_ERR(phy_regs)) {
255 			dev_err(&pdev->dev, "Unable to map internal phy registers\n");
256 			return PTR_ERR(phy_regs);
257 		}
258 
259 		phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs,
260 						   &mscc_miim_phy_regmap_config);
261 		if (IS_ERR(phy_regmap)) {
262 			dev_err(&pdev->dev, "Unable to create phy register regmap\n");
263 			return PTR_ERR(phy_regmap);
264 		}
265 	}
266 
267 	ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0);
268 	if (ret < 0) {
269 		dev_err(&pdev->dev, "Unable to setup the MDIO bus\n");
270 		return ret;
271 	}
272 
273 	miim = bus->priv;
274 	miim->phy_regs = phy_regmap;
275 	miim->phy_reset_offset = 0;
276 
277 	ret = of_mdiobus_register(bus, pdev->dev.of_node);
278 	if (ret < 0) {
279 		dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
280 		return ret;
281 	}
282 
283 	platform_set_drvdata(pdev, bus);
284 
285 	return 0;
286 }
287 
288 static int mscc_miim_remove(struct platform_device *pdev)
289 {
290 	struct mii_bus *bus = platform_get_drvdata(pdev);
291 
292 	mdiobus_unregister(bus);
293 
294 	return 0;
295 }
296 
297 static const struct of_device_id mscc_miim_match[] = {
298 	{ .compatible = "mscc,ocelot-miim" },
299 	{ }
300 };
301 MODULE_DEVICE_TABLE(of, mscc_miim_match);
302 
303 static struct platform_driver mscc_miim_driver = {
304 	.probe = mscc_miim_probe,
305 	.remove = mscc_miim_remove,
306 	.driver = {
307 		.name = "mscc-miim",
308 		.of_match_table = mscc_miim_match,
309 	},
310 };
311 
312 module_platform_driver(mscc_miim_driver);
313 
314 MODULE_DESCRIPTION("Microsemi MIIM driver");
315 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
316 MODULE_LICENSE("Dual MIT/GPL");
317