1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Driver for the MDIO interface of Microsemi network switches.
4  *
5  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
6  * Copyright (c) 2017 Microsemi Corporation
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mdio/mdio-mscc-miim.h>
15 #include <linux/mfd/ocelot.h>
16 #include <linux/module.h>
17 #include <linux/of_mdio.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 
23 #define MSCC_MIIM_REG_STATUS		0x0
24 #define		MSCC_MIIM_STATUS_STAT_PENDING	BIT(2)
25 #define		MSCC_MIIM_STATUS_STAT_BUSY	BIT(3)
26 #define MSCC_MIIM_REG_CMD		0x8
27 #define		MSCC_MIIM_CMD_OPR_WRITE		BIT(1)
28 #define		MSCC_MIIM_CMD_OPR_READ		BIT(2)
29 #define		MSCC_MIIM_CMD_WRDATA_SHIFT	4
30 #define		MSCC_MIIM_CMD_REGAD_SHIFT	20
31 #define		MSCC_MIIM_CMD_PHYAD_SHIFT	25
32 #define		MSCC_MIIM_CMD_VLD		BIT(31)
33 #define MSCC_MIIM_REG_DATA		0xC
34 #define		MSCC_MIIM_DATA_ERROR		(BIT(16) | BIT(17))
35 #define MSCC_MIIM_REG_CFG		0x10
36 #define		MSCC_MIIM_CFG_PRESCALE_MASK	GENMASK(7, 0)
37 
38 #define MSCC_PHY_REG_PHY_CFG	0x0
39 #define		PHY_CFG_PHY_ENA		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
40 #define		PHY_CFG_PHY_COMMON_RESET BIT(4)
41 #define		PHY_CFG_PHY_RESET	(BIT(5) | BIT(6) | BIT(7) | BIT(8))
42 #define MSCC_PHY_REG_PHY_STATUS	0x4
43 
44 #define LAN966X_CUPHY_COMMON_CFG	0x0
45 #define		CUPHY_COMMON_CFG_RESET_N	BIT(0)
46 
47 struct mscc_miim_info {
48 	unsigned int phy_reset_offset;
49 	unsigned int phy_reset_bits;
50 };
51 
52 struct mscc_miim_dev {
53 	struct regmap *regs;
54 	int mii_status_offset;
55 	struct regmap *phy_regs;
56 	const struct mscc_miim_info *info;
57 	struct clk *clk;
58 	u32 bus_freq;
59 };
60 
61 /* When high resolution timers aren't built-in: we can't use usleep_range() as
62  * we would sleep way too long. Use udelay() instead.
63  */
64 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
65 ({									  \
66 	if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS))			  \
67 		readx_poll_timeout_atomic(op, addr, val, cond, delay_us,  \
68 					  timeout_us);			  \
69 	readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us);	  \
70 })
71 
72 static int mscc_miim_status(struct mii_bus *bus)
73 {
74 	struct mscc_miim_dev *miim = bus->priv;
75 	int val, ret;
76 
77 	ret = regmap_read(miim->regs,
78 			  MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
79 	if (ret < 0) {
80 		WARN_ONCE(1, "mscc miim status read error %d\n", ret);
81 		return ret;
82 	}
83 
84 	return val;
85 }
86 
87 static int mscc_miim_wait_ready(struct mii_bus *bus)
88 {
89 	u32 val;
90 
91 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
92 				       !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
93 				       10000);
94 }
95 
96 static int mscc_miim_wait_pending(struct mii_bus *bus)
97 {
98 	u32 val;
99 
100 	return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
101 				       !(val & MSCC_MIIM_STATUS_STAT_PENDING),
102 				       50, 10000);
103 }
104 
105 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
106 {
107 	struct mscc_miim_dev *miim = bus->priv;
108 	u32 val;
109 	int ret;
110 
111 	ret = mscc_miim_wait_pending(bus);
112 	if (ret)
113 		goto out;
114 
115 	ret = regmap_write(miim->regs,
116 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
117 			   MSCC_MIIM_CMD_VLD |
118 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
119 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
120 			   MSCC_MIIM_CMD_OPR_READ);
121 
122 	if (ret < 0) {
123 		WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
124 		goto out;
125 	}
126 
127 	ret = mscc_miim_wait_ready(bus);
128 	if (ret)
129 		goto out;
130 
131 	ret = regmap_read(miim->regs,
132 			  MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
133 	if (ret < 0) {
134 		WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
135 		goto out;
136 	}
137 
138 	if (val & MSCC_MIIM_DATA_ERROR) {
139 		ret = -EIO;
140 		goto out;
141 	}
142 
143 	ret = val & 0xFFFF;
144 out:
145 	return ret;
146 }
147 
148 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
149 			   int regnum, u16 value)
150 {
151 	struct mscc_miim_dev *miim = bus->priv;
152 	int ret;
153 
154 	ret = mscc_miim_wait_pending(bus);
155 	if (ret < 0)
156 		goto out;
157 
158 	ret = regmap_write(miim->regs,
159 			   MSCC_MIIM_REG_CMD + miim->mii_status_offset,
160 			   MSCC_MIIM_CMD_VLD |
161 			   (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
162 			   (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
163 			   (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
164 			   MSCC_MIIM_CMD_OPR_WRITE);
165 
166 	if (ret < 0)
167 		WARN_ONCE(1, "mscc miim write error %d\n", ret);
168 out:
169 	return ret;
170 }
171 
172 static int mscc_miim_reset(struct mii_bus *bus)
173 {
174 	struct mscc_miim_dev *miim = bus->priv;
175 	unsigned int offset, bits;
176 	int ret;
177 
178 	if (!miim->phy_regs)
179 		return 0;
180 
181 	offset = miim->info->phy_reset_offset;
182 	bits = miim->info->phy_reset_bits;
183 
184 	ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
185 	if (ret < 0) {
186 		WARN_ONCE(1, "mscc reset set error %d\n", ret);
187 		return ret;
188 	}
189 
190 	ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
191 	if (ret < 0) {
192 		WARN_ONCE(1, "mscc reset clear error %d\n", ret);
193 		return ret;
194 	}
195 
196 	mdelay(500);
197 
198 	return 0;
199 }
200 
201 static const struct regmap_config mscc_miim_regmap_config = {
202 	.reg_bits	= 32,
203 	.val_bits	= 32,
204 	.reg_stride	= 4,
205 };
206 
207 static const struct regmap_config mscc_miim_phy_regmap_config = {
208 	.reg_bits	= 32,
209 	.val_bits	= 32,
210 	.reg_stride	= 4,
211 	.name		= "phy",
212 };
213 
214 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
215 		    struct regmap *mii_regmap, int status_offset)
216 {
217 	struct mscc_miim_dev *miim;
218 	struct mii_bus *bus;
219 
220 	bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
221 	if (!bus)
222 		return -ENOMEM;
223 
224 	bus->name = name;
225 	bus->read = mscc_miim_read;
226 	bus->write = mscc_miim_write;
227 	bus->reset = mscc_miim_reset;
228 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
229 	bus->parent = dev;
230 
231 	miim = bus->priv;
232 
233 	*pbus = bus;
234 
235 	miim->regs = mii_regmap;
236 	miim->mii_status_offset = status_offset;
237 
238 	*pbus = bus;
239 
240 	return 0;
241 }
242 EXPORT_SYMBOL(mscc_miim_setup);
243 
244 static int mscc_miim_clk_set(struct mii_bus *bus)
245 {
246 	struct mscc_miim_dev *miim = bus->priv;
247 	unsigned long rate;
248 	u32 div;
249 
250 	/* Keep the current settings */
251 	if (!miim->bus_freq)
252 		return 0;
253 
254 	rate = clk_get_rate(miim->clk);
255 
256 	div = DIV_ROUND_UP(rate, 2 * miim->bus_freq) - 1;
257 	if (div == 0 || div & ~MSCC_MIIM_CFG_PRESCALE_MASK) {
258 		dev_err(&bus->dev, "Incorrect MDIO clock frequency\n");
259 		return -EINVAL;
260 	}
261 
262 	return regmap_update_bits(miim->regs, MSCC_MIIM_REG_CFG,
263 				  MSCC_MIIM_CFG_PRESCALE_MASK, div);
264 }
265 
266 static int mscc_miim_probe(struct platform_device *pdev)
267 {
268 	struct device_node *np = pdev->dev.of_node;
269 	struct regmap *mii_regmap, *phy_regmap;
270 	struct device *dev = &pdev->dev;
271 	struct mscc_miim_dev *miim;
272 	struct mii_bus *bus;
273 	int ret;
274 
275 	mii_regmap = ocelot_regmap_from_resource(pdev, 0,
276 						 &mscc_miim_regmap_config);
277 	if (IS_ERR(mii_regmap))
278 		return dev_err_probe(dev, PTR_ERR(mii_regmap),
279 				     "Unable to create MIIM regmap\n");
280 
281 	/* This resource is optional */
282 	phy_regmap = ocelot_regmap_from_resource_optional(pdev, 1,
283 						 &mscc_miim_phy_regmap_config);
284 	if (IS_ERR(phy_regmap))
285 		return dev_err_probe(dev, PTR_ERR(phy_regmap),
286 				     "Unable to create phy register regmap\n");
287 
288 	ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0);
289 	if (ret < 0) {
290 		dev_err(dev, "Unable to setup the MDIO bus\n");
291 		return ret;
292 	}
293 
294 	miim = bus->priv;
295 	miim->phy_regs = phy_regmap;
296 
297 	miim->info = device_get_match_data(dev);
298 	if (!miim->info)
299 		return -EINVAL;
300 
301 	miim->clk = devm_clk_get_optional(dev, NULL);
302 	if (IS_ERR(miim->clk))
303 		return PTR_ERR(miim->clk);
304 
305 	of_property_read_u32(np, "clock-frequency", &miim->bus_freq);
306 
307 	if (miim->bus_freq && !miim->clk) {
308 		dev_err(dev, "cannot use clock-frequency without a clock\n");
309 		return -EINVAL;
310 	}
311 
312 	ret = clk_prepare_enable(miim->clk);
313 	if (ret)
314 		return ret;
315 
316 	ret = mscc_miim_clk_set(bus);
317 	if (ret)
318 		goto out_disable_clk;
319 
320 	ret = of_mdiobus_register(bus, np);
321 	if (ret < 0) {
322 		dev_err(dev, "Cannot register MDIO bus (%d)\n", ret);
323 		goto out_disable_clk;
324 	}
325 
326 	platform_set_drvdata(pdev, bus);
327 
328 	return 0;
329 
330 out_disable_clk:
331 	clk_disable_unprepare(miim->clk);
332 	return ret;
333 }
334 
335 static int mscc_miim_remove(struct platform_device *pdev)
336 {
337 	struct mii_bus *bus = platform_get_drvdata(pdev);
338 	struct mscc_miim_dev *miim = bus->priv;
339 
340 	clk_disable_unprepare(miim->clk);
341 	mdiobus_unregister(bus);
342 
343 	return 0;
344 }
345 
346 static const struct mscc_miim_info mscc_ocelot_miim_info = {
347 	.phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
348 	.phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
349 			  PHY_CFG_PHY_RESET,
350 };
351 
352 static const struct mscc_miim_info microchip_lan966x_miim_info = {
353 	.phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
354 	.phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
355 };
356 
357 static const struct of_device_id mscc_miim_match[] = {
358 	{
359 		.compatible = "mscc,ocelot-miim",
360 		.data = &mscc_ocelot_miim_info
361 	}, {
362 		.compatible = "microchip,lan966x-miim",
363 		.data = &microchip_lan966x_miim_info
364 	},
365 	{ }
366 };
367 MODULE_DEVICE_TABLE(of, mscc_miim_match);
368 
369 static struct platform_driver mscc_miim_driver = {
370 	.probe = mscc_miim_probe,
371 	.remove = mscc_miim_remove,
372 	.driver = {
373 		.name = "mscc-miim",
374 		.of_match_table = mscc_miim_match,
375 	},
376 };
377 
378 module_platform_driver(mscc_miim_driver);
379 
380 MODULE_DESCRIPTION("Microsemi MIIM driver");
381 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
382 MODULE_LICENSE("Dual MIT/GPL");
383