1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../ipa.h" 8 #include "../ipa_reg.h" 9 10 static const u32 ipa_reg_comp_cfg_fmask[] = { 11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 12 [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 /* Bit 4 reserved */ 16 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 17 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 28 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 29 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), 30 /* Bits 22-31 reserved */ 31 }; 32 33 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 34 35 static const u32 ipa_reg_clkon_cfg_fmask[] = { 36 [CLKON_RX] = BIT(0), 37 [CLKON_PROC] = BIT(1), 38 [TX_WRAPPER] = BIT(2), 39 [CLKON_MISC] = BIT(3), 40 [RAM_ARB] = BIT(4), 41 [FTCH_HPS] = BIT(5), 42 [FTCH_DPS] = BIT(6), 43 [CLKON_HPS] = BIT(7), 44 [CLKON_DPS] = BIT(8), 45 [RX_HPS_CMDQS] = BIT(9), 46 [HPS_DPS_CMDQS] = BIT(10), 47 [DPS_TX_CMDQS] = BIT(11), 48 [RSRC_MNGR] = BIT(12), 49 [CTX_HANDLER] = BIT(13), 50 [ACK_MNGR] = BIT(14), 51 [D_DCPH] = BIT(15), 52 [H_DCPH] = BIT(16), 53 [CLKON_DCMP] = BIT(17), 54 [NTF_TX_CMDQS] = BIT(18), 55 [CLKON_TX_0] = BIT(19), 56 [CLKON_TX_1] = BIT(20), 57 [CLKON_FNR] = BIT(21), 58 [QSB2AXI_CMDQ_L] = BIT(22), 59 [AGGR_WRAPPER] = BIT(23), 60 [RAM_SLAVEWAY] = BIT(24), 61 [CLKON_QMB] = BIT(25), 62 [WEIGHT_ARB] = BIT(26), 63 [GSI_IF] = BIT(27), 64 [CLKON_GLOBAL] = BIT(28), 65 [GLOBAL_2X_CLK] = BIT(29), 66 [DPL_FIFO] = BIT(30), 67 [DRBIP] = BIT(31), 68 }; 69 70 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 71 72 static const u32 ipa_reg_route_fmask[] = { 73 [ROUTE_DIS] = BIT(0), 74 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 75 [ROUTE_DEF_HDR_TABLE] = BIT(6), 76 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 77 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 78 /* Bits 22-23 reserved */ 79 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 80 /* Bits 25-31 reserved */ 81 }; 82 83 IPA_REG_FIELDS(ROUTE, route, 0x00000048); 84 85 static const u32 ipa_reg_shared_mem_size_fmask[] = { 86 [MEM_SIZE] = GENMASK(15, 0), 87 [MEM_BADDR] = GENMASK(31, 16), 88 }; 89 90 IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 91 92 static const u32 ipa_reg_qsb_max_writes_fmask[] = { 93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 95 /* Bits 8-31 reserved */ 96 }; 97 98 IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 99 100 static const u32 ipa_reg_qsb_max_reads_fmask[] = { 101 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 102 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 103 /* Bits 8-15 reserved */ 104 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 106 }; 107 108 IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 109 110 static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 111 [IPV6_ROUTER_HASH] = BIT(0), 112 /* Bits 1-3 reserved */ 113 [IPV6_FILTER_HASH] = BIT(4), 114 /* Bits 5-7 reserved */ 115 [IPV4_ROUTER_HASH] = BIT(8), 116 /* Bits 9-11 reserved */ 117 [IPV4_FILTER_HASH] = BIT(12), 118 /* Bits 13-31 reserved */ 119 }; 120 121 IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 122 123 static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 124 [IPV6_ROUTER_HASH] = BIT(0), 125 /* Bits 1-3 reserved */ 126 [IPV6_FILTER_HASH] = BIT(4), 127 /* Bits 5-7 reserved */ 128 [IPV4_ROUTER_HASH] = BIT(8), 129 /* Bits 9-11 reserved */ 130 [IPV4_FILTER_HASH] = BIT(12), 131 /* Bits 13-31 reserved */ 132 }; 133 134 IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 135 136 /* Valid bits defined by ipa->available */ 137 IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 138 139 static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 140 [IPA_BASE_ADDR] = GENMASK(17, 0), 141 /* Bits 18-31 reserved */ 142 }; 143 144 /* Offset must be a multiple of 8 */ 145 IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 146 147 /* Valid bits defined by ipa->available */ 148 IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 149 150 static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 151 /* Bits 0-1 reserved */ 152 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 153 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 154 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 155 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 156 [PA_MASK_EN] = BIT(12), 157 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 158 [DUAL_TX_ENABLE] = BIT(17), 159 [SSPND_PA_NO_START_STATE] = BIT(18), 160 /* Bits 19-31 reserved */ 161 }; 162 163 IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 164 165 static const u32 ipa_reg_flavor_0_fmask[] = { 166 [MAX_PIPES] = GENMASK(3, 0), 167 /* Bits 4-7 reserved */ 168 [MAX_CONS_PIPES] = GENMASK(12, 8), 169 /* Bits 13-15 reserved */ 170 [MAX_PROD_PIPES] = GENMASK(20, 16), 171 /* Bits 21-23 reserved */ 172 [PROD_LOWEST] = GENMASK(27, 24), 173 /* Bits 28-31 reserved */ 174 }; 175 176 IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 177 178 static const u32 ipa_reg_idle_indication_cfg_fmask[] = { 179 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 180 [CONST_NON_IDLE_ENABLE] = BIT(16), 181 /* Bits 17-31 reserved */ 182 }; 183 184 IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 185 186 static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = { 187 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 188 /* Bits 5-6 reserved */ 189 [DPL_TIMESTAMP_SEL] = BIT(7), 190 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 191 /* Bits 13-15 reserved */ 192 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 193 /* Bits 21-31 reserved */ 194 }; 195 196 IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 197 198 static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = { 199 [DIV_VALUE] = GENMASK(8, 0), 200 /* Bits 9-30 reserved */ 201 [DIV_ENABLE] = BIT(31), 202 }; 203 204 IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 205 206 static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = { 207 [PULSE_GRAN_0] = GENMASK(2, 0), 208 [PULSE_GRAN_1] = GENMASK(5, 3), 209 [PULSE_GRAN_2] = GENMASK(8, 6), 210 }; 211 212 IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 213 214 static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 215 [X_MIN_LIM] = GENMASK(5, 0), 216 /* Bits 6-7 reserved */ 217 [X_MAX_LIM] = GENMASK(13, 8), 218 /* Bits 14-15 reserved */ 219 [Y_MIN_LIM] = GENMASK(21, 16), 220 /* Bits 22-23 reserved */ 221 [Y_MAX_LIM] = GENMASK(29, 24), 222 /* Bits 30-31 reserved */ 223 }; 224 225 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 226 0x00000400, 0x0020); 227 228 static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 229 [X_MIN_LIM] = GENMASK(5, 0), 230 /* Bits 6-7 reserved */ 231 [X_MAX_LIM] = GENMASK(13, 8), 232 /* Bits 14-15 reserved */ 233 [Y_MIN_LIM] = GENMASK(21, 16), 234 /* Bits 22-23 reserved */ 235 [Y_MAX_LIM] = GENMASK(29, 24), 236 /* Bits 30-31 reserved */ 237 }; 238 239 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 240 0x00000404, 0x0020); 241 242 static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 243 [X_MIN_LIM] = GENMASK(5, 0), 244 /* Bits 6-7 reserved */ 245 [X_MAX_LIM] = GENMASK(13, 8), 246 /* Bits 14-15 reserved */ 247 [Y_MIN_LIM] = GENMASK(21, 16), 248 /* Bits 22-23 reserved */ 249 [Y_MAX_LIM] = GENMASK(29, 24), 250 /* Bits 30-31 reserved */ 251 }; 252 253 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 254 0x00000500, 0x0020); 255 256 static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 257 [X_MIN_LIM] = GENMASK(5, 0), 258 /* Bits 6-7 reserved */ 259 [X_MAX_LIM] = GENMASK(13, 8), 260 /* Bits 14-15 reserved */ 261 [Y_MIN_LIM] = GENMASK(21, 16), 262 /* Bits 22-23 reserved */ 263 [Y_MAX_LIM] = GENMASK(29, 24), 264 /* Bits 30-31 reserved */ 265 }; 266 267 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 268 0x00000504, 0x0020); 269 270 static const u32 ipa_reg_endp_init_cfg_fmask[] = { 271 [FRAG_OFFLOAD_EN] = BIT(0), 272 [CS_OFFLOAD_EN] = GENMASK(2, 1), 273 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 274 /* Bit 7 reserved */ 275 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 276 /* Bits 9-31 reserved */ 277 }; 278 279 IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 280 281 static const u32 ipa_reg_endp_init_nat_fmask[] = { 282 [NAT_EN] = GENMASK(1, 0), 283 /* Bits 2-31 reserved */ 284 }; 285 286 IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 287 288 static const u32 ipa_reg_endp_init_hdr_fmask[] = { 289 [HDR_LEN] = GENMASK(5, 0), 290 [HDR_OFST_METADATA_VALID] = BIT(6), 291 [HDR_OFST_METADATA] = GENMASK(12, 7), 292 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 293 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 294 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 295 [HDR_A5_MUX] = BIT(26), 296 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 297 [HDR_LEN_MSB] = GENMASK(29, 28), 298 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 299 }; 300 301 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 302 303 static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 304 [HDR_ENDIANNESS] = BIT(0), 305 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 306 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 307 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 308 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 309 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 310 /* Bits 14-15 reserved */ 311 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 312 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 313 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 314 /* Bits 22-31 reserved */ 315 }; 316 317 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 318 319 IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 320 0x00000818, 0x0070); 321 322 static const u32 ipa_reg_endp_init_mode_fmask[] = { 323 [ENDP_MODE] = GENMASK(2, 0), 324 [DCPH_ENABLE] = BIT(3), 325 [DEST_PIPE_INDEX] = GENMASK(8, 4), 326 /* Bits 9-11 reserved */ 327 [BYTE_THRESHOLD] = GENMASK(27, 12), 328 [PIPE_REPLICATION_EN] = BIT(28), 329 [PAD_EN] = BIT(29), 330 /* Bits 30-31 reserved */ 331 }; 332 333 IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 334 335 static const u32 ipa_reg_endp_init_aggr_fmask[] = { 336 [AGGR_EN] = GENMASK(1, 0), 337 [AGGR_TYPE] = GENMASK(4, 2), 338 [BYTE_LIMIT] = GENMASK(10, 5), 339 /* Bit 11 reserved */ 340 [TIME_LIMIT] = GENMASK(16, 12), 341 [PKT_LIMIT] = GENMASK(22, 17), 342 [SW_EOF_ACTIVE] = BIT(23), 343 [FORCE_CLOSE] = BIT(24), 344 /* Bit 25 reserved */ 345 [HARD_BYTE_LIMIT_EN] = BIT(26), 346 [AGGR_GRAN_SEL] = BIT(27), 347 /* Bits 28-31 reserved */ 348 }; 349 350 IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 351 352 static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 353 [HOL_BLOCK_EN] = BIT(0), 354 /* Bits 1-31 reserved */ 355 }; 356 357 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 358 0x0000082c, 0x0070); 359 360 static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 361 [TIMER_LIMIT] = GENMASK(4, 0), 362 /* Bits 5-7 reserved */ 363 [TIMER_GRAN_SEL] = BIT(8), 364 /* Bits 9-31 reserved */ 365 }; 366 367 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 368 0x00000830, 0x0070); 369 370 static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 371 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 372 [SYSPIPE_ERR_DETECTION] = BIT(6), 373 [PACKET_OFFSET_VALID] = BIT(7), 374 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 375 [IGNORE_MIN_PKT_ERR] = BIT(14), 376 /* Bit 15 reserved */ 377 [MAX_PACKET_LEN] = GENMASK(31, 16), 378 }; 379 380 IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 381 382 static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 383 [ENDP_RSRC_GRP] = BIT(0), 384 /* Bits 1-31 reserved */ 385 }; 386 387 IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 388 0x00000838, 0x0070); 389 390 static const u32 ipa_reg_endp_init_seq_fmask[] = { 391 [SEQ_TYPE] = GENMASK(7, 0), 392 /* Bits 8-31 reserved */ 393 }; 394 395 IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 396 397 static const u32 ipa_reg_endp_status_fmask[] = { 398 [STATUS_EN] = BIT(0), 399 [STATUS_ENDP] = GENMASK(5, 1), 400 /* Bits 6-8 reserved */ 401 [STATUS_PKT_SUPPRESS] = BIT(9), 402 /* Bits 10-31 reserved */ 403 }; 404 405 IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 406 407 static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 408 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 409 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 410 [FILTER_HASH_MSK_DST_IP] = BIT(2), 411 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 412 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 413 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 414 [FILTER_HASH_MSK_METADATA] = BIT(6), 415 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 416 /* Bits 7-15 reserved */ 417 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 418 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 419 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 420 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 421 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 422 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 423 [ROUTER_HASH_MSK_METADATA] = BIT(22), 424 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 425 /* Bits 23-31 reserved */ 426 }; 427 428 IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 429 0x0000085c, 0x0070); 430 431 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 432 IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 433 434 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 435 IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 436 437 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 438 IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 439 440 static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 441 [UC_INTR] = BIT(0), 442 /* Bits 1-31 reserved */ 443 }; 444 445 IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 446 447 /* Valid bits defined by ipa->available */ 448 IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 449 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 450 451 /* Valid bits defined by ipa->available */ 452 IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 453 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 454 455 /* Valid bits defined by ipa->available */ 456 IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 457 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 458 459 static const struct ipa_reg *ipa_reg_array[] = { 460 [COMP_CFG] = &ipa_reg_comp_cfg, 461 [CLKON_CFG] = &ipa_reg_clkon_cfg, 462 [ROUTE] = &ipa_reg_route, 463 [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 464 [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 465 [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 466 [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 467 [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 468 [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 469 [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 470 [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 471 [IPA_TX_CFG] = &ipa_reg_ipa_tx_cfg, 472 [FLAVOR_0] = &ipa_reg_flavor_0, 473 [IDLE_INDICATION_CFG] = &ipa_reg_idle_indication_cfg, 474 [QTIME_TIMESTAMP_CFG] = &ipa_reg_qtime_timestamp_cfg, 475 [TIMERS_XO_CLK_DIV_CFG] = &ipa_reg_timers_xo_clk_div_cfg, 476 [TIMERS_PULSE_GRAN_CFG] = &ipa_reg_timers_pulse_gran_cfg, 477 [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 478 [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 479 [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 480 [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 481 [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 482 [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 483 [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 484 [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 485 [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 486 [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 487 [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 488 [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 489 [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 490 [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 491 [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 492 [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 493 [ENDP_STATUS] = &ipa_reg_endp_status, 494 [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 495 [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 496 [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 497 [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 498 [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 499 [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 500 [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 501 [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 502 }; 503 504 const struct ipa_regs ipa_regs_v4_7 = { 505 .reg_count = ARRAY_SIZE(ipa_reg_array), 506 .reg = ipa_reg_array, 507 }; 508