1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../ipa.h" 8 #include "../ipa_reg.h" 9 10 static const u32 ipa_reg_comp_cfg_fmask[] = { 11 [COMP_CFG_ENABLE] = BIT(0), 12 [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 /* Bits 5-31 reserved */ 17 }; 18 19 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 20 21 static const u32 ipa_reg_clkon_cfg_fmask[] = { 22 [CLKON_RX] = BIT(0), 23 [CLKON_PROC] = BIT(1), 24 [TX_WRAPPER] = BIT(2), 25 [CLKON_MISC] = BIT(3), 26 [RAM_ARB] = BIT(4), 27 [FTCH_HPS] = BIT(5), 28 [FTCH_DPS] = BIT(6), 29 [CLKON_HPS] = BIT(7), 30 [CLKON_DPS] = BIT(8), 31 [RX_HPS_CMDQS] = BIT(9), 32 [HPS_DPS_CMDQS] = BIT(10), 33 [DPS_TX_CMDQS] = BIT(11), 34 [RSRC_MNGR] = BIT(12), 35 [CTX_HANDLER] = BIT(13), 36 [ACK_MNGR] = BIT(14), 37 [D_DCPH] = BIT(15), 38 [H_DCPH] = BIT(16), 39 /* Bits 17-31 reserved */ 40 }; 41 42 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 43 44 static const u32 ipa_reg_route_fmask[] = { 45 [ROUTE_DIS] = BIT(0), 46 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 47 [ROUTE_DEF_HDR_TABLE] = BIT(6), 48 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 49 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 50 /* Bits 22-23 reserved */ 51 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 52 /* Bits 25-31 reserved */ 53 }; 54 55 IPA_REG_FIELDS(ROUTE, route, 0x00000048); 56 57 static const u32 ipa_reg_shared_mem_size_fmask[] = { 58 [MEM_SIZE] = GENMASK(15, 0), 59 [MEM_BADDR] = GENMASK(31, 16), 60 }; 61 62 IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 63 64 static const u32 ipa_reg_qsb_max_writes_fmask[] = { 65 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 66 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 67 /* Bits 8-31 reserved */ 68 }; 69 70 IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 71 72 static const u32 ipa_reg_qsb_max_reads_fmask[] = { 73 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 74 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 75 }; 76 77 IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 78 79 static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 80 [IPV6_ROUTER_HASH] = BIT(0), 81 /* Bits 1-3 reserved */ 82 [IPV6_FILTER_HASH] = BIT(4), 83 /* Bits 5-7 reserved */ 84 [IPV4_ROUTER_HASH] = BIT(8), 85 /* Bits 9-11 reserved */ 86 [IPV4_FILTER_HASH] = BIT(12), 87 /* Bits 13-31 reserved */ 88 }; 89 90 IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 91 92 static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 93 [IPV6_ROUTER_HASH] = BIT(0), 94 /* Bits 1-3 reserved */ 95 [IPV6_FILTER_HASH] = BIT(4), 96 /* Bits 5-7 reserved */ 97 [IPV4_ROUTER_HASH] = BIT(8), 98 /* Bits 9-11 reserved */ 99 [IPV4_FILTER_HASH] = BIT(12), 100 /* Bits 13-31 reserved */ 101 }; 102 103 IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 104 105 /* Valid bits defined by ipa->available */ 106 IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); 107 108 IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); 109 110 static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 111 [IPA_BASE_ADDR] = GENMASK(16, 0), 112 /* Bits 17-31 reserved */ 113 }; 114 115 /* Offset must be a multiple of 8 */ 116 IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 117 118 /* Valid bits defined by ipa->available */ 119 IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 120 121 static const u32 ipa_reg_counter_cfg_fmask[] = { 122 [EOT_COAL_GRANULARITY] = GENMASK(3, 0), 123 [AGGR_GRANULARITY] = GENMASK(8, 4), 124 /* Bits 5-31 reserved */ 125 }; 126 127 IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 128 129 static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 130 [X_MIN_LIM] = GENMASK(7, 0), 131 [X_MAX_LIM] = GENMASK(15, 8), 132 [Y_MIN_LIM] = GENMASK(23, 16), 133 [Y_MAX_LIM] = GENMASK(31, 24), 134 }; 135 136 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 137 0x00000400, 0x0020); 138 139 static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 140 [X_MIN_LIM] = GENMASK(7, 0), 141 [X_MAX_LIM] = GENMASK(15, 8), 142 [Y_MIN_LIM] = GENMASK(23, 16), 143 [Y_MAX_LIM] = GENMASK(31, 24), 144 }; 145 146 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 147 0x00000404, 0x0020); 148 149 static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 150 [X_MIN_LIM] = GENMASK(7, 0), 151 [X_MAX_LIM] = GENMASK(15, 8), 152 [Y_MIN_LIM] = GENMASK(23, 16), 153 [Y_MAX_LIM] = GENMASK(31, 24), 154 }; 155 156 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 157 0x00000408, 0x0020); 158 159 static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 160 [X_MIN_LIM] = GENMASK(7, 0), 161 [X_MAX_LIM] = GENMASK(15, 8), 162 [Y_MIN_LIM] = GENMASK(23, 16), 163 [Y_MAX_LIM] = GENMASK(31, 24), 164 }; 165 166 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 167 0x0000040c, 0x0020); 168 169 static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 170 [X_MIN_LIM] = GENMASK(7, 0), 171 [X_MAX_LIM] = GENMASK(15, 8), 172 [Y_MIN_LIM] = GENMASK(23, 16), 173 [Y_MAX_LIM] = GENMASK(31, 24), 174 }; 175 176 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 177 0x00000500, 0x0020); 178 179 static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 180 [X_MIN_LIM] = GENMASK(7, 0), 181 [X_MAX_LIM] = GENMASK(15, 8), 182 [Y_MIN_LIM] = GENMASK(23, 16), 183 [Y_MAX_LIM] = GENMASK(31, 24), 184 }; 185 186 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 187 0x00000504, 0x0020); 188 189 static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 190 [X_MIN_LIM] = GENMASK(7, 0), 191 [X_MAX_LIM] = GENMASK(15, 8), 192 [Y_MIN_LIM] = GENMASK(23, 16), 193 [Y_MAX_LIM] = GENMASK(31, 24), 194 }; 195 196 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 197 0x00000508, 0x0020); 198 199 static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 200 [X_MIN_LIM] = GENMASK(7, 0), 201 [X_MAX_LIM] = GENMASK(15, 8), 202 [Y_MIN_LIM] = GENMASK(23, 16), 203 [Y_MAX_LIM] = GENMASK(31, 24), 204 }; 205 206 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 207 0x0000050c, 0x0020); 208 209 static const u32 ipa_reg_endp_init_ctrl_fmask[] = { 210 [ENDP_SUSPEND] = BIT(0), 211 [ENDP_DELAY] = BIT(1), 212 /* Bits 2-31 reserved */ 213 }; 214 215 IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 216 217 static const u32 ipa_reg_endp_init_cfg_fmask[] = { 218 [FRAG_OFFLOAD_EN] = BIT(0), 219 [CS_OFFLOAD_EN] = GENMASK(2, 1), 220 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 221 /* Bit 7 reserved */ 222 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 223 /* Bits 9-31 reserved */ 224 }; 225 226 IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 227 228 static const u32 ipa_reg_endp_init_nat_fmask[] = { 229 [NAT_EN] = GENMASK(1, 0), 230 /* Bits 2-31 reserved */ 231 }; 232 233 IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 234 235 static const u32 ipa_reg_endp_init_hdr_fmask[] = { 236 [HDR_LEN] = GENMASK(5, 0), 237 [HDR_OFST_METADATA_VALID] = BIT(6), 238 [HDR_OFST_METADATA] = GENMASK(12, 7), 239 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 240 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 241 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 242 [HDR_A5_MUX] = BIT(26), 243 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 244 [HDR_METADATA_REG_VALID] = BIT(28), 245 /* Bits 29-31 reserved */ 246 }; 247 248 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 249 250 static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 251 [HDR_ENDIANNESS] = BIT(0), 252 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 253 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 254 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 255 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 256 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 257 /* Bits 14-31 reserved */ 258 }; 259 260 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 261 262 IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 263 0x00000818, 0x0070); 264 265 static const u32 ipa_reg_endp_init_mode_fmask[] = { 266 [ENDP_MODE] = GENMASK(2, 0), 267 /* Bit 3 reserved */ 268 [DEST_PIPE_INDEX] = GENMASK(8, 4), 269 /* Bits 9-11 reserved */ 270 [BYTE_THRESHOLD] = GENMASK(27, 12), 271 [PIPE_REPLICATION_EN] = BIT(28), 272 [PAD_EN] = BIT(29), 273 [HDR_FTCH_DISABLE] = BIT(30), 274 /* Bit 31 reserved */ 275 }; 276 277 IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 278 279 static const u32 ipa_reg_endp_init_aggr_fmask[] = { 280 [AGGR_EN] = GENMASK(1, 0), 281 [AGGR_TYPE] = GENMASK(4, 2), 282 [BYTE_LIMIT] = GENMASK(9, 5), 283 [TIME_LIMIT] = GENMASK(14, 10), 284 [PKT_LIMIT] = GENMASK(20, 15), 285 [SW_EOF_ACTIVE] = BIT(21), 286 [FORCE_CLOSE] = BIT(22), 287 /* Bit 23 reserved */ 288 [HARD_BYTE_LIMIT_EN] = BIT(24), 289 /* Bits 25-31 reserved */ 290 }; 291 292 IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 293 294 static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 295 [HOL_BLOCK_EN] = BIT(0), 296 /* Bits 1-31 reserved */ 297 }; 298 299 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 300 0x0000082c, 0x0070); 301 302 /* Entire register is a tick count */ 303 static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 304 [TIMER_BASE_VALUE] = GENMASK(31, 0), 305 }; 306 307 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 308 0x00000830, 0x0070); 309 310 static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 311 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 312 [SYSPIPE_ERR_DETECTION] = BIT(6), 313 [PACKET_OFFSET_VALID] = BIT(7), 314 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 315 [IGNORE_MIN_PKT_ERR] = BIT(14), 316 /* Bit 15 reserved */ 317 [MAX_PACKET_LEN] = GENMASK(31, 16), 318 }; 319 320 IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 321 322 static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 323 [ENDP_RSRC_GRP] = GENMASK(2, 0), 324 /* Bits 3-31 reserved */ 325 }; 326 327 IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 328 0x00000838, 0x0070); 329 330 static const u32 ipa_reg_endp_init_seq_fmask[] = { 331 [SEQ_TYPE] = GENMASK(7, 0), 332 [SEQ_REP_TYPE] = GENMASK(15, 8), 333 /* Bits 16-31 reserved */ 334 }; 335 336 IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 337 338 static const u32 ipa_reg_endp_status_fmask[] = { 339 [STATUS_EN] = BIT(0), 340 [STATUS_ENDP] = GENMASK(5, 1), 341 /* Bits 6-7 reserved */ 342 [STATUS_LOCATION] = BIT(8), 343 /* Bits 9-31 reserved */ 344 }; 345 346 IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 347 348 static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 349 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 350 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 351 [FILTER_HASH_MSK_DST_IP] = BIT(2), 352 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 353 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 354 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 355 [FILTER_HASH_MSK_METADATA] = BIT(6), 356 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 357 /* Bits 7-15 reserved */ 358 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 359 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 360 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 361 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 362 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 363 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 364 [ROUTER_HASH_MSK_METADATA] = BIT(22), 365 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 366 /* Bits 23-31 reserved */ 367 }; 368 369 IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 370 0x0000085c, 0x0070); 371 372 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 373 IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 374 375 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 376 IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 377 378 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 379 IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 380 381 static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 382 [UC_INTR] = BIT(0), 383 /* Bits 1-31 reserved */ 384 }; 385 386 IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 387 388 /* Valid bits defined by ipa->available */ 389 IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 390 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 391 392 /* Valid bits defined by ipa->available */ 393 IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 394 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 395 396 /* Valid bits defined by ipa->available */ 397 IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 398 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 399 400 static const struct ipa_reg *ipa_reg_array[] = { 401 [COMP_CFG] = &ipa_reg_comp_cfg, 402 [CLKON_CFG] = &ipa_reg_clkon_cfg, 403 [ROUTE] = &ipa_reg_route, 404 [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 405 [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 406 [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 407 [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 408 [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 409 [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 410 [IPA_BCR] = &ipa_reg_ipa_bcr, 411 [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 412 [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 413 [COUNTER_CFG] = &ipa_reg_counter_cfg, 414 [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 415 [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 416 [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, 417 [SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type, 418 [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 419 [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 420 [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, 421 [DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type, 422 [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, 423 [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 424 [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 425 [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 426 [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 427 [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 428 [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 429 [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 430 [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 431 [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 432 [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 433 [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 434 [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 435 [ENDP_STATUS] = &ipa_reg_endp_status, 436 [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 437 [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 438 [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 439 [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 440 [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 441 [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 442 [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 443 [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 444 }; 445 446 const struct ipa_regs ipa_regs_v3_1 = { 447 .reg_count = ARRAY_SIZE(ipa_reg_array), 448 .reg = ipa_reg_array, 449 }; 450