1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../ipa.h" 8 #include "../ipa_reg.h" 9 10 static const u32 ipa_reg_comp_cfg_fmask[] = { 11 [COMP_CFG_ENABLE] = BIT(0), 12 [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 /* Bits 5-31 reserved */ 17 }; 18 19 IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 20 21 static const u32 ipa_reg_clkon_cfg_fmask[] = { 22 [CLKON_RX] = BIT(0), 23 [CLKON_PROC] = BIT(1), 24 [TX_WRAPPER] = BIT(2), 25 [CLKON_MISC] = BIT(3), 26 [RAM_ARB] = BIT(4), 27 [FTCH_HPS] = BIT(5), 28 [FTCH_DPS] = BIT(6), 29 [CLKON_HPS] = BIT(7), 30 [CLKON_DPS] = BIT(8), 31 [RX_HPS_CMDQS] = BIT(9), 32 [HPS_DPS_CMDQS] = BIT(10), 33 [DPS_TX_CMDQS] = BIT(11), 34 [RSRC_MNGR] = BIT(12), 35 [CTX_HANDLER] = BIT(13), 36 [ACK_MNGR] = BIT(14), 37 [D_DCPH] = BIT(15), 38 [H_DCPH] = BIT(16), 39 /* Bits 17-31 reserved */ 40 }; 41 42 IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 43 44 static const u32 ipa_reg_route_fmask[] = { 45 [ROUTE_DIS] = BIT(0), 46 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 47 [ROUTE_DEF_HDR_TABLE] = BIT(6), 48 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 49 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 50 /* Bits 22-23 reserved */ 51 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 52 /* Bits 25-31 reserved */ 53 }; 54 55 IPA_REG_FIELDS(ROUTE, route, 0x00000048); 56 57 static const u32 ipa_reg_shared_mem_size_fmask[] = { 58 [MEM_SIZE] = GENMASK(15, 0), 59 [MEM_BADDR] = GENMASK(31, 16), 60 }; 61 62 IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 63 64 static const u32 ipa_reg_qsb_max_writes_fmask[] = { 65 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 66 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 67 /* Bits 8-31 reserved */ 68 }; 69 70 IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 71 72 static const u32 ipa_reg_qsb_max_reads_fmask[] = { 73 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 74 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 75 }; 76 77 IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 78 79 static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { 80 [IPV6_ROUTER_HASH] = BIT(0), 81 /* Bits 1-3 reserved */ 82 [IPV6_FILTER_HASH] = BIT(4), 83 /* Bits 5-7 reserved */ 84 [IPV4_ROUTER_HASH] = BIT(8), 85 /* Bits 9-11 reserved */ 86 [IPV4_FILTER_HASH] = BIT(12), 87 /* Bits 13-31 reserved */ 88 }; 89 90 IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 91 92 static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { 93 [IPV6_ROUTER_HASH] = BIT(0), 94 /* Bits 1-3 reserved */ 95 [IPV6_FILTER_HASH] = BIT(4), 96 /* Bits 5-7 reserved */ 97 [IPV4_ROUTER_HASH] = BIT(8), 98 /* Bits 9-11 reserved */ 99 [IPV4_FILTER_HASH] = BIT(12), 100 /* Bits 13-31 reserved */ 101 }; 102 103 IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 104 105 /* Valid bits defined by ipa->available */ 106 IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); 107 108 IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); 109 110 static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { 111 [IPA_BASE_ADDR] = GENMASK(16, 0), 112 /* Bits 17-31 reserved */ 113 }; 114 115 /* Offset must be a multiple of 8 */ 116 IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 117 118 /* Valid bits defined by ipa->available */ 119 IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec); 120 121 static const u32 ipa_reg_counter_cfg_fmask[] = { 122 [EOT_COAL_GRANULARITY] = GENMASK(3, 0), 123 [AGGR_GRANULARITY] = GENMASK(8, 4), 124 /* Bits 5-31 reserved */ 125 }; 126 127 IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 128 129 static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 130 [X_MIN_LIM] = GENMASK(5, 0), 131 /* Bits 6-7 reserved */ 132 [X_MAX_LIM] = GENMASK(13, 8), 133 /* Bits 14-15 reserved */ 134 [Y_MIN_LIM] = GENMASK(21, 16), 135 /* Bits 22-23 reserved */ 136 [Y_MAX_LIM] = GENMASK(29, 24), 137 /* Bits 30-31 reserved */ 138 }; 139 140 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 141 0x00000400, 0x0020); 142 143 static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 144 [X_MIN_LIM] = GENMASK(5, 0), 145 /* Bits 6-7 reserved */ 146 [X_MAX_LIM] = GENMASK(13, 8), 147 /* Bits 14-15 reserved */ 148 [Y_MIN_LIM] = GENMASK(21, 16), 149 /* Bits 22-23 reserved */ 150 [Y_MAX_LIM] = GENMASK(29, 24), 151 /* Bits 30-31 reserved */ 152 }; 153 154 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 155 0x00000404, 0x0020); 156 157 static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 158 [X_MIN_LIM] = GENMASK(5, 0), 159 /* Bits 6-7 reserved */ 160 [X_MAX_LIM] = GENMASK(13, 8), 161 /* Bits 14-15 reserved */ 162 [Y_MIN_LIM] = GENMASK(21, 16), 163 /* Bits 22-23 reserved */ 164 [Y_MAX_LIM] = GENMASK(29, 24), 165 /* Bits 30-31 reserved */ 166 }; 167 168 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 169 0x00000408, 0x0020); 170 171 static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 172 [X_MIN_LIM] = GENMASK(5, 0), 173 /* Bits 6-7 reserved */ 174 [X_MAX_LIM] = GENMASK(13, 8), 175 /* Bits 14-15 reserved */ 176 [Y_MIN_LIM] = GENMASK(21, 16), 177 /* Bits 22-23 reserved */ 178 [Y_MAX_LIM] = GENMASK(29, 24), 179 /* Bits 30-31 reserved */ 180 }; 181 182 IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 183 0x0000040c, 0x0020); 184 185 static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 186 [X_MIN_LIM] = GENMASK(5, 0), 187 /* Bits 6-7 reserved */ 188 [X_MAX_LIM] = GENMASK(13, 8), 189 /* Bits 14-15 reserved */ 190 [Y_MIN_LIM] = GENMASK(21, 16), 191 /* Bits 22-23 reserved */ 192 [Y_MAX_LIM] = GENMASK(29, 24), 193 /* Bits 30-31 reserved */ 194 }; 195 196 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 197 0x00000500, 0x0020); 198 199 static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 200 [X_MIN_LIM] = GENMASK(5, 0), 201 /* Bits 6-7 reserved */ 202 [X_MAX_LIM] = GENMASK(13, 8), 203 /* Bits 14-15 reserved */ 204 [Y_MIN_LIM] = GENMASK(21, 16), 205 /* Bits 22-23 reserved */ 206 [Y_MAX_LIM] = GENMASK(29, 24), 207 /* Bits 30-31 reserved */ 208 }; 209 210 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 211 0x00000504, 0x0020); 212 213 static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 214 [X_MIN_LIM] = GENMASK(5, 0), 215 /* Bits 6-7 reserved */ 216 [X_MAX_LIM] = GENMASK(13, 8), 217 /* Bits 14-15 reserved */ 218 [Y_MIN_LIM] = GENMASK(21, 16), 219 /* Bits 22-23 reserved */ 220 [Y_MAX_LIM] = GENMASK(29, 24), 221 /* Bits 30-31 reserved */ 222 }; 223 224 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 225 0x00000508, 0x0020); 226 227 static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 228 [X_MIN_LIM] = GENMASK(5, 0), 229 /* Bits 6-7 reserved */ 230 [X_MAX_LIM] = GENMASK(13, 8), 231 /* Bits 14-15 reserved */ 232 [Y_MIN_LIM] = GENMASK(21, 16), 233 /* Bits 22-23 reserved */ 234 [Y_MAX_LIM] = GENMASK(29, 24), 235 /* Bits 30-31 reserved */ 236 }; 237 238 IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 239 0x0000050c, 0x0020); 240 241 static const u32 ipa_reg_endp_init_ctrl_fmask[] = { 242 [ENDP_SUSPEND] = BIT(0), 243 [ENDP_DELAY] = BIT(1), 244 /* Bits 2-31 reserved */ 245 }; 246 247 IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 248 249 static const u32 ipa_reg_endp_init_cfg_fmask[] = { 250 [FRAG_OFFLOAD_EN] = BIT(0), 251 [CS_OFFLOAD_EN] = GENMASK(2, 1), 252 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 253 /* Bit 7 reserved */ 254 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 255 /* Bits 9-31 reserved */ 256 }; 257 258 IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 259 260 static const u32 ipa_reg_endp_init_nat_fmask[] = { 261 [NAT_EN] = GENMASK(1, 0), 262 /* Bits 2-31 reserved */ 263 }; 264 265 IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 266 267 static const u32 ipa_reg_endp_init_hdr_fmask[] = { 268 [HDR_LEN] = GENMASK(5, 0), 269 [HDR_OFST_METADATA_VALID] = BIT(6), 270 [HDR_OFST_METADATA] = GENMASK(12, 7), 271 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 272 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 273 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 274 [HDR_A5_MUX] = BIT(26), 275 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 276 [HDR_METADATA_REG_VALID] = BIT(28), 277 /* Bits 29-31 reserved */ 278 }; 279 280 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 281 282 static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { 283 [HDR_ENDIANNESS] = BIT(0), 284 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 285 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 286 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 287 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 288 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 289 /* Bits 14-31 reserved */ 290 }; 291 292 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 293 294 IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 295 0x00000818, 0x0070); 296 297 static const u32 ipa_reg_endp_init_mode_fmask[] = { 298 [ENDP_MODE] = GENMASK(2, 0), 299 /* Bit 3 reserved */ 300 [DEST_PIPE_INDEX] = GENMASK(8, 4), 301 /* Bits 9-11 reserved */ 302 [BYTE_THRESHOLD] = GENMASK(27, 12), 303 [PIPE_REPLICATION_EN] = BIT(28), 304 [PAD_EN] = BIT(29), 305 [HDR_FTCH_DISABLE] = BIT(30), 306 /* Bit 31 reserved */ 307 }; 308 309 IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 310 311 static const u32 ipa_reg_endp_init_aggr_fmask[] = { 312 [AGGR_EN] = GENMASK(1, 0), 313 [AGGR_TYPE] = GENMASK(4, 2), 314 [BYTE_LIMIT] = GENMASK(9, 5), 315 [TIME_LIMIT] = GENMASK(14, 10), 316 [PKT_LIMIT] = GENMASK(20, 15), 317 [SW_EOF_ACTIVE] = BIT(21), 318 [FORCE_CLOSE] = BIT(22), 319 /* Bit 23 reserved */ 320 [HARD_BYTE_LIMIT_EN] = BIT(24), 321 /* Bits 25-31 reserved */ 322 }; 323 324 IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 325 326 static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { 327 [HOL_BLOCK_EN] = BIT(0), 328 /* Bits 1-31 reserved */ 329 }; 330 331 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 332 0x0000082c, 0x0070); 333 334 /* Entire register is a tick count */ 335 static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { 336 [TIMER_BASE_VALUE] = GENMASK(31, 0), 337 }; 338 339 IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 340 0x00000830, 0x0070); 341 342 static const u32 ipa_reg_endp_init_deaggr_fmask[] = { 343 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 344 [SYSPIPE_ERR_DETECTION] = BIT(6), 345 [PACKET_OFFSET_VALID] = BIT(7), 346 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 347 [IGNORE_MIN_PKT_ERR] = BIT(14), 348 /* Bit 15 reserved */ 349 [MAX_PACKET_LEN] = GENMASK(31, 16), 350 }; 351 352 IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 353 354 static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { 355 [ENDP_RSRC_GRP] = GENMASK(2, 0), 356 /* Bits 3-31 reserved */ 357 }; 358 359 IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 360 0x00000838, 0x0070); 361 362 static const u32 ipa_reg_endp_init_seq_fmask[] = { 363 [SEQ_TYPE] = GENMASK(7, 0), 364 [SEQ_REP_TYPE] = GENMASK(15, 8), 365 /* Bits 16-31 reserved */ 366 }; 367 368 IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 369 370 static const u32 ipa_reg_endp_status_fmask[] = { 371 [STATUS_EN] = BIT(0), 372 [STATUS_ENDP] = GENMASK(5, 1), 373 /* Bits 6-7 reserved */ 374 [STATUS_LOCATION] = BIT(8), 375 /* Bits 9-31 reserved */ 376 }; 377 378 IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 379 380 static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { 381 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 382 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 383 [FILTER_HASH_MSK_DST_IP] = BIT(2), 384 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 385 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 386 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 387 [FILTER_HASH_MSK_METADATA] = BIT(6), 388 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 389 /* Bits 7-15 reserved */ 390 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 391 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 392 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 393 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 394 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 395 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 396 [ROUTER_HASH_MSK_METADATA] = BIT(22), 397 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 398 /* Bits 23-31 reserved */ 399 }; 400 401 IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 402 0x0000085c, 0x0070); 403 404 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 405 IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 406 407 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 408 IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 409 410 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 411 IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 412 413 static const u32 ipa_reg_ipa_irq_uc_fmask[] = { 414 [UC_INTR] = BIT(0), 415 /* Bits 1-31 reserved */ 416 }; 417 418 IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 419 420 /* Valid bits defined by ipa->available */ 421 IPA_REG(IRQ_SUSPEND_INFO, irq_suspend_info, 0x00003030 + 0x1000 * GSI_EE_AP); 422 423 /* Valid bits defined by ipa->available */ 424 IPA_REG(IRQ_SUSPEND_EN, irq_suspend_en, 0x00003034 + 0x1000 * GSI_EE_AP); 425 426 /* Valid bits defined by ipa->available */ 427 IPA_REG(IRQ_SUSPEND_CLR, irq_suspend_clr, 0x00003038 + 0x1000 * GSI_EE_AP); 428 429 static const struct ipa_reg *ipa_reg_array[] = { 430 [COMP_CFG] = &ipa_reg_comp_cfg, 431 [CLKON_CFG] = &ipa_reg_clkon_cfg, 432 [ROUTE] = &ipa_reg_route, 433 [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, 434 [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, 435 [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, 436 [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, 437 [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, 438 [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, 439 [IPA_BCR] = &ipa_reg_ipa_bcr, 440 [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, 441 [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, 442 [COUNTER_CFG] = &ipa_reg_counter_cfg, 443 [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, 444 [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, 445 [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, 446 [SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type, 447 [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, 448 [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, 449 [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, 450 [DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type, 451 [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, 452 [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, 453 [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, 454 [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, 455 [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, 456 [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, 457 [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, 458 [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, 459 [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, 460 [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, 461 [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, 462 [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, 463 [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, 464 [ENDP_STATUS] = &ipa_reg_endp_status, 465 [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, 466 [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, 467 [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, 468 [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, 469 [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, 470 [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, 471 [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, 472 [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, 473 }; 474 475 const struct ipa_regs ipa_regs_v3_1 = { 476 .reg_count = ARRAY_SIZE(ipa_reg_array), 477 .reg = ipa_reg_array, 478 }; 479