xref: /openbmc/linux/drivers/net/ipa/reg/gsi_reg-v4.5.c (revision 59b12b1d) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023 Linaro Ltd. */
4 
5 #include <linux/types.h>
6 
7 #include "../gsi.h"
8 #include "../reg.h"
9 #include "../gsi_reg.h"
10 
11 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12     0x0000c020 + 0x1000 * GSI_EE_AP);
13 
14 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15     0x0000c024 + 0x1000 * GSI_EE_AP);
16 
17 static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
19 	[CHTYPE_DIR]					= BIT(3),
20 	[CH_EE]						= GENMASK(7, 4),
21 	[CHID]						= GENMASK(12, 8),
22 	[CHTYPE_PROTOCOL_MSB]				= BIT(13),
23 	[ERINDEX]					= GENMASK(18, 14),
24 						/* Bit 19 reserved */
25 	[CHSTATE]					= GENMASK(23, 20),
26 	[ELEMENT_SIZE]					= GENMASK(31, 24),
27 };
28 
29 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 		  0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
31 
32 static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 	[CH_R_LENGTH]					= GENMASK(15, 0),
34 						/* Bits 16-31 reserved */
35 };
36 
37 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 		  0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
39 
40 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
41 
42 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
43 
44 static const u32 reg_ch_c_qos_fmask[] = {
45 	[WRR_WEIGHT]					= GENMASK(3, 0),
46 						/* Bits 4-7 reserved */
47 	[MAX_PREFETCH]					= BIT(8),
48 	[USE_DB_ENG]					= BIT(9),
49 	[PREFETCH_MODE]					= GENMASK(13, 10),
50 						/* Bits 14-15 reserved */
51 	[EMPTY_LVL_THRSHOLD]				= GENMASK(23, 16),
52 						/* Bits 24-31 reserved */
53 };
54 
55 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
56 
57 static const u32 reg_error_log_fmask[] = {
58 	[ERR_ARG3]					= GENMASK(3, 0),
59 	[ERR_ARG2]					= GENMASK(7, 4),
60 	[ERR_ARG1]					= GENMASK(11, 8),
61 	[ERR_CODE]					= GENMASK(15, 12),
62 						/* Bits 16-18 reserved */
63 	[ERR_VIRT_IDX]					= GENMASK(23, 19),
64 	[ERR_TYPE]					= GENMASK(27, 24),
65 	[ERR_EE]					= GENMASK(31, 28),
66 };
67 
68 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
69 	   0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
70 
71 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
72 	   0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
73 
74 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
75 	   0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
76 
77 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
78 	   0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
79 
80 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
81 	[EV_CHTYPE]					= GENMASK(3, 0),
82 	[EV_EE]						= GENMASK(7, 4),
83 	[EV_EVCHID]					= GENMASK(15, 8),
84 	[EV_INTYPE]					= BIT(16),
85 						/* Bits 17-19 reserved */
86 	[EV_CHSTATE]					= GENMASK(23, 20),
87 	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
88 };
89 
90 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
91 		  0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
92 
93 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
94 	   0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
95 
96 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
97 	   0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
98 
99 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
100 	   0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
101 
102 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
103 	   0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
104 
105 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
106 	[EV_MODT]					= GENMASK(15, 0),
107 	[EV_MODC]					= GENMASK(23, 16),
108 	[EV_MOD_CNT]					= GENMASK(31, 24),
109 };
110 
111 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
112 		  0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
113 
114 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
115 	   0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
116 
117 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
118 	   0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
119 
120 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
121 	   0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
122 
123 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
124 	   0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
125 
126 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
127 	   0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
128 
129 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
130 	   0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
131 
132 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
133 	   0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
134 
135 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
136 	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
137 
138 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
139 	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
140 
141 static const u32 reg_gsi_status_fmask[] = {
142 	[ENABLED]					= BIT(0),
143 						/* Bits 1-31 reserved */
144 };
145 
146 REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
147 
148 static const u32 reg_ch_cmd_fmask[] = {
149 	[CH_CHID]					= GENMASK(7, 0),
150 						/* Bits 8-23 reserved */
151 	[CH_OPCODE]					= GENMASK(31, 24),
152 };
153 
154 REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
155 
156 static const u32 reg_ev_ch_cmd_fmask[] = {
157 	[EV_CHID]					= GENMASK(7, 0),
158 						/* Bits 8-23 reserved */
159 	[EV_OPCODE]					= GENMASK(31, 24),
160 };
161 
162 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
163 
164 static const u32 reg_generic_cmd_fmask[] = {
165 	[GENERIC_OPCODE]				= GENMASK(4, 0),
166 	[GENERIC_CHID]					= GENMASK(9, 5),
167 	[GENERIC_EE]					= GENMASK(13, 10),
168 						/* Bits 14-31 reserved */
169 };
170 
171 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
172 
173 static const u32 reg_hw_param_2_fmask[] = {
174 	[IRAM_SIZE]					= GENMASK(2, 0),
175 	[NUM_CH_PER_EE]					= GENMASK(7, 3),
176 	[NUM_EV_PER_EE]					= GENMASK(12, 8),
177 	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
178 	[GSI_CH_FULL_LOGIC]				= BIT(14),
179 	[GSI_USE_SDMA]					= BIT(15),
180 	[GSI_SDMA_N_INT]				= GENMASK(18, 16),
181 	[GSI_SDMA_MAX_BURST]				= GENMASK(26, 19),
182 	[GSI_SDMA_N_IOVEC]				= GENMASK(29, 27),
183 	[GSI_USE_RD_WR_ENG]				= BIT(30),
184 	[GSI_USE_INTER_EE]				= BIT(31),
185 };
186 
187 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
188 
189 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
190 
191 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
192 
193 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
194 
195 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
196 
197 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
198     0x0001f098 + 0x4000 * GSI_EE_AP);
199 
200 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
201     0x0001f09c + 0x4000 * GSI_EE_AP);
202 
203 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
204     0x0001f0a0 + 0x4000 * GSI_EE_AP);
205 
206 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
207     0x0001f0a4 + 0x4000 * GSI_EE_AP);
208 
209 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
210 
211 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
212     0x0001f0b8 + 0x4000 * GSI_EE_AP);
213 
214 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
215     0x0001f0c0 + 0x4000 * GSI_EE_AP);
216 
217 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
218 
219 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
220 
221 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
222 
223 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
224 
225 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
226 
227 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
228 
229 static const u32 reg_cntxt_intset_fmask[] = {
230 	[INTYPE]					= BIT(0)
231 						/* Bits 1-31 reserved */
232 };
233 
234 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
235 
236 REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
237 
238 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
239 
240 static const u32 reg_cntxt_scratch_0_fmask[] = {
241 	[INTER_EE_RESULT]				= GENMASK(2, 0),
242 						/* Bits 3-4 reserved */
243 	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
244 						/* Bits 8-31 reserved */
245 };
246 
247 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
248 
249 static const struct reg *reg_array[] = {
250 	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
251 	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
252 	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
253 	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
254 	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
255 	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
256 	[CH_C_QOS]			= &reg_ch_c_qos,
257 	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
258 	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
259 	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
260 	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
261 	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
262 	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
263 	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
264 	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
265 	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
266 	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
267 	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
268 	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
269 	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
270 	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
271 	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
272 	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
273 	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
274 	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
275 	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
276 	[GSI_STATUS]			= &reg_gsi_status,
277 	[CH_CMD]			= &reg_ch_cmd,
278 	[EV_CH_CMD]			= &reg_ev_ch_cmd,
279 	[GENERIC_CMD]			= &reg_generic_cmd,
280 	[HW_PARAM_2]			= &reg_hw_param_2,
281 	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
282 	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
283 	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
284 	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
285 	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
286 	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
287 	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
288 	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
289 	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
290 	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
291 	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
292 	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
293 	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
294 	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
295 	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
296 	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
297 	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
298 	[CNTXT_INTSET]			= &reg_cntxt_intset,
299 	[ERROR_LOG]			= &reg_error_log,
300 	[ERROR_LOG_CLR]			= &reg_error_log_clr,
301 	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
302 };
303 
304 const struct regs gsi_regs_v4_5 = {
305 	.reg_count	= ARRAY_SIZE(reg_array),
306 	.reg		= reg_array,
307 };
308