1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2023 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../gsi.h" 8 #include "../reg.h" 9 #include "../gsi_reg.h" 10 11 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ 12 13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 14 0x0000c020 + 0x1000 * GSI_EE_AP); 15 16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 17 0x0000c024 + 0x1000 * GSI_EE_AP); 18 19 /* All other register offsets are relative to gsi->virt */ 20 21 static const u32 reg_ch_c_cntxt_0_fmask[] = { 22 [CHTYPE_PROTOCOL] = GENMASK(2, 0), 23 [CHTYPE_DIR] = BIT(3), 24 [CH_EE] = GENMASK(7, 4), 25 [CHID] = GENMASK(12, 8), 26 [CHTYPE_PROTOCOL_MSB] = BIT(13), 27 [ERINDEX] = GENMASK(18, 14), 28 /* Bit 19 reserved */ 29 [CHSTATE] = GENMASK(23, 20), 30 [ELEMENT_SIZE] = GENMASK(31, 24), 31 }; 32 33 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, 34 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); 35 36 static const u32 reg_ch_c_cntxt_1_fmask[] = { 37 [CH_R_LENGTH] = GENMASK(15, 0), 38 /* Bits 16-31 reserved */ 39 }; 40 41 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, 42 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); 43 44 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); 45 46 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); 47 48 static const u32 reg_ch_c_qos_fmask[] = { 49 [WRR_WEIGHT] = GENMASK(3, 0), 50 /* Bits 4-7 reserved */ 51 [MAX_PREFETCH] = BIT(8), 52 [USE_DB_ENG] = BIT(9), 53 [PREFETCH_MODE] = GENMASK(13, 10), 54 /* Bits 14-15 reserved */ 55 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16), 56 /* Bits 24-31 reserved */ 57 }; 58 59 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); 60 61 static const u32 reg_error_log_fmask[] = { 62 [ERR_ARG3] = GENMASK(3, 0), 63 [ERR_ARG2] = GENMASK(7, 4), 64 [ERR_ARG1] = GENMASK(11, 8), 65 [ERR_CODE] = GENMASK(15, 12), 66 /* Bits 16-18 reserved */ 67 [ERR_VIRT_IDX] = GENMASK(23, 19), 68 [ERR_TYPE] = GENMASK(27, 24), 69 [ERR_EE] = GENMASK(31, 28), 70 }; 71 72 REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); 73 74 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); 75 76 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 77 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); 78 79 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, 80 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); 81 82 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, 83 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); 84 85 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, 86 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); 87 88 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { 89 [EV_CHTYPE] = GENMASK(3, 0), 90 [EV_EE] = GENMASK(7, 4), 91 [EV_EVCHID] = GENMASK(15, 8), 92 [EV_INTYPE] = BIT(16), 93 /* Bits 17-19 reserved */ 94 [EV_CHSTATE] = GENMASK(23, 20), 95 [EV_ELEMENT_SIZE] = GENMASK(31, 24), 96 }; 97 98 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 99 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); 100 101 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, 102 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); 103 104 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 105 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); 106 107 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, 108 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); 109 110 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, 111 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); 112 113 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { 114 [EV_MODT] = GENMASK(15, 0), 115 [EV_MODC] = GENMASK(23, 16), 116 [EV_MOD_CNT] = GENMASK(31, 24), 117 }; 118 119 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, 120 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); 121 122 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, 123 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); 124 125 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, 126 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); 127 128 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, 129 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); 130 131 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, 132 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); 133 134 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, 135 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); 136 137 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, 138 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); 139 140 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, 141 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); 142 143 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, 144 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); 145 146 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, 147 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); 148 149 static const u32 reg_gsi_status_fmask[] = { 150 [ENABLED] = BIT(0), 151 /* Bits 1-31 reserved */ 152 }; 153 154 REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); 155 156 static const u32 reg_ch_cmd_fmask[] = { 157 [CH_CHID] = GENMASK(7, 0), 158 [CH_OPCODE] = GENMASK(31, 24), 159 }; 160 161 REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); 162 163 static const u32 reg_ev_ch_cmd_fmask[] = { 164 [EV_CHID] = GENMASK(7, 0), 165 [EV_OPCODE] = GENMASK(31, 24), 166 }; 167 168 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); 169 170 static const u32 reg_generic_cmd_fmask[] = { 171 [GENERIC_OPCODE] = GENMASK(4, 0), 172 [GENERIC_CHID] = GENMASK(9, 5), 173 [GENERIC_EE] = GENMASK(13, 10), 174 /* Bits 14-31 reserved */ 175 }; 176 177 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); 178 179 static const u32 reg_hw_param_2_fmask[] = { 180 [IRAM_SIZE] = GENMASK(2, 0), 181 [NUM_CH_PER_EE] = GENMASK(7, 3), 182 [NUM_EV_PER_EE] = GENMASK(12, 8), 183 [GSI_CH_PEND_TRANSLATE] = BIT(13), 184 [GSI_CH_FULL_LOGIC] = BIT(14), 185 [GSI_USE_SDMA] = BIT(15), 186 [GSI_SDMA_N_INT] = GENMASK(18, 16), 187 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19), 188 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27), 189 [GSI_USE_RD_WR_ENG] = BIT(30), 190 [GSI_USE_INTER_EE] = BIT(31), 191 }; 192 193 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); 194 195 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); 196 197 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); 198 199 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); 200 201 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); 202 203 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, 204 0x0001f098 + 0x4000 * GSI_EE_AP); 205 206 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, 207 0x0001f09c + 0x4000 * GSI_EE_AP); 208 209 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, 210 0x0001f0a0 + 0x4000 * GSI_EE_AP); 211 212 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, 213 0x0001f0a4 + 0x4000 * GSI_EE_AP); 214 215 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); 216 217 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, 218 0x0001f0b8 + 0x4000 * GSI_EE_AP); 219 220 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, 221 0x0001f0c0 + 0x4000 * GSI_EE_AP); 222 223 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); 224 225 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); 226 227 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); 228 229 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); 230 231 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); 232 233 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); 234 235 static const u32 reg_cntxt_intset_fmask[] = { 236 [INTYPE] = BIT(0) 237 /* Bits 1-31 reserved */ 238 }; 239 240 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); 241 242 static const u32 reg_cntxt_scratch_0_fmask[] = { 243 [INTER_EE_RESULT] = GENMASK(2, 0), 244 /* Bits 3-4 reserved */ 245 [GENERIC_EE_RESULT] = GENMASK(7, 5), 246 /* Bits 8-31 reserved */ 247 }; 248 249 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); 250 251 static const struct reg *reg_array[] = { 252 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, 253 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, 254 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, 255 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, 256 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, 257 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, 258 [CH_C_QOS] = ®_ch_c_qos, 259 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, 260 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, 261 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, 262 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, 263 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, 264 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, 265 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, 266 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, 267 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, 268 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, 269 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, 270 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, 271 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, 272 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, 273 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, 274 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, 275 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, 276 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, 277 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, 278 [GSI_STATUS] = ®_gsi_status, 279 [CH_CMD] = ®_ch_cmd, 280 [EV_CH_CMD] = ®_ev_ch_cmd, 281 [GENERIC_CMD] = ®_generic_cmd, 282 [HW_PARAM_2] = ®_hw_param_2, 283 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, 284 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, 285 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, 286 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, 287 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, 288 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, 289 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, 290 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, 291 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, 292 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, 293 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, 294 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, 295 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, 296 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, 297 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, 298 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, 299 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, 300 [CNTXT_INTSET] = ®_cntxt_intset, 301 [ERROR_LOG] = ®_error_log, 302 [ERROR_LOG_CLR] = ®_error_log_clr, 303 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, 304 }; 305 306 const struct regs gsi_regs_v4_5 = { 307 .reg_count = ARRAY_SIZE(reg_array), 308 .reg = reg_array, 309 }; 310