1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/io.h> 9 #include <linux/delay.h> 10 11 #include "ipa.h" 12 #include "ipa_clock.h" 13 #include "ipa_uc.h" 14 15 /** 16 * DOC: The IPA embedded microcontroller 17 * 18 * The IPA incorporates a microcontroller that is able to do some additional 19 * handling/offloading of network activity. The current code makes 20 * essentially no use of the microcontroller, but it still requires some 21 * initialization. It needs to be notified in the event the AP crashes. 22 * 23 * The microcontroller can generate two interrupts to the AP. One interrupt 24 * is used to indicate that a response to a request from the AP is available. 25 * The other is used to notify the AP of the occurrence of an event. In 26 * addition, the AP can interrupt the microcontroller by writing a register. 27 * 28 * A 128 byte block of structured memory within the IPA SRAM is used together 29 * with these interrupts to implement the communication interface between the 30 * AP and the IPA microcontroller. Each side writes data to the shared area 31 * before interrupting its peer, which will read the written data in response 32 * to the interrupt. Some information found in the shared area is currently 33 * unused. All remaining space in the shared area is reserved, and must not 34 * be read or written by the AP. 35 */ 36 /* Supports hardware interface version 0x2000 */ 37 38 /* Delay to allow a the microcontroller to save state when crashing */ 39 #define IPA_SEND_DELAY 100 /* microseconds */ 40 41 /** 42 * struct ipa_uc_mem_area - AP/microcontroller shared memory area 43 * @command: command code (AP->microcontroller) 44 * @reserved0: reserved bytes; avoid reading or writing 45 * @command_param: low 32 bits of command parameter (AP->microcontroller) 46 * @command_param_hi: high 32 bits of command parameter (AP->microcontroller) 47 * 48 * @response: response code (microcontroller->AP) 49 * @reserved1: reserved bytes; avoid reading or writing 50 * @response_param: response parameter (microcontroller->AP) 51 * 52 * @event: event code (microcontroller->AP) 53 * @reserved2: reserved bytes; avoid reading or writing 54 * @event_param: event parameter (microcontroller->AP) 55 * 56 * @first_error_address: address of first error-source on SNOC 57 * @hw_state: state of hardware (including error type information) 58 * @warning_counter: counter of non-fatal hardware errors 59 * @reserved3: reserved bytes; avoid reading or writing 60 * @interface_version: hardware-reported interface version 61 * @reserved4: reserved bytes; avoid reading or writing 62 * 63 * A shared memory area at the base of IPA resident memory is used for 64 * communication with the microcontroller. The region is 128 bytes in 65 * size, but only the first 40 bytes (structured this way) are used. 66 */ 67 struct ipa_uc_mem_area { 68 u8 command; /* enum ipa_uc_command */ 69 u8 reserved0[3]; 70 __le32 command_param; 71 __le32 command_param_hi; 72 u8 response; /* enum ipa_uc_response */ 73 u8 reserved1[3]; 74 __le32 response_param; 75 u8 event; /* enum ipa_uc_event */ 76 u8 reserved2[3]; 77 78 __le32 event_param; 79 __le32 first_error_address; 80 u8 hw_state; 81 u8 warning_counter; 82 __le16 reserved3; 83 __le16 interface_version; 84 __le16 reserved4; 85 }; 86 87 /** enum ipa_uc_command - commands from the AP to the microcontroller */ 88 enum ipa_uc_command { 89 IPA_UC_COMMAND_NO_OP = 0x0, 90 IPA_UC_COMMAND_UPDATE_FLAGS = 0x1, 91 IPA_UC_COMMAND_DEBUG_RUN_TEST = 0x2, 92 IPA_UC_COMMAND_DEBUG_GET_INFO = 0x3, 93 IPA_UC_COMMAND_ERR_FATAL = 0x4, 94 IPA_UC_COMMAND_CLK_GATE = 0x5, 95 IPA_UC_COMMAND_CLK_UNGATE = 0x6, 96 IPA_UC_COMMAND_MEMCPY = 0x7, 97 IPA_UC_COMMAND_RESET_PIPE = 0x8, 98 IPA_UC_COMMAND_REG_WRITE = 0x9, 99 IPA_UC_COMMAND_GSI_CH_EMPTY = 0xa, 100 }; 101 102 /** enum ipa_uc_response - microcontroller response codes */ 103 enum ipa_uc_response { 104 IPA_UC_RESPONSE_NO_OP = 0x0, 105 IPA_UC_RESPONSE_INIT_COMPLETED = 0x1, 106 IPA_UC_RESPONSE_CMD_COMPLETED = 0x2, 107 IPA_UC_RESPONSE_DEBUG_GET_INFO = 0x3, 108 }; 109 110 /** enum ipa_uc_event - common cpu events reported by the microcontroller */ 111 enum ipa_uc_event { 112 IPA_UC_EVENT_NO_OP = 0x0, 113 IPA_UC_EVENT_ERROR = 0x1, 114 IPA_UC_EVENT_LOG_INFO = 0x2, 115 }; 116 117 static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa) 118 { 119 const struct ipa_mem *mem = ipa_mem_find(ipa, IPA_MEM_UC_SHARED); 120 u32 offset = ipa->mem_offset + mem->offset; 121 122 return ipa->mem_virt + offset; 123 } 124 125 /* Microcontroller event IPA interrupt handler */ 126 static void ipa_uc_event_handler(struct ipa *ipa, enum ipa_irq_id irq_id) 127 { 128 struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); 129 struct device *dev = &ipa->pdev->dev; 130 131 if (shared->event == IPA_UC_EVENT_ERROR) 132 dev_err(dev, "microcontroller error event\n"); 133 else if (shared->event != IPA_UC_EVENT_LOG_INFO) 134 dev_err(dev, "unsupported microcontroller event %u\n", 135 shared->event); 136 /* The LOG_INFO event can be safely ignored */ 137 } 138 139 /* Microcontroller response IPA interrupt handler */ 140 static void ipa_uc_response_hdlr(struct ipa *ipa, enum ipa_irq_id irq_id) 141 { 142 struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); 143 struct device *dev = &ipa->pdev->dev; 144 145 /* An INIT_COMPLETED response message is sent to the AP by the 146 * microcontroller when it is operational. Other than this, the AP 147 * should only receive responses from the microcontroller when it has 148 * sent it a request message. 149 * 150 * We can drop the clock reference taken in ipa_uc_clock() once we 151 * know the microcontroller has finished its initialization. 152 */ 153 switch (shared->response) { 154 case IPA_UC_RESPONSE_INIT_COMPLETED: 155 if (ipa->uc_clocked) { 156 ipa->uc_loaded = true; 157 ipa_clock_put(ipa); 158 ipa->uc_clocked = false; 159 } else { 160 dev_warn(dev, "unexpected init_completed response\n"); 161 } 162 break; 163 default: 164 dev_warn(dev, "unsupported microcontroller response %u\n", 165 shared->response); 166 break; 167 } 168 } 169 170 /* Configure the IPA microcontroller subsystem */ 171 void ipa_uc_config(struct ipa *ipa) 172 { 173 ipa->uc_clocked = false; 174 ipa->uc_loaded = false; 175 ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_0, ipa_uc_event_handler); 176 ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_1, ipa_uc_response_hdlr); 177 } 178 179 /* Inverse of ipa_uc_config() */ 180 void ipa_uc_deconfig(struct ipa *ipa) 181 { 182 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_1); 183 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_0); 184 if (ipa->uc_clocked) 185 ipa_clock_put(ipa); 186 } 187 188 /* Take a proxy clock reference for the microcontroller */ 189 void ipa_uc_clock(struct ipa *ipa) 190 { 191 static bool already; 192 193 if (already) 194 return; 195 already = true; /* Only do this on first boot */ 196 197 /* This clock reference dropped in ipa_uc_response_hdlr() above */ 198 ipa_clock_get(ipa); 199 ipa->uc_clocked = true; 200 } 201 202 /* Send a command to the microcontroller */ 203 static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param) 204 { 205 struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa); 206 u32 offset; 207 u32 val; 208 209 /* Fill in the command data */ 210 shared->command = command; 211 shared->command_param = cpu_to_le32(command_param); 212 shared->command_param_hi = 0; 213 shared->response = 0; 214 shared->response_param = 0; 215 216 /* Use an interrupt to tell the microcontroller the command is ready */ 217 val = u32_encode_bits(1, UC_INTR_FMASK); 218 offset = ipa_reg_irq_uc_offset(ipa->version); 219 iowrite32(val, ipa->reg_virt + offset); 220 } 221 222 /* Tell the microcontroller the AP is shutting down */ 223 void ipa_uc_panic_notifier(struct ipa *ipa) 224 { 225 if (!ipa->uc_loaded) 226 return; 227 228 send_uc_command(ipa, IPA_UC_COMMAND_ERR_FATAL, 0); 229 230 /* give uc enough time to save state */ 231 udelay(IPA_SEND_DELAY); 232 } 233