1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 69 70 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 71 #define ENABLE_FMASK GENMASK(0, 0) 72 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 73 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 74 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 75 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 76 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 77 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 78 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 79 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 80 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 81 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 82 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 83 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 84 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 85 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 86 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 87 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 88 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 89 90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 91 #define RX_FMASK GENMASK(0, 0) 92 #define PROC_FMASK GENMASK(1, 1) 93 #define TX_WRAPPER_FMASK GENMASK(2, 2) 94 #define MISC_FMASK GENMASK(3, 3) 95 #define RAM_ARB_FMASK GENMASK(4, 4) 96 #define FTCH_HPS_FMASK GENMASK(5, 5) 97 #define FTCH_DPS_FMASK GENMASK(6, 6) 98 #define HPS_FMASK GENMASK(7, 7) 99 #define DPS_FMASK GENMASK(8, 8) 100 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 101 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 102 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 103 #define RSRC_MNGR_FMASK GENMASK(12, 12) 104 #define CTX_HANDLER_FMASK GENMASK(13, 13) 105 #define ACK_MNGR_FMASK GENMASK(14, 14) 106 #define D_DCPH_FMASK GENMASK(15, 15) 107 #define H_DCPH_FMASK GENMASK(16, 16) 108 #define DCMP_FMASK GENMASK(17, 17) 109 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 110 #define TX_0_FMASK GENMASK(19, 19) 111 #define TX_1_FMASK GENMASK(20, 20) 112 #define FNR_FMASK GENMASK(21, 21) 113 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 114 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 115 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 116 #define QMB_FMASK GENMASK(25, 25) 117 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 118 #define GSI_IF_FMASK GENMASK(27, 27) 119 #define GLOBAL_FMASK GENMASK(28, 28) 120 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 121 122 #define IPA_REG_ROUTE_OFFSET 0x00000048 123 #define ROUTE_DIS_FMASK GENMASK(0, 0) 124 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 125 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 126 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 127 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 128 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 129 130 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 131 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 132 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 133 134 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 135 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 136 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 137 138 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 139 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 140 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 141 /* The next two fields are present for IPA v4.0 and above */ 142 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 143 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 144 145 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 146 { 147 if (version == IPA_VERSION_3_5_1) 148 return 0x0000010c; 149 150 return 0x000000b4; 151 } 152 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 153 154 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 155 { 156 if (version == IPA_VERSION_3_5_1) 157 return 0x000008c; 158 159 return 0x0000148; 160 } 161 162 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 163 { 164 if (version == IPA_VERSION_3_5_1) 165 return 0x0000090; 166 167 return 0x000014c; 168 } 169 170 /* The next four fields are used for the hash enable and flush registers */ 171 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 172 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 173 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 174 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 175 176 #define IPA_REG_BCR_OFFSET 0x000001d0 177 /* The next two fields are not present for IPA v4.2 */ 178 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 179 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 180 /* The next field is invalid for IPA v4.1 */ 181 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 182 /* The next two fields are not present for IPA v4.2 */ 183 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 184 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 185 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 186 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 187 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 188 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 189 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 190 191 /* Backward compatibility register value to use for each version */ 192 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 193 { 194 if (version == IPA_VERSION_3_5_1) 195 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 196 BCR_TX_NOT_USING_BRESP_FMASK | 197 BCR_SUSPEND_L2_IRQ_FMASK | 198 BCR_HOLB_DROP_L2_IRQ_FMASK | 199 BCR_DUAL_TX_FMASK; 200 201 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 202 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 203 BCR_SUSPEND_L2_IRQ_FMASK | 204 BCR_HOLB_DROP_L2_IRQ_FMASK | 205 BCR_DUAL_TX_FMASK; 206 207 return 0x00000000; 208 } 209 210 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 211 212 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 213 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 214 215 /* The internal inactivity timer clock is used for the aggregation timer */ 216 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 217 218 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 219 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 220 /* Compute the value to use in the AGGR_GRANULARITY field representing the 221 * given number of microseconds. The value is one less than the number of 222 * timer ticks in the requested period. Zero not a valid granularity value. 223 */ 224 static inline u32 ipa_aggr_granularity_val(u32 usec) 225 { 226 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 227 } 228 229 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 230 /* The first three fields are present for IPA v3.5.1 only */ 231 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 232 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 233 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 234 /* The next fields are present for IPA v4.0 and above */ 235 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 236 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 237 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 238 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 239 #define PA_MASK_EN_FMASK GENMASK(12, 12) 240 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 241 /* The last two fields are present for IPA v4.2 and above */ 242 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 243 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 244 245 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 246 #define BAM_MAX_PIPES_FMASK GENMASK(4, 0) 247 #define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 248 #define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 249 #define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) 250 251 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 252 { 253 if (version == IPA_VERSION_4_2) 254 return 0x00000240; 255 256 return 0x00000220; 257 } 258 259 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 260 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 261 262 /* # IPA source resource groups available based on version */ 263 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 264 { 265 switch (version) { 266 case IPA_VERSION_3_5_1: 267 case IPA_VERSION_4_0: 268 case IPA_VERSION_4_1: 269 return 4; 270 271 case IPA_VERSION_4_2: 272 return 1; 273 274 default: 275 return 0; 276 } 277 } 278 279 /* # IPA destination resource groups available based on version */ 280 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 281 { 282 switch (version) { 283 case IPA_VERSION_3_5_1: 284 return 3; 285 286 case IPA_VERSION_4_0: 287 case IPA_VERSION_4_1: 288 return 4; 289 290 case IPA_VERSION_4_2: 291 return 1; 292 293 default: 294 return 0; 295 } 296 } 297 298 /* Not all of the following are valid (depends on the count, above) */ 299 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 300 (0x00000400 + 0x0020 * (rt)) 301 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 302 (0x00000404 + 0x0020 * (rt)) 303 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 304 (0x00000408 + 0x0020 * (rt)) 305 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 306 (0x00000500 + 0x0020 * (rt)) 307 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 308 (0x00000504 + 0x0020 * (rt)) 309 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 310 (0x00000508 + 0x0020 * (rt)) 311 #define X_MIN_LIM_FMASK GENMASK(5, 0) 312 #define X_MAX_LIM_FMASK GENMASK(13, 8) 313 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 314 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 315 316 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 317 (0x00000800 + 0x0070 * (ep)) 318 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 319 #define ENDP_DELAY_FMASK GENMASK(1, 1) 320 321 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 322 (0x00000808 + 0x0070 * (ep)) 323 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 324 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 325 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 326 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 327 328 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 329 (0x00000810 + 0x0070 * (ep)) 330 #define HDR_LEN_FMASK GENMASK(5, 0) 331 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 332 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 333 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 334 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 335 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 336 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 337 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 338 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 339 340 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 341 (0x00000814 + 0x0070 * (ep)) 342 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 343 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 344 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 345 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 346 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 347 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 348 349 /* Valid only for RX (IPA producer) endpoints */ 350 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 351 (0x00000818 + 0x0070 * (rxep)) 352 353 /* Valid only for TX (IPA consumer) endpoints */ 354 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 355 (0x00000820 + 0x0070 * (txep)) 356 #define MODE_FMASK GENMASK(2, 0) 357 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 358 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 359 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 360 #define PAD_EN_FMASK GENMASK(29, 29) 361 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 362 363 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 364 (0x00000824 + 0x0070 * (ep)) 365 #define AGGR_EN_FMASK GENMASK(1, 0) 366 #define AGGR_TYPE_FMASK GENMASK(4, 2) 367 #define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) 368 #define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) 369 #define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) 370 #define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) 371 #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) 372 #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) 373 374 /* Valid only for RX (IPA producer) endpoints */ 375 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 376 (0x0000082c + 0x0070 * (rxep)) 377 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 378 379 /* Valid only for RX (IPA producer) endpoints */ 380 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 381 (0x00000830 + 0x0070 * (rxep)) 382 /* The next fields are present for IPA v4.2 only */ 383 #define BASE_VALUE_FMASK GENMASK(4, 0) 384 #define SCALE_FMASK GENMASK(12, 8) 385 386 /* Valid only for TX (IPA consumer) endpoints */ 387 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 388 (0x00000834 + 0x0070 * (txep)) 389 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 390 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 391 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 392 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 393 394 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 395 (0x00000838 + 0x0070 * (ep)) 396 /* Encoded value for RSRC_GRP endpoint register RSRC_GRP field */ 397 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 398 { 399 switch (version) { 400 case IPA_VERSION_4_2: 401 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 402 default: 403 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 404 } 405 } 406 407 /* Valid only for TX (IPA consumer) endpoints */ 408 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 409 (0x0000083c + 0x0070 * (txep)) 410 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) 411 #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) 412 #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) 413 #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) 414 415 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 416 (0x00000840 + 0x0070 * (ep)) 417 #define STATUS_EN_FMASK GENMASK(0, 0) 418 #define STATUS_ENDP_FMASK GENMASK(5, 1) 419 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 420 /* The next field is present for IPA v4.0 and above */ 421 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 422 423 /* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ 424 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 425 (0x0000085c + 0x0070 * (er)) 426 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 427 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 428 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 429 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 430 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 431 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 432 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 433 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 434 435 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 436 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 437 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 438 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 439 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 440 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 441 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 442 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 443 444 #define IPA_REG_IRQ_STTS_OFFSET \ 445 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 446 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 447 (0x00003008 + 0x1000 * (ee)) 448 449 #define IPA_REG_IRQ_EN_OFFSET \ 450 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 451 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 452 (0x0000300c + 0x1000 * (ee)) 453 454 #define IPA_REG_IRQ_CLR_OFFSET \ 455 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 456 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 457 (0x00003010 + 0x1000 * (ee)) 458 459 #define IPA_REG_IRQ_UC_OFFSET \ 460 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 461 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 462 (0x0000301c + 0x1000 * (ee)) 463 464 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 465 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 466 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 467 (0x00003030 + 0x1000 * (ee)) 468 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 469 470 #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ 471 IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) 472 #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ 473 (0x00003034 + 0x1000 * (ee)) 474 /* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ 475 476 #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ 477 IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) 478 #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ 479 (0x00003038 + 0x1000 * (ee)) 480 /* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ 481 482 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 483 enum ipa_cs_offload_en { 484 IPA_CS_OFFLOAD_NONE = 0, 485 IPA_CS_OFFLOAD_UL = 1, 486 IPA_CS_OFFLOAD_DL = 2, 487 IPA_CS_RSVD 488 }; 489 490 /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ 491 enum ipa_aggr_en { 492 IPA_BYPASS_AGGR = 0, 493 IPA_ENABLE_AGGR = 1, 494 IPA_ENABLE_DEAGGR = 2, 495 }; 496 497 /** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ 498 enum ipa_aggr_type { 499 IPA_MBIM_16 = 0, 500 IPA_HDLC = 1, 501 IPA_TLP = 2, 502 IPA_RNDIS = 3, 503 IPA_GENERIC = 4, 504 IPA_COALESCE = 5, 505 IPA_QCMAP = 6, 506 }; 507 508 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 509 enum ipa_mode { 510 IPA_BASIC = 0, 511 IPA_ENABLE_FRAMING_HDLC = 1, 512 IPA_ENABLE_DEFRAMING_HDLC = 2, 513 IPA_DMA = 3, 514 }; 515 516 /** 517 * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N 518 * @IPA_SEQ_DMA_ONLY: only DMA is performed 519 * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: 520 * packet processing + no decipher + microcontroller (Ethernet Bridging) 521 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: 522 * second packet processing pass + no decipher + microcontroller 523 * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher 524 * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression 525 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: 526 * packet processing + no decipher + no uCP + HPS REP DMA parser 527 * @IPA_SEQ_INVALID: invalid sequencer type 528 * 529 * The values defined here are broken into 4-bit nibbles that are written 530 * into fields of the INIT_SEQ_N endpoint registers. 531 */ 532 enum ipa_seq_type { 533 IPA_SEQ_DMA_ONLY = 0x0000, 534 IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, 535 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, 536 IPA_SEQ_DMA_DEC = 0x0011, 537 IPA_SEQ_DMA_COMP_DECOMP = 0x0020, 538 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, 539 IPA_SEQ_INVALID = 0xffff, 540 }; 541 542 int ipa_reg_init(struct ipa *ipa); 543 void ipa_reg_exit(struct ipa *ipa); 544 545 #endif /* _IPA_REG_H_ */ 546