1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 /* The next field is not supported for IPA v4.1 */ 70 #define ENABLE_FMASK GENMASK(0, 0) 71 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 72 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 73 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 74 /* The next field is not present for IPA v4.5 */ 75 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 76 /* The remaining fields are not present for IPA v3.5.1 */ 77 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 78 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 79 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 80 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 81 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 82 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 83 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 84 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 85 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 86 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 87 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 88 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 89 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 90 /* The next field is present for IPA v4.5 */ 91 #define IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN_FMASK GENMASK(21, 21) 92 93 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 94 #define RX_FMASK GENMASK(0, 0) 95 #define PROC_FMASK GENMASK(1, 1) 96 #define TX_WRAPPER_FMASK GENMASK(2, 2) 97 #define MISC_FMASK GENMASK(3, 3) 98 #define RAM_ARB_FMASK GENMASK(4, 4) 99 #define FTCH_HPS_FMASK GENMASK(5, 5) 100 #define FTCH_DPS_FMASK GENMASK(6, 6) 101 #define HPS_FMASK GENMASK(7, 7) 102 #define DPS_FMASK GENMASK(8, 8) 103 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 104 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 105 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 106 #define RSRC_MNGR_FMASK GENMASK(12, 12) 107 #define CTX_HANDLER_FMASK GENMASK(13, 13) 108 #define ACK_MNGR_FMASK GENMASK(14, 14) 109 #define D_DCPH_FMASK GENMASK(15, 15) 110 #define H_DCPH_FMASK GENMASK(16, 16) 111 /* The next field is not present for IPA v4.5 */ 112 #define DCMP_FMASK GENMASK(17, 17) 113 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 114 #define TX_0_FMASK GENMASK(19, 19) 115 #define TX_1_FMASK GENMASK(20, 20) 116 #define FNR_FMASK GENMASK(21, 21) 117 /* The remaining fields are not present for IPA v3.5.1 */ 118 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 119 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 120 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 121 #define QMB_FMASK GENMASK(25, 25) 122 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 123 #define GSI_IF_FMASK GENMASK(27, 27) 124 #define GLOBAL_FMASK GENMASK(28, 28) 125 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 126 /* The next field is present for IPA v4.5 */ 127 #define DPL_FIFO_FMASK GENMASK(30, 30) 128 129 #define IPA_REG_ROUTE_OFFSET 0x00000048 130 #define ROUTE_DIS_FMASK GENMASK(0, 0) 131 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 132 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 133 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 134 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 135 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 136 137 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 138 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 139 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 140 141 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 142 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 143 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 144 145 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 146 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 147 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 148 /* The next two fields are not present for IPA v3.5.1 */ 149 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 150 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 151 152 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 153 { 154 if (version == IPA_VERSION_3_5_1) 155 return 0x000008c; 156 157 return 0x0000148; 158 } 159 160 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 161 { 162 if (version == IPA_VERSION_3_5_1) 163 return 0x0000090; 164 165 return 0x000014c; 166 } 167 168 /* The next four fields are used for the hash enable and flush registers */ 169 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 170 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 171 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 172 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 173 174 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 175 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 176 { 177 if (version == IPA_VERSION_3_5_1) 178 return 0x0000010c; 179 180 return 0x000000b4; 181 } 182 183 /* The next register is not present for IPA v4.5 */ 184 #define IPA_REG_BCR_OFFSET 0x000001d0 185 /* The next two fields are not present for IPA v4.2 */ 186 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 187 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 188 /* The next field is invalid for IPA v4.1 */ 189 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 190 /* The next two fields are not present for IPA v4.2 */ 191 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 192 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 193 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 194 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 195 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 196 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 197 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 198 199 /* Backward compatibility register value to use for each version */ 200 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 201 { 202 if (version == IPA_VERSION_3_5_1) 203 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 204 BCR_TX_NOT_USING_BRESP_FMASK | 205 BCR_SUSPEND_L2_IRQ_FMASK | 206 BCR_HOLB_DROP_L2_IRQ_FMASK | 207 BCR_DUAL_TX_FMASK; 208 209 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 210 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 211 BCR_SUSPEND_L2_IRQ_FMASK | 212 BCR_HOLB_DROP_L2_IRQ_FMASK | 213 BCR_DUAL_TX_FMASK; 214 215 /* assert(version != IPA_VERSION_4_5); */ 216 217 return 0x00000000; 218 } 219 220 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 221 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 222 223 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 224 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 225 u32 addr) 226 { 227 if (version < IPA_VERSION_4_5) 228 return u32_encode_bits(addr, GENMASK(16, 0)); 229 230 return u32_encode_bits(addr, GENMASK(17, 0)); 231 } 232 233 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 234 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 235 236 /* The next register is not present for IPA v4.5 */ 237 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 238 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 239 240 /* The internal inactivity timer clock is used for the aggregation timer */ 241 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 242 243 /* Compute the value to use in the AGGR_GRANULARITY field representing the 244 * given number of microseconds. The value is one less than the number of 245 * timer ticks in the requested period. 0 not a valid granularity value. 246 */ 247 static inline u32 ipa_aggr_granularity_val(u32 usec) 248 { 249 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 250 } 251 252 /* The next register is not present for IPA v4.5 */ 253 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 254 /* The first three fields are present for IPA v3.5.1 only */ 255 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 256 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 257 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 258 /* The next six fields are present for IPA v4.0 and above */ 259 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 260 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 261 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 262 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 263 #define PA_MASK_EN_FMASK GENMASK(12, 12) 264 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 265 /* The next field is present for IPA v4.5 */ 266 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 267 /* The next two fields are present for IPA v4.2 only */ 268 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 269 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 270 271 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 272 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 273 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 274 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 275 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 276 277 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 278 { 279 if (version >= IPA_VERSION_4_2) 280 return 0x00000240; 281 282 return 0x00000220; 283 } 284 285 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 286 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 287 288 /* The next register is present for IPA v4.5 */ 289 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 290 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 291 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 292 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 293 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 294 295 /* The next register is present for IPA v4.5 */ 296 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 297 #define DIV_VALUE_FMASK GENMASK(8, 0) 298 #define DIV_ENABLE_FMASK GENMASK(31, 31) 299 300 /* The next register is present for IPA v4.5 */ 301 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 302 #define GRAN_0_FMASK GENMASK(2, 0) 303 #define GRAN_1_FMASK GENMASK(5, 3) 304 #define GRAN_2_FMASK GENMASK(8, 6) 305 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 306 enum ipa_pulse_gran { 307 IPA_GRAN_10_US = 0x0, 308 IPA_GRAN_20_US = 0x1, 309 IPA_GRAN_50_US = 0x2, 310 IPA_GRAN_100_US = 0x3, 311 IPA_GRAN_1_MS = 0x4, 312 IPA_GRAN_10_MS = 0x5, 313 IPA_GRAN_100_MS = 0x6, 314 IPA_GRAN_655350_US = 0x7, 315 }; 316 317 /* # IPA source resource groups available based on version */ 318 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 319 { 320 switch (version) { 321 case IPA_VERSION_3_5_1: 322 case IPA_VERSION_4_0: 323 case IPA_VERSION_4_1: 324 return 4; 325 326 case IPA_VERSION_4_2: 327 return 1; 328 329 case IPA_VERSION_4_5: 330 return 5; 331 332 default: 333 return 0; 334 } 335 } 336 337 /* # IPA destination resource groups available based on version */ 338 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 339 { 340 switch (version) { 341 case IPA_VERSION_3_5_1: 342 return 3; 343 344 case IPA_VERSION_4_0: 345 case IPA_VERSION_4_1: 346 return 4; 347 348 case IPA_VERSION_4_2: 349 return 1; 350 351 case IPA_VERSION_4_5: 352 return 5; 353 354 default: 355 return 0; 356 } 357 } 358 359 /* Not all of the following are valid (depends on the count, above) */ 360 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 361 (0x00000400 + 0x0020 * (rt)) 362 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 363 (0x00000404 + 0x0020 * (rt)) 364 /* The next register is only present for IPA v4.5 */ 365 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 366 (0x00000408 + 0x0020 * (rt)) 367 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 368 (0x00000500 + 0x0020 * (rt)) 369 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 370 (0x00000504 + 0x0020 * (rt)) 371 /* The next register is only present for IPA v4.5 */ 372 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 373 (0x00000508 + 0x0020 * (rt)) 374 /* The next four fields are used for all resource group registers */ 375 #define X_MIN_LIM_FMASK GENMASK(5, 0) 376 #define X_MAX_LIM_FMASK GENMASK(13, 8) 377 /* The next two fields are not always present (if resource count is odd) */ 378 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 379 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 380 381 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 382 (0x00000800 + 0x0070 * (ep)) 383 /* The next field should only used for IPA v3.5.1 */ 384 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 385 #define ENDP_DELAY_FMASK GENMASK(1, 1) 386 387 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 388 (0x00000808 + 0x0070 * (ep)) 389 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 390 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 391 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 392 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 393 394 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 395 enum ipa_cs_offload_en { 396 IPA_CS_OFFLOAD_NONE = 0x0, 397 IPA_CS_OFFLOAD_UL = 0x1, 398 IPA_CS_OFFLOAD_DL = 0x2, 399 }; 400 401 /* Valid only for TX (IPA consumer) endpoints */ 402 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 403 (0x0000080c + 0x0070 * (ep)) 404 #define NAT_EN_FMASK GENMASK(1, 0) 405 406 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 407 enum ipa_nat_en { 408 IPA_NAT_BYPASS = 0x0, 409 IPA_NAT_SRC = 0x1, 410 IPA_NAT_DST = 0x2, 411 }; 412 413 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 414 (0x00000810 + 0x0070 * (ep)) 415 #define HDR_LEN_FMASK GENMASK(5, 0) 416 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 417 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 418 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 419 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 420 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 421 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 422 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 423 /* The next field is not present for IPA v4.5 */ 424 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 425 /* The next two fields are present for IPA v4.5 */ 426 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 427 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 428 429 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 430 static inline u32 ipa_header_size_encoded(enum ipa_version version, 431 u32 header_size) 432 { 433 u32 size = header_size & field_mask(HDR_LEN_FMASK); 434 u32 val; 435 436 val = u32_encode_bits(size, HDR_LEN_FMASK); 437 if (version < IPA_VERSION_4_5) { 438 /* ipa_assert(header_size == size); */ 439 return val; 440 } 441 442 /* IPA v4.5 adds a few more most-significant bits */ 443 size = header_size >> hweight32(HDR_LEN_FMASK); 444 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 445 446 return val; 447 } 448 449 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 450 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 451 u32 offset) 452 { 453 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 454 u32 val; 455 456 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 457 if (version < IPA_VERSION_4_5) { 458 /* ipa_assert(offset == off); */ 459 return val; 460 } 461 462 /* IPA v4.5 adds a few more most-significant bits */ 463 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 464 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 465 466 return val; 467 } 468 469 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 470 (0x00000814 + 0x0070 * (ep)) 471 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 472 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 473 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 474 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 475 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 476 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 477 /* The next three fields are present for IPA v4.5 */ 478 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 479 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 480 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 481 482 /* Valid only for RX (IPA producer) endpoints */ 483 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 484 (0x00000818 + 0x0070 * (rxep)) 485 486 /* Valid only for TX (IPA consumer) endpoints */ 487 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 488 (0x00000820 + 0x0070 * (txep)) 489 #define MODE_FMASK GENMASK(2, 0) 490 /* The next field is present for IPA v4.5 */ 491 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 492 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 493 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 494 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 495 #define PAD_EN_FMASK GENMASK(29, 29) 496 /* The next register is not present for IPA v4.5 */ 497 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 498 499 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 500 enum ipa_mode { 501 IPA_BASIC = 0x0, 502 IPA_ENABLE_FRAMING_HDLC = 0x1, 503 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 504 IPA_DMA = 0x3, 505 }; 506 507 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 508 (0x00000824 + 0x0070 * (ep)) 509 #define AGGR_EN_FMASK GENMASK(1, 0) 510 #define AGGR_TYPE_FMASK GENMASK(4, 2) 511 static inline u32 aggr_byte_limit_fmask(bool legacy) 512 { 513 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 514 } 515 516 static inline u32 aggr_time_limit_fmask(bool legacy) 517 { 518 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 519 } 520 521 static inline u32 aggr_pkt_limit_fmask(bool legacy) 522 { 523 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 524 } 525 526 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 527 { 528 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 529 } 530 531 static inline u32 aggr_force_close_fmask(bool legacy) 532 { 533 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 534 } 535 536 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 537 { 538 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 539 } 540 541 /* The next field is present for IPA v4.5 */ 542 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 543 544 /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ 545 enum ipa_aggr_en { 546 IPA_BYPASS_AGGR = 0x0, 547 IPA_ENABLE_AGGR = 0x1, 548 IPA_ENABLE_DEAGGR = 0x2, 549 }; 550 551 /** enum ipa_aggr_type - aggregation type field in ENDP_INIT_AGGR_N */ 552 enum ipa_aggr_type { 553 IPA_MBIM_16 = 0x0, 554 IPA_HDLC = 0x1, 555 IPA_TLP = 0x2, 556 IPA_RNDIS = 0x3, 557 IPA_GENERIC = 0x4, 558 IPA_COALESCE = 0x5, 559 IPA_QCMAP = 0x6, 560 }; 561 562 /* Valid only for RX (IPA producer) endpoints */ 563 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 564 (0x0000082c + 0x0070 * (rxep)) 565 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 566 567 /* Valid only for RX (IPA producer) endpoints */ 568 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 569 (0x00000830 + 0x0070 * (rxep)) 570 /* The next two fields are present for IPA v4.2 only */ 571 #define BASE_VALUE_FMASK GENMASK(4, 0) 572 #define SCALE_FMASK GENMASK(12, 8) 573 /* The next two fields are present for IPA v4.5 */ 574 #define TIME_LIMIT_FMASK GENMASK(4, 0) 575 #define GRAN_SEL_FMASK GENMASK(8, 8) 576 577 /* Valid only for TX (IPA consumer) endpoints */ 578 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 579 (0x00000834 + 0x0070 * (txep)) 580 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 581 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 582 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 583 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 584 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 585 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 586 587 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 588 (0x00000838 + 0x0070 * (ep)) 589 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 590 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 591 { 592 switch (version) { 593 case IPA_VERSION_4_2: 594 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 595 case IPA_VERSION_4_5: 596 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 597 default: 598 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 599 } 600 } 601 602 /* Valid only for TX (IPA consumer) endpoints */ 603 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 604 (0x0000083c + 0x0070 * (txep)) 605 #define SEQ_TYPE_FMASK GENMASK(7, 0) 606 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 607 608 /** 609 * enum ipa_seq_type - HPS and DPS sequencer type 610 * 611 * The low-order byte of the sequencer type register defines the number of 612 * passes a packet takes through the IPA pipeline. The last pass through can 613 * optionally skip the microprocessor. Deciphering is optional for all types; 614 * if enabled, an additional mask (two bits) is added to the type value. 615 * 616 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 617 * supported (or meaningful). 618 */ 619 #define IPA_SEQ_DECIPHER 0x11 620 enum ipa_seq_type { 621 IPA_SEQ_DMA = 0x00, 622 IPA_SEQ_1_PASS = 0x02, 623 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 624 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 625 IPA_SEQ_2_PASS = 0x0a, 626 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 627 }; 628 629 /** 630 * enum ipa_seq_rep_type - replicated packet sequencer type 631 * 632 * This goes in the second byte of the endpoint sequencer type register. 633 * 634 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 635 * supported (or meaningful). 636 */ 637 enum ipa_seq_rep_type { 638 IPA_SEQ_REP_DMA_PARSER = 0x08, 639 }; 640 641 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 642 (0x00000840 + 0x0070 * (ep)) 643 #define STATUS_EN_FMASK GENMASK(0, 0) 644 #define STATUS_ENDP_FMASK GENMASK(5, 1) 645 /* The next field is not present for IPA v4.5 */ 646 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 647 /* The next field is not present for IPA v3.5.1 */ 648 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 649 650 /* The next register is only present for IPA versions that support hashing */ 651 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 652 (0x0000085c + 0x0070 * (er)) 653 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 654 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 655 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 656 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 657 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 658 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 659 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 660 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 661 662 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 663 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 664 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 665 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 666 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 667 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 668 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 669 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 670 671 #define IPA_REG_IRQ_STTS_OFFSET \ 672 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 673 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 674 (0x00003008 + 0x1000 * (ee)) 675 676 #define IPA_REG_IRQ_EN_OFFSET \ 677 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 678 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 679 (0x0000300c + 0x1000 * (ee)) 680 681 #define IPA_REG_IRQ_CLR_OFFSET \ 682 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 683 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 684 (0x00003010 + 0x1000 * (ee)) 685 /** 686 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 687 * @IPA_IRQ_UC_0: Microcontroller event interrupt 688 * @IPA_IRQ_UC_1: Microcontroller response interrupt 689 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 690 * 691 * IRQ types not described above are not currently used. 692 */ 693 enum ipa_irq_id { 694 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 695 /* Type (bit) 0x1 is not defined */ 696 IPA_IRQ_UC_0 = 0x2, 697 IPA_IRQ_UC_1 = 0x3, 698 IPA_IRQ_UC_2 = 0x4, 699 IPA_IRQ_UC_3 = 0x5, 700 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 701 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 702 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 703 IPA_IRQ_RX_ERR = 0x9, 704 IPA_IRQ_DEAGGR_ERR = 0xa, 705 IPA_IRQ_TX_ERR = 0xb, 706 IPA_IRQ_STEP_MODE = 0xc, 707 IPA_IRQ_PROC_ERR = 0xd, 708 IPA_IRQ_TX_SUSPEND = 0xe, 709 IPA_IRQ_TX_HOLB_DROP = 0xf, 710 IPA_IRQ_BAM_GSI_IDLE = 0x10, 711 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 712 IPA_IRQ_PIPE_RED_BELOW = 0x12, 713 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 714 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 715 IPA_IRQ_UCP = 0x15, 716 IPA_IRQ_DCMP = 0x16, 717 IPA_IRQ_GSI_EE = 0x17, 718 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 719 IPA_IRQ_GSI_UC = 0x19, 720 /* The next bit is present for IPA v4.5 */ 721 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 722 IPA_IRQ_COUNT, /* Last; not an id */ 723 }; 724 725 #define IPA_REG_IRQ_UC_OFFSET \ 726 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 727 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 728 (0x0000301c + 0x1000 * (ee)) 729 #define UC_INTR_FMASK GENMASK(0, 0) 730 731 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 732 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 733 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 734 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 735 (0x00003030 + 0x1000 * (ee)) 736 737 /* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ 738 #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ 739 IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) 740 #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ 741 (0x00003034 + 0x1000 * (ee)) 742 743 /* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ 744 #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ 745 IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) 746 #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ 747 (0x00003038 + 0x1000 * (ee)) 748 749 int ipa_reg_init(struct ipa *ipa); 750 void ipa_reg_exit(struct ipa *ipa); 751 752 #endif /* _IPA_REG_H_ */ 753