1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 70 #define ENABLE_FMASK GENMASK(0, 0) 71 /* The next field is present for IPA v4.7+ */ 72 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 73 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 74 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 75 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 76 /* The next field is not present for IPA v4.5+ */ 77 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 78 /* The next twelve fields are present for IPA v4.0+ */ 79 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 80 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 81 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 82 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 83 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 84 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 85 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 86 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 87 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 88 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 89 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 90 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 91 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 92 /* The next field is present for IPA v4.5 and IPA v4.7 */ 93 #define IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN_FMASK GENMASK(21, 21) 94 /* The next five fields are present for IPA v4.9+ */ 95 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 96 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 97 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 98 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 99 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 100 101 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 102 #define RX_FMASK GENMASK(0, 0) 103 #define PROC_FMASK GENMASK(1, 1) 104 #define TX_WRAPPER_FMASK GENMASK(2, 2) 105 #define MISC_FMASK GENMASK(3, 3) 106 #define RAM_ARB_FMASK GENMASK(4, 4) 107 #define FTCH_HPS_FMASK GENMASK(5, 5) 108 #define FTCH_DPS_FMASK GENMASK(6, 6) 109 #define HPS_FMASK GENMASK(7, 7) 110 #define DPS_FMASK GENMASK(8, 8) 111 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 112 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 113 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 114 #define RSRC_MNGR_FMASK GENMASK(12, 12) 115 #define CTX_HANDLER_FMASK GENMASK(13, 13) 116 #define ACK_MNGR_FMASK GENMASK(14, 14) 117 #define D_DCPH_FMASK GENMASK(15, 15) 118 #define H_DCPH_FMASK GENMASK(16, 16) 119 /* The next field is not present for IPA v4.5+ */ 120 #define DCMP_FMASK GENMASK(17, 17) 121 /* The next three fields are present for IPA v3.5+ */ 122 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 123 #define TX_0_FMASK GENMASK(19, 19) 124 #define TX_1_FMASK GENMASK(20, 20) 125 /* The next field is present for IPA v3.5.1+ */ 126 #define FNR_FMASK GENMASK(21, 21) 127 /* The next eight fields are present for IPA v4.0+ */ 128 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 129 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 130 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 131 #define QMB_FMASK GENMASK(25, 25) 132 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 133 #define GSI_IF_FMASK GENMASK(27, 27) 134 #define GLOBAL_FMASK GENMASK(28, 28) 135 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 136 /* The next field is present for IPA v4.5+ */ 137 #define DPL_FIFO_FMASK GENMASK(30, 30) 138 /* The next field is present for IPA v4.7+ */ 139 #define DRBIP_FMASK GENMASK(31, 31) 140 141 #define IPA_REG_ROUTE_OFFSET 0x00000048 142 #define ROUTE_DIS_FMASK GENMASK(0, 0) 143 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 144 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 145 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 146 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 147 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 148 149 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 150 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 151 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 152 153 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 154 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 155 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 156 157 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 158 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 159 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 160 /* The next two fields are present for IPA v4.0+ */ 161 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 162 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 163 164 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 165 { 166 if (version < IPA_VERSION_4_0) 167 return 0x000008c; 168 169 return 0x0000148; 170 } 171 172 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 173 { 174 if (version < IPA_VERSION_4_0) 175 return 0x0000090; 176 177 return 0x000014c; 178 } 179 180 /* The next four fields are used for the hash enable and flush registers */ 181 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 182 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 183 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 184 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 185 186 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 187 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 188 { 189 if (version < IPA_VERSION_4_0) 190 return 0x0000010c; 191 192 return 0x000000b4; 193 } 194 195 /* The next register is not present for IPA v4.5+ */ 196 #define IPA_REG_BCR_OFFSET 0x000001d0 197 /* The next two fields are not present for IPA v4.2+ */ 198 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 199 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 200 /* The next field is invalid for IPA v4.0+ */ 201 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 202 /* The next two fields are not present for IPA v4.2+ */ 203 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 204 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 205 /* The next five fields are present for IPA v3.5+ */ 206 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 207 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 208 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 209 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 210 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 211 212 /* Backward compatibility register value to use for each version */ 213 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 214 { 215 if (version == IPA_VERSION_3_5_1) 216 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 217 BCR_TX_NOT_USING_BRESP_FMASK | 218 BCR_SUSPEND_L2_IRQ_FMASK | 219 BCR_HOLB_DROP_L2_IRQ_FMASK | 220 BCR_DUAL_TX_FMASK; 221 222 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 223 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 224 BCR_SUSPEND_L2_IRQ_FMASK | 225 BCR_HOLB_DROP_L2_IRQ_FMASK | 226 BCR_DUAL_TX_FMASK; 227 228 /* assert(version != IPA_VERSION_4_5); */ 229 230 return 0x00000000; 231 } 232 233 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 234 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 235 236 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 237 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 238 u32 addr) 239 { 240 if (version < IPA_VERSION_4_5) 241 return u32_encode_bits(addr, GENMASK(16, 0)); 242 243 return u32_encode_bits(addr, GENMASK(17, 0)); 244 } 245 246 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 247 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 248 249 /* The next register is not present for IPA v4.5+ */ 250 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 251 /* The next field is not present for IPA v3.5+ */ 252 #define EOT_COAL_GRANULARITY GENMASK(3, 0) 253 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 254 255 /* The next register is present for IPA v3.5+ */ 256 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 257 /* The next three fields are not present for IPA v4.0+ */ 258 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 259 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 260 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 261 /* The next six fields are present for IPA v4.0+ */ 262 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 263 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 264 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 265 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 266 #define PA_MASK_EN_FMASK GENMASK(12, 12) 267 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 268 /* The next field is present for IPA v4.5+ */ 269 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 270 /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 271 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 272 /* The next field is present for IPA v4.2 only */ 273 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 274 275 /* The next register is present for IPA v3.5+ */ 276 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 277 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 278 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 279 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 280 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 281 282 /* The next register is present for IPA v3.5+ */ 283 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 284 { 285 if (version >= IPA_VERSION_4_2) 286 return 0x00000240; 287 288 return 0x00000220; 289 } 290 291 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 292 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 293 294 /* The next register is present for IPA v4.5+ */ 295 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 296 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 297 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 298 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 299 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 300 301 /* The next register is present for IPA v4.5+ */ 302 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 303 #define DIV_VALUE_FMASK GENMASK(8, 0) 304 #define DIV_ENABLE_FMASK GENMASK(31, 31) 305 306 /* The next register is present for IPA v4.5+ */ 307 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 308 #define GRAN_0_FMASK GENMASK(2, 0) 309 #define GRAN_1_FMASK GENMASK(5, 3) 310 #define GRAN_2_FMASK GENMASK(8, 6) 311 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 312 enum ipa_pulse_gran { 313 IPA_GRAN_10_US = 0x0, 314 IPA_GRAN_20_US = 0x1, 315 IPA_GRAN_50_US = 0x2, 316 IPA_GRAN_100_US = 0x3, 317 IPA_GRAN_1_MS = 0x4, 318 IPA_GRAN_10_MS = 0x5, 319 IPA_GRAN_100_MS = 0x6, 320 IPA_GRAN_655350_US = 0x7, 321 }; 322 323 /* # IPA source resource groups available based on version */ 324 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 325 { 326 switch (version) { 327 case IPA_VERSION_3_5_1: 328 case IPA_VERSION_4_0: 329 case IPA_VERSION_4_1: 330 return 4; 331 332 case IPA_VERSION_4_2: 333 return 1; 334 335 case IPA_VERSION_4_5: 336 return 5; 337 338 default: 339 return 0; 340 } 341 } 342 343 /* # IPA destination resource groups available based on version */ 344 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 345 { 346 switch (version) { 347 case IPA_VERSION_3_5_1: 348 return 3; 349 350 case IPA_VERSION_4_0: 351 case IPA_VERSION_4_1: 352 return 4; 353 354 case IPA_VERSION_4_2: 355 return 1; 356 357 case IPA_VERSION_4_5: 358 return 5; 359 360 default: 361 return 0; 362 } 363 } 364 365 /* Not all of the following are present (depends on IPA version) */ 366 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 367 (0x00000400 + 0x0020 * (rt)) 368 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 369 (0x00000404 + 0x0020 * (rt)) 370 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 371 (0x00000408 + 0x0020 * (rt)) 372 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 373 (0x00000500 + 0x0020 * (rt)) 374 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 375 (0x00000504 + 0x0020 * (rt)) 376 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 377 (0x00000508 + 0x0020 * (rt)) 378 /* The next four fields are used for all resource group registers */ 379 #define X_MIN_LIM_FMASK GENMASK(5, 0) 380 #define X_MAX_LIM_FMASK GENMASK(13, 8) 381 /* The next two fields are not always present (if resource count is odd) */ 382 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 383 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 384 385 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 386 (0x00000800 + 0x0070 * (ep)) 387 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 388 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 389 /* Valid only for TX (IPA consumer) endpoints */ 390 #define ENDP_DELAY_FMASK GENMASK(1, 1) 391 392 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 393 (0x00000808 + 0x0070 * (ep)) 394 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 395 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 396 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 397 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 398 399 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 400 enum ipa_cs_offload_en { 401 IPA_CS_OFFLOAD_NONE = 0x0, 402 IPA_CS_OFFLOAD_UL = 0x1, /* Before IPA v4.5 (TX) */ 403 IPA_CS_OFFLOAD_DL = 0x2, /* Before IPA v4.5 (RX) */ 404 }; 405 406 /* Valid only for TX (IPA consumer) endpoints */ 407 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 408 (0x0000080c + 0x0070 * (ep)) 409 #define NAT_EN_FMASK GENMASK(1, 0) 410 411 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 412 enum ipa_nat_en { 413 IPA_NAT_BYPASS = 0x0, 414 IPA_NAT_SRC = 0x1, 415 IPA_NAT_DST = 0x2, 416 }; 417 418 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 419 (0x00000810 + 0x0070 * (ep)) 420 #define HDR_LEN_FMASK GENMASK(5, 0) 421 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 422 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 423 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 424 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 425 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 426 /* The next field is not present for IPA v4.9+ */ 427 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 428 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 429 /* The next field is not present for IPA v4.5+ */ 430 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 431 /* The next two fields are present for IPA v4.5+ */ 432 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 433 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 434 435 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 436 static inline u32 ipa_header_size_encoded(enum ipa_version version, 437 u32 header_size) 438 { 439 u32 size = header_size & field_mask(HDR_LEN_FMASK); 440 u32 val; 441 442 val = u32_encode_bits(size, HDR_LEN_FMASK); 443 if (version < IPA_VERSION_4_5) { 444 /* ipa_assert(header_size == size); */ 445 return val; 446 } 447 448 /* IPA v4.5 adds a few more most-significant bits */ 449 size = header_size >> hweight32(HDR_LEN_FMASK); 450 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 451 452 return val; 453 } 454 455 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 456 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 457 u32 offset) 458 { 459 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 460 u32 val; 461 462 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 463 if (version < IPA_VERSION_4_5) { 464 /* ipa_assert(offset == off); */ 465 return val; 466 } 467 468 /* IPA v4.5 adds a few more most-significant bits */ 469 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 470 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 471 472 return val; 473 } 474 475 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 476 (0x00000814 + 0x0070 * (ep)) 477 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 478 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 479 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 480 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 481 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 482 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 483 /* The next three fields are present for IPA v4.5+ */ 484 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 485 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 486 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 487 488 /* Valid only for RX (IPA producer) endpoints */ 489 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 490 (0x00000818 + 0x0070 * (rxep)) 491 492 /* Valid only for TX (IPA consumer) endpoints */ 493 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 494 (0x00000820 + 0x0070 * (txep)) 495 #define MODE_FMASK GENMASK(2, 0) 496 /* The next field is present for IPA v4.5+ */ 497 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 498 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 499 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 500 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 501 #define PAD_EN_FMASK GENMASK(29, 29) 502 /* The next field is not present for IPA v4.5+ */ 503 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 504 /* The next field is present for IPA v4.9+ */ 505 #define DRBIP_ACL_ENABLE GENMASK(30, 30) 506 507 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 508 enum ipa_mode { 509 IPA_BASIC = 0x0, 510 IPA_ENABLE_FRAMING_HDLC = 0x1, 511 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 512 IPA_DMA = 0x3, 513 }; 514 515 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 516 (0x00000824 + 0x0070 * (ep)) 517 #define AGGR_EN_FMASK GENMASK(1, 0) 518 #define AGGR_TYPE_FMASK GENMASK(4, 2) 519 520 /* The legacy value is used for IPA hardware before IPA v4.5 */ 521 static inline u32 aggr_byte_limit_fmask(bool legacy) 522 { 523 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 524 } 525 526 /* The legacy value is used for IPA hardware before IPA v4.5 */ 527 static inline u32 aggr_time_limit_fmask(bool legacy) 528 { 529 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 530 } 531 532 /* The legacy value is used for IPA hardware before IPA v4.5 */ 533 static inline u32 aggr_pkt_limit_fmask(bool legacy) 534 { 535 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 536 } 537 538 /* The legacy value is used for IPA hardware before IPA v4.5 */ 539 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 540 { 541 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 542 } 543 544 /* The legacy value is used for IPA hardware before IPA v4.5 */ 545 static inline u32 aggr_force_close_fmask(bool legacy) 546 { 547 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 548 } 549 550 /* The legacy value is used for IPA hardware before IPA v4.5 */ 551 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 552 { 553 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 554 } 555 556 /* The next field is present for IPA v4.5+ */ 557 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 558 559 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 560 enum ipa_aggr_en { 561 IPA_BYPASS_AGGR = 0x0, /* (TX, RX) */ 562 IPA_ENABLE_AGGR = 0x1, /* (RX) */ 563 IPA_ENABLE_DEAGGR = 0x2, /* (TX) */ 564 }; 565 566 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 567 enum ipa_aggr_type { 568 IPA_MBIM_16 = 0x0, 569 IPA_HDLC = 0x1, 570 IPA_TLP = 0x2, 571 IPA_RNDIS = 0x3, 572 IPA_GENERIC = 0x4, 573 IPA_COALESCE = 0x5, 574 IPA_QCMAP = 0x6, 575 }; 576 577 /* Valid only for RX (IPA producer) endpoints */ 578 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 579 (0x0000082c + 0x0070 * (rxep)) 580 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 581 582 /* Valid only for RX (IPA producer) endpoints */ 583 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 584 (0x00000830 + 0x0070 * (rxep)) 585 /* The next two fields are present for IPA v4.2 only */ 586 #define BASE_VALUE_FMASK GENMASK(4, 0) 587 #define SCALE_FMASK GENMASK(12, 8) 588 /* The next two fields are present for IPA v4.5 */ 589 #define TIME_LIMIT_FMASK GENMASK(4, 0) 590 #define GRAN_SEL_FMASK GENMASK(8, 8) 591 592 /* Valid only for TX (IPA consumer) endpoints */ 593 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 594 (0x00000834 + 0x0070 * (txep)) 595 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 596 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 597 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 598 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 599 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 600 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 601 602 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 603 (0x00000838 + 0x0070 * (ep)) 604 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 605 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 606 { 607 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 608 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 609 610 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 611 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 612 613 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 614 } 615 616 /* Valid only for TX (IPA consumer) endpoints */ 617 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 618 (0x0000083c + 0x0070 * (txep)) 619 #define SEQ_TYPE_FMASK GENMASK(7, 0) 620 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 621 622 /** 623 * enum ipa_seq_type - HPS and DPS sequencer type 624 * @IPA_SEQ_DMA: Perform DMA only 625 * @IPA_SEQ_1_PASS: One pass through the pipeline 626 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 627 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 628 * @IPA_SEQ_2_PASS: Two passes through the pipeline 629 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 630 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 631 * 632 * The low-order byte of the sequencer type register defines the number of 633 * passes a packet takes through the IPA pipeline. The last pass through can 634 * optionally skip the microprocessor. Deciphering is optional for all types; 635 * if enabled, an additional mask (two bits) is added to the type value. 636 * 637 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 638 * supported (or meaningful). 639 */ 640 enum ipa_seq_type { 641 IPA_SEQ_DMA = 0x00, 642 IPA_SEQ_1_PASS = 0x02, 643 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 644 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 645 IPA_SEQ_2_PASS = 0x0a, 646 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 647 /* The next value can be ORed with the above */ 648 IPA_SEQ_DECIPHER = 0x11, 649 }; 650 651 /** 652 * enum ipa_seq_rep_type - replicated packet sequencer type 653 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 654 * 655 * This goes in the second byte of the endpoint sequencer type register. 656 * 657 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 658 * supported (or meaningful). 659 */ 660 enum ipa_seq_rep_type { 661 IPA_SEQ_REP_DMA_PARSER = 0x08, 662 }; 663 664 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 665 (0x00000840 + 0x0070 * (ep)) 666 #define STATUS_EN_FMASK GENMASK(0, 0) 667 #define STATUS_ENDP_FMASK GENMASK(5, 1) 668 /* The next field is not present for IPA v4.5+ */ 669 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 670 /* The next field is present for IPA v4.0+ */ 671 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 672 673 /* The next register is not present for IPA v4.2 (which no hashing support) */ 674 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 675 (0x0000085c + 0x0070 * (er)) 676 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 677 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 678 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 679 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 680 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 681 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 682 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 683 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 684 685 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 686 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 687 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 688 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 689 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 690 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 691 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 692 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 693 694 #define IPA_REG_IRQ_STTS_OFFSET \ 695 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 696 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 697 (0x00003008 + 0x1000 * (ee)) 698 699 #define IPA_REG_IRQ_EN_OFFSET \ 700 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 701 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 702 (0x0000300c + 0x1000 * (ee)) 703 704 #define IPA_REG_IRQ_CLR_OFFSET \ 705 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 706 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 707 (0x00003010 + 0x1000 * (ee)) 708 /** 709 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 710 * @IPA_IRQ_UC_0: Microcontroller event interrupt 711 * @IPA_IRQ_UC_1: Microcontroller response interrupt 712 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 713 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 714 * 715 * IRQ types not described above are not currently used. 716 * 717 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 718 * @IPA_IRQ_EOT_COAL: (Not currently used) 719 * @IPA_IRQ_UC_2: (Not currently used) 720 * @IPA_IRQ_UC_3: (Not currently used) 721 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 722 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 723 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 724 * @IPA_IRQ_RX_ERR: (Not currently used) 725 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 726 * @IPA_IRQ_TX_ERR: (Not currently used) 727 * @IPA_IRQ_STEP_MODE: (Not currently used) 728 * @IPA_IRQ_PROC_ERR: (Not currently used) 729 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 730 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 731 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 732 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 733 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 734 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 735 * @IPA_IRQ_UCP: (Not currently used) 736 * @IPA_IRQ_DCMP: (Not currently used) 737 * @IPA_IRQ_GSI_EE: (Not currently used) 738 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 739 * @IPA_IRQ_GSI_UC: (Not currently used) 740 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 741 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 742 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 743 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 744 */ 745 enum ipa_irq_id { 746 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 747 /* The next bit is not present for IPA v3.5+ */ 748 IPA_IRQ_EOT_COAL = 0x1, 749 IPA_IRQ_UC_0 = 0x2, 750 IPA_IRQ_UC_1 = 0x3, 751 IPA_IRQ_UC_2 = 0x4, 752 IPA_IRQ_UC_3 = 0x5, 753 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 754 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 755 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 756 IPA_IRQ_RX_ERR = 0x9, 757 IPA_IRQ_DEAGGR_ERR = 0xa, 758 IPA_IRQ_TX_ERR = 0xb, 759 IPA_IRQ_STEP_MODE = 0xc, 760 IPA_IRQ_PROC_ERR = 0xd, 761 IPA_IRQ_TX_SUSPEND = 0xe, 762 IPA_IRQ_TX_HOLB_DROP = 0xf, 763 IPA_IRQ_BAM_GSI_IDLE = 0x10, 764 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 765 IPA_IRQ_PIPE_RED_BELOW = 0x12, 766 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 767 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 768 IPA_IRQ_UCP = 0x15, 769 /* The next bit is not present for IPA v4.5+ */ 770 IPA_IRQ_DCMP = 0x16, 771 IPA_IRQ_GSI_EE = 0x17, 772 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 773 IPA_IRQ_GSI_UC = 0x19, 774 /* The next bit is present for IPA v4.5+ */ 775 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 776 /* The next three bits are present for IPA v4.9+ */ 777 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 778 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 779 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 780 IPA_IRQ_COUNT, /* Last; not an id */ 781 }; 782 783 #define IPA_REG_IRQ_UC_OFFSET \ 784 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 785 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 786 (0x0000301c + 0x1000 * (ee)) 787 #define UC_INTR_FMASK GENMASK(0, 0) 788 789 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 790 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 791 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 792 /* This register is at (0x00003098 + 0x1000 * (ee)) for IPA v3.0 */ 793 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 794 (0x00003030 + 0x1000 * (ee)) 795 796 /* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ 797 /* This register is present for IPA v3.1+ */ 798 #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ 799 IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) 800 #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ 801 (0x00003034 + 0x1000 * (ee)) 802 803 /* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ 804 /* This register is present for IPA v3.1+ */ 805 #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ 806 IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) 807 #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ 808 (0x00003038 + 0x1000 * (ee)) 809 810 int ipa_reg_init(struct ipa *ipa); 811 void ipa_reg_exit(struct ipa *ipa); 812 813 #endif /* _IPA_REG_H_ */ 814