1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 70 #define ENABLE_FMASK GENMASK(0, 0) 71 /* The next field is present for IPA v4.7+ */ 72 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 73 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 74 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 75 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 76 /* The next field is not present for IPA v4.5+ */ 77 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 78 /* The next twelve fields are present for IPA v4.0+ */ 79 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 80 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 81 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 82 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 83 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 84 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 85 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 86 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 87 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 88 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 89 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 90 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 91 /* The next five fields are present for IPA v4.9+ */ 92 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 93 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 94 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 95 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 96 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 97 98 /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ 99 static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, 100 u32 mask) 101 { 102 /* assert(version >= IPA_VERSION_4_0); */ 103 104 if (version < IPA_VERSION_4_9) 105 return u32_encode_bits(mask, GENMASK(20, 17)); 106 107 if (version == IPA_VERSION_4_9) 108 return u32_encode_bits(mask, GENMASK(24, 22)); 109 110 return u32_encode_bits(mask, GENMASK(23, 22)); 111 } 112 113 /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ 114 static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, 115 bool enable) 116 { 117 u32 val = enable ? 1 : 0; 118 119 /* assert(version >= IPA_VERSION_4_5); */ 120 121 if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) 122 return u32_encode_bits(val, GENMASK(21, 21)); 123 124 return u32_encode_bits(val, GENMASK(17, 17)); 125 } 126 127 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 128 #define RX_FMASK GENMASK(0, 0) 129 #define PROC_FMASK GENMASK(1, 1) 130 #define TX_WRAPPER_FMASK GENMASK(2, 2) 131 #define MISC_FMASK GENMASK(3, 3) 132 #define RAM_ARB_FMASK GENMASK(4, 4) 133 #define FTCH_HPS_FMASK GENMASK(5, 5) 134 #define FTCH_DPS_FMASK GENMASK(6, 6) 135 #define HPS_FMASK GENMASK(7, 7) 136 #define DPS_FMASK GENMASK(8, 8) 137 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 138 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 139 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 140 #define RSRC_MNGR_FMASK GENMASK(12, 12) 141 #define CTX_HANDLER_FMASK GENMASK(13, 13) 142 #define ACK_MNGR_FMASK GENMASK(14, 14) 143 #define D_DCPH_FMASK GENMASK(15, 15) 144 #define H_DCPH_FMASK GENMASK(16, 16) 145 /* The next field is not present for IPA v4.5+ */ 146 #define DCMP_FMASK GENMASK(17, 17) 147 /* The next three fields are present for IPA v3.5+ */ 148 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 149 #define TX_0_FMASK GENMASK(19, 19) 150 #define TX_1_FMASK GENMASK(20, 20) 151 /* The next field is present for IPA v3.5.1+ */ 152 #define FNR_FMASK GENMASK(21, 21) 153 /* The next eight fields are present for IPA v4.0+ */ 154 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 155 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 156 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 157 #define QMB_FMASK GENMASK(25, 25) 158 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 159 #define GSI_IF_FMASK GENMASK(27, 27) 160 #define GLOBAL_FMASK GENMASK(28, 28) 161 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 162 /* The next field is present for IPA v4.5+ */ 163 #define DPL_FIFO_FMASK GENMASK(30, 30) 164 /* The next field is present for IPA v4.7+ */ 165 #define DRBIP_FMASK GENMASK(31, 31) 166 167 #define IPA_REG_ROUTE_OFFSET 0x00000048 168 #define ROUTE_DIS_FMASK GENMASK(0, 0) 169 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 170 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 171 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 172 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 173 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 174 175 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 176 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 177 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 178 179 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 180 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 181 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 182 183 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 184 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 185 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 186 /* The next two fields are present for IPA v4.0+ */ 187 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 188 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 189 190 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 191 { 192 if (version < IPA_VERSION_4_0) 193 return 0x000008c; 194 195 return 0x0000148; 196 } 197 198 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 199 { 200 if (version < IPA_VERSION_4_0) 201 return 0x0000090; 202 203 return 0x000014c; 204 } 205 206 /* The next four fields are used for the hash enable and flush registers */ 207 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 208 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 209 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 210 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 211 212 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 213 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 214 { 215 if (version < IPA_VERSION_4_0) 216 return 0x0000010c; 217 218 return 0x000000b4; 219 } 220 221 /* The next register is not present for IPA v4.5+ */ 222 #define IPA_REG_BCR_OFFSET 0x000001d0 223 /* The next two fields are not present for IPA v4.2+ */ 224 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 225 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 226 /* The next field is invalid for IPA v4.0+ */ 227 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 228 /* The next two fields are not present for IPA v4.2+ */ 229 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 230 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 231 /* The next five fields are present for IPA v3.5+ */ 232 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 233 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 234 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 235 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 236 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 237 238 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 239 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 240 241 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 242 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 243 u32 addr) 244 { 245 if (version < IPA_VERSION_4_5) 246 return u32_encode_bits(addr, GENMASK(16, 0)); 247 248 return u32_encode_bits(addr, GENMASK(17, 0)); 249 } 250 251 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 252 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 253 254 /* The next register is not present for IPA v4.5+ */ 255 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 256 /* The next field is not present for IPA v3.5+ */ 257 #define EOT_COAL_GRANULARITY GENMASK(3, 0) 258 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 259 260 /* The next register is present for IPA v3.5+ */ 261 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 262 /* The next three fields are not present for IPA v4.0+ */ 263 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 264 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 265 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 266 /* The next six fields are present for IPA v4.0+ */ 267 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 268 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 269 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 270 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 271 #define PA_MASK_EN_FMASK GENMASK(12, 12) 272 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 273 /* The next field is present for IPA v4.5+ */ 274 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 275 /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 276 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 277 /* The next field is present for IPA v4.2 only */ 278 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 279 280 /* The next register is present for IPA v3.5+ */ 281 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 282 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 283 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 284 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 285 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 286 287 /* The next register is present for IPA v3.5+ */ 288 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 289 { 290 if (version >= IPA_VERSION_4_2) 291 return 0x00000240; 292 293 return 0x00000220; 294 } 295 296 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 297 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 298 299 /* The next register is present for IPA v4.5+ */ 300 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 301 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 302 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 303 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 304 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 305 306 /* The next register is present for IPA v4.5+ */ 307 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 308 #define DIV_VALUE_FMASK GENMASK(8, 0) 309 #define DIV_ENABLE_FMASK GENMASK(31, 31) 310 311 /* The next register is present for IPA v4.5+ */ 312 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 313 #define GRAN_0_FMASK GENMASK(2, 0) 314 #define GRAN_1_FMASK GENMASK(5, 3) 315 #define GRAN_2_FMASK GENMASK(8, 6) 316 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 317 enum ipa_pulse_gran { 318 IPA_GRAN_10_US = 0x0, 319 IPA_GRAN_20_US = 0x1, 320 IPA_GRAN_50_US = 0x2, 321 IPA_GRAN_100_US = 0x3, 322 IPA_GRAN_1_MS = 0x4, 323 IPA_GRAN_10_MS = 0x5, 324 IPA_GRAN_100_MS = 0x6, 325 IPA_GRAN_655350_US = 0x7, 326 }; 327 328 /* Not all of the following are present (depends on IPA version) */ 329 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 330 (0x00000400 + 0x0020 * (rt)) 331 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 332 (0x00000404 + 0x0020 * (rt)) 333 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 334 (0x00000408 + 0x0020 * (rt)) 335 #define IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 336 (0x0000040c + 0x0020 * (rt)) 337 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 338 (0x00000500 + 0x0020 * (rt)) 339 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 340 (0x00000504 + 0x0020 * (rt)) 341 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 342 (0x00000508 + 0x0020 * (rt)) 343 #define IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 344 (0x0000050c + 0x0020 * (rt)) 345 /* The next four fields are used for all resource group registers */ 346 #define X_MIN_LIM_FMASK GENMASK(5, 0) 347 #define X_MAX_LIM_FMASK GENMASK(13, 8) 348 /* The next two fields are not always present (if resource count is odd) */ 349 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 350 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 351 352 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 353 (0x00000800 + 0x0070 * (ep)) 354 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 355 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 356 /* Valid only for TX (IPA consumer) endpoints */ 357 #define ENDP_DELAY_FMASK GENMASK(1, 1) 358 359 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 360 (0x00000808 + 0x0070 * (ep)) 361 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 362 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 363 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 364 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 365 366 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 367 enum ipa_cs_offload_en { 368 IPA_CS_OFFLOAD_NONE = 0x0, 369 IPA_CS_OFFLOAD_UL = 0x1, /* Before IPA v4.5 (TX) */ 370 IPA_CS_OFFLOAD_DL = 0x2, /* Before IPA v4.5 (RX) */ 371 IPA_CS_OFFLOAD_INLINE = 0x1, /* IPA v4.5 (TX and RX) */ 372 }; 373 374 /* Valid only for TX (IPA consumer) endpoints */ 375 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 376 (0x0000080c + 0x0070 * (ep)) 377 #define NAT_EN_FMASK GENMASK(1, 0) 378 379 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 380 enum ipa_nat_en { 381 IPA_NAT_BYPASS = 0x0, 382 IPA_NAT_SRC = 0x1, 383 IPA_NAT_DST = 0x2, 384 }; 385 386 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 387 (0x00000810 + 0x0070 * (ep)) 388 #define HDR_LEN_FMASK GENMASK(5, 0) 389 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 390 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 391 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 392 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 393 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 394 /* The next field is not present for IPA v4.9+ */ 395 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 396 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 397 /* The next field is not present for IPA v4.5+ */ 398 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 399 /* The next two fields are present for IPA v4.5+ */ 400 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 401 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 402 403 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 404 static inline u32 ipa_header_size_encoded(enum ipa_version version, 405 u32 header_size) 406 { 407 u32 size = header_size & field_mask(HDR_LEN_FMASK); 408 u32 val; 409 410 val = u32_encode_bits(size, HDR_LEN_FMASK); 411 if (version < IPA_VERSION_4_5) { 412 /* ipa_assert(header_size == size); */ 413 return val; 414 } 415 416 /* IPA v4.5 adds a few more most-significant bits */ 417 size = header_size >> hweight32(HDR_LEN_FMASK); 418 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 419 420 return val; 421 } 422 423 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 424 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 425 u32 offset) 426 { 427 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 428 u32 val; 429 430 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 431 if (version < IPA_VERSION_4_5) { 432 /* ipa_assert(offset == off); */ 433 return val; 434 } 435 436 /* IPA v4.5 adds a few more most-significant bits */ 437 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 438 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 439 440 return val; 441 } 442 443 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 444 (0x00000814 + 0x0070 * (ep)) 445 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 446 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 447 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 448 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 449 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 450 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 451 /* The next three fields are present for IPA v4.5+ */ 452 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 453 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 454 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 455 456 /* Valid only for RX (IPA producer) endpoints */ 457 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 458 (0x00000818 + 0x0070 * (rxep)) 459 460 /* Valid only for TX (IPA consumer) endpoints */ 461 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 462 (0x00000820 + 0x0070 * (txep)) 463 #define MODE_FMASK GENMASK(2, 0) 464 /* The next field is present for IPA v4.5+ */ 465 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 466 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 467 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 468 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 469 #define PAD_EN_FMASK GENMASK(29, 29) 470 /* The next field is not present for IPA v4.5+ */ 471 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 472 /* The next field is present for IPA v4.9+ */ 473 #define DRBIP_ACL_ENABLE GENMASK(30, 30) 474 475 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 476 enum ipa_mode { 477 IPA_BASIC = 0x0, 478 IPA_ENABLE_FRAMING_HDLC = 0x1, 479 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 480 IPA_DMA = 0x3, 481 }; 482 483 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 484 (0x00000824 + 0x0070 * (ep)) 485 #define AGGR_EN_FMASK GENMASK(1, 0) 486 #define AGGR_TYPE_FMASK GENMASK(4, 2) 487 488 /* The legacy value is used for IPA hardware before IPA v4.5 */ 489 static inline u32 aggr_byte_limit_fmask(bool legacy) 490 { 491 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 492 } 493 494 /* The legacy value is used for IPA hardware before IPA v4.5 */ 495 static inline u32 aggr_time_limit_fmask(bool legacy) 496 { 497 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 498 } 499 500 /* The legacy value is used for IPA hardware before IPA v4.5 */ 501 static inline u32 aggr_pkt_limit_fmask(bool legacy) 502 { 503 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 504 } 505 506 /* The legacy value is used for IPA hardware before IPA v4.5 */ 507 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 508 { 509 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 510 } 511 512 /* The legacy value is used for IPA hardware before IPA v4.5 */ 513 static inline u32 aggr_force_close_fmask(bool legacy) 514 { 515 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 516 } 517 518 /* The legacy value is used for IPA hardware before IPA v4.5 */ 519 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 520 { 521 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 522 } 523 524 /* The next field is present for IPA v4.5+ */ 525 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 526 527 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 528 enum ipa_aggr_en { 529 IPA_BYPASS_AGGR = 0x0, /* (TX, RX) */ 530 IPA_ENABLE_AGGR = 0x1, /* (RX) */ 531 IPA_ENABLE_DEAGGR = 0x2, /* (TX) */ 532 }; 533 534 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 535 enum ipa_aggr_type { 536 IPA_MBIM_16 = 0x0, 537 IPA_HDLC = 0x1, 538 IPA_TLP = 0x2, 539 IPA_RNDIS = 0x3, 540 IPA_GENERIC = 0x4, 541 IPA_COALESCE = 0x5, 542 IPA_QCMAP = 0x6, 543 }; 544 545 /* Valid only for RX (IPA producer) endpoints */ 546 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 547 (0x0000082c + 0x0070 * (rxep)) 548 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 549 550 /* Valid only for RX (IPA producer) endpoints */ 551 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 552 (0x00000830 + 0x0070 * (rxep)) 553 /* The next two fields are present for IPA v4.2 only */ 554 #define BASE_VALUE_FMASK GENMASK(4, 0) 555 #define SCALE_FMASK GENMASK(12, 8) 556 /* The next two fields are present for IPA v4.5 */ 557 #define TIME_LIMIT_FMASK GENMASK(4, 0) 558 #define GRAN_SEL_FMASK GENMASK(8, 8) 559 560 /* Valid only for TX (IPA consumer) endpoints */ 561 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 562 (0x00000834 + 0x0070 * (txep)) 563 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 564 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 565 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 566 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 567 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 568 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 569 570 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 571 (0x00000838 + 0x0070 * (ep)) 572 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 573 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 574 { 575 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 576 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 577 578 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 579 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 580 581 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 582 } 583 584 /* Valid only for TX (IPA consumer) endpoints */ 585 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 586 (0x0000083c + 0x0070 * (txep)) 587 #define SEQ_TYPE_FMASK GENMASK(7, 0) 588 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 589 590 /** 591 * enum ipa_seq_type - HPS and DPS sequencer type 592 * @IPA_SEQ_DMA: Perform DMA only 593 * @IPA_SEQ_1_PASS: One pass through the pipeline 594 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 595 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 596 * @IPA_SEQ_2_PASS: Two passes through the pipeline 597 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 598 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 599 * 600 * The low-order byte of the sequencer type register defines the number of 601 * passes a packet takes through the IPA pipeline. The last pass through can 602 * optionally skip the microprocessor. Deciphering is optional for all types; 603 * if enabled, an additional mask (two bits) is added to the type value. 604 * 605 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 606 * supported (or meaningful). 607 */ 608 enum ipa_seq_type { 609 IPA_SEQ_DMA = 0x00, 610 IPA_SEQ_1_PASS = 0x02, 611 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 612 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 613 IPA_SEQ_2_PASS = 0x0a, 614 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 615 /* The next value can be ORed with the above */ 616 IPA_SEQ_DECIPHER = 0x11, 617 }; 618 619 /** 620 * enum ipa_seq_rep_type - replicated packet sequencer type 621 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 622 * 623 * This goes in the second byte of the endpoint sequencer type register. 624 * 625 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 626 * supported (or meaningful). 627 */ 628 enum ipa_seq_rep_type { 629 IPA_SEQ_REP_DMA_PARSER = 0x08, 630 }; 631 632 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 633 (0x00000840 + 0x0070 * (ep)) 634 #define STATUS_EN_FMASK GENMASK(0, 0) 635 #define STATUS_ENDP_FMASK GENMASK(5, 1) 636 /* The next field is not present for IPA v4.5+ */ 637 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 638 /* The next field is present for IPA v4.0+ */ 639 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 640 641 /* The next register is not present for IPA v4.2 (which no hashing support) */ 642 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 643 (0x0000085c + 0x0070 * (er)) 644 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 645 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 646 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 647 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 648 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 649 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 650 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 651 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 652 653 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 654 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 655 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 656 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 657 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 658 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 659 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 660 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 661 662 static inline u32 ipa_reg_irq_stts_ee_n_offset(enum ipa_version version, 663 u32 ee) 664 { 665 if (version < IPA_VERSION_4_9) 666 return 0x00003008 + 0x1000 * ee; 667 668 return 0x00004008 + 0x1000 * ee; 669 } 670 671 static inline u32 ipa_reg_irq_stts_offset(enum ipa_version version) 672 { 673 return ipa_reg_irq_stts_ee_n_offset(version, GSI_EE_AP); 674 } 675 676 static inline u32 ipa_reg_irq_en_ee_n_offset(enum ipa_version version, u32 ee) 677 { 678 if (version < IPA_VERSION_4_9) 679 return 0x0000300c + 0x1000 * ee; 680 681 return 0x0000400c + 0x1000 * ee; 682 } 683 684 static inline u32 ipa_reg_irq_en_offset(enum ipa_version version) 685 { 686 return ipa_reg_irq_en_ee_n_offset(version, GSI_EE_AP); 687 } 688 689 static inline u32 ipa_reg_irq_clr_ee_n_offset(enum ipa_version version, u32 ee) 690 { 691 if (version < IPA_VERSION_4_9) 692 return 0x00003010 + 0x1000 * ee; 693 694 return 0x00004010 + 0x1000 * ee; 695 } 696 697 static inline u32 ipa_reg_irq_clr_offset(enum ipa_version version) 698 { 699 return ipa_reg_irq_clr_ee_n_offset(version, GSI_EE_AP); 700 } 701 702 /** 703 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 704 * @IPA_IRQ_UC_0: Microcontroller event interrupt 705 * @IPA_IRQ_UC_1: Microcontroller response interrupt 706 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 707 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 708 * 709 * IRQ types not described above are not currently used. 710 * 711 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 712 * @IPA_IRQ_EOT_COAL: (Not currently used) 713 * @IPA_IRQ_UC_2: (Not currently used) 714 * @IPA_IRQ_UC_3: (Not currently used) 715 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 716 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 717 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 718 * @IPA_IRQ_RX_ERR: (Not currently used) 719 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 720 * @IPA_IRQ_TX_ERR: (Not currently used) 721 * @IPA_IRQ_STEP_MODE: (Not currently used) 722 * @IPA_IRQ_PROC_ERR: (Not currently used) 723 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 724 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 725 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 726 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 727 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 728 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 729 * @IPA_IRQ_UCP: (Not currently used) 730 * @IPA_IRQ_DCMP: (Not currently used) 731 * @IPA_IRQ_GSI_EE: (Not currently used) 732 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 733 * @IPA_IRQ_GSI_UC: (Not currently used) 734 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 735 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 736 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 737 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 738 */ 739 enum ipa_irq_id { 740 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 741 /* The next bit is not present for IPA v3.5+ */ 742 IPA_IRQ_EOT_COAL = 0x1, 743 IPA_IRQ_UC_0 = 0x2, 744 IPA_IRQ_UC_1 = 0x3, 745 IPA_IRQ_UC_2 = 0x4, 746 IPA_IRQ_UC_3 = 0x5, 747 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 748 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 749 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 750 IPA_IRQ_RX_ERR = 0x9, 751 IPA_IRQ_DEAGGR_ERR = 0xa, 752 IPA_IRQ_TX_ERR = 0xb, 753 IPA_IRQ_STEP_MODE = 0xc, 754 IPA_IRQ_PROC_ERR = 0xd, 755 IPA_IRQ_TX_SUSPEND = 0xe, 756 IPA_IRQ_TX_HOLB_DROP = 0xf, 757 IPA_IRQ_BAM_GSI_IDLE = 0x10, 758 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 759 IPA_IRQ_PIPE_RED_BELOW = 0x12, 760 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 761 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 762 IPA_IRQ_UCP = 0x15, 763 /* The next bit is not present for IPA v4.5+ */ 764 IPA_IRQ_DCMP = 0x16, 765 IPA_IRQ_GSI_EE = 0x17, 766 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 767 IPA_IRQ_GSI_UC = 0x19, 768 /* The next bit is present for IPA v4.5+ */ 769 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 770 /* The next three bits are present for IPA v4.9+ */ 771 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 772 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 773 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 774 IPA_IRQ_COUNT, /* Last; not an id */ 775 }; 776 777 static inline u32 ipa_reg_irq_uc_ee_n_offset(enum ipa_version version, u32 ee) 778 { 779 if (version < IPA_VERSION_4_9) 780 return 0x0000301c + 0x1000 * ee; 781 782 return 0x0000401c + 0x1000 * ee; 783 } 784 785 static inline u32 ipa_reg_irq_uc_offset(enum ipa_version version) 786 { 787 return ipa_reg_irq_uc_ee_n_offset(version, GSI_EE_AP); 788 } 789 790 #define UC_INTR_FMASK GENMASK(0, 0) 791 792 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 793 static inline u32 794 ipa_reg_irq_suspend_info_ee_n_offset(enum ipa_version version, u32 ee) 795 { 796 if (version == IPA_VERSION_3_0) 797 return 0x00003098 + 0x1000 * ee; 798 799 if (version < IPA_VERSION_4_9) 800 return 0x00003030 + 0x1000 * ee; 801 802 return 0x00004030 + 0x1000 * ee; 803 } 804 805 static inline u32 806 ipa_reg_irq_suspend_info_offset(enum ipa_version version) 807 { 808 return ipa_reg_irq_suspend_info_ee_n_offset(version, GSI_EE_AP); 809 } 810 811 /* ipa->available defines the valid bits in the SUSPEND_EN register */ 812 static inline u32 813 ipa_reg_irq_suspend_en_ee_n_offset(enum ipa_version version, u32 ee) 814 { 815 /* assert(version != IPA_VERSION_3_0); */ 816 817 if (version < IPA_VERSION_4_9) 818 return 0x00003034 + 0x1000 * ee; 819 820 return 0x00004034 + 0x1000 * ee; 821 } 822 823 static inline u32 824 ipa_reg_irq_suspend_en_offset(enum ipa_version version) 825 { 826 return ipa_reg_irq_suspend_en_ee_n_offset(version, GSI_EE_AP); 827 } 828 829 /* ipa->available defines the valid bits in the SUSPEND_CLR register */ 830 static inline u32 831 ipa_reg_irq_suspend_clr_ee_n_offset(enum ipa_version version, u32 ee) 832 { 833 /* assert(version != IPA_VERSION_3_0); */ 834 835 if (version < IPA_VERSION_4_9) 836 return 0x00003038 + 0x1000 * ee; 837 838 return 0x00004038 + 0x1000 * ee; 839 } 840 841 static inline u32 842 ipa_reg_irq_suspend_clr_offset(enum ipa_version version) 843 { 844 return ipa_reg_irq_suspend_clr_ee_n_offset(version, GSI_EE_AP); 845 } 846 847 int ipa_reg_init(struct ipa *ipa); 848 void ipa_reg_exit(struct ipa *ipa); 849 850 #endif /* _IPA_REG_H_ */ 851