1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 14 struct ipa; 15 16 /** 17 * DOC: IPA Registers 18 * 19 * IPA registers are located within the "ipa-reg" address space defined by 20 * Device Tree. The offset of each register within that space is specified 21 * by symbols defined below. The address space is mapped to virtual memory 22 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 23 * 24 * Certain register types are duplicated for a number of instances of 25 * something. For example, each IPA endpoint has an set of registers 26 * defining its configuration. The offset to an endpoint's set of registers 27 * is computed based on an "base" offset, plus an endpoint's ID multiplied 28 * and a "stride" value for the register. For such registers, the offset is 29 * computed by a function-like macro that takes a parameter used in the 30 * computation. 31 * 32 * Some register offsets depend on execution environment. For these an "ee" 33 * parameter is supplied to the offset macro. The "ee" value is a member of 34 * the gsi_ee enumerated type. 35 * 36 * The offset of a register dependent on endpoint ID is computed by a macro 37 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 38 * "ep" parameter is valid for any endpoint; a register with a "txep" or 39 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 40 * "*ep" value is assumed to be less than the maximum valid endpoint ID 41 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 42 * 43 * The offset of registers related to filter and route tables is computed 44 * by a macro that is supplied a parameter "er". The "er" represents an 45 * endpoint ID for filters, or a route ID for routes. For filters, the 46 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 47 * because not all endpoints support filtering. For routes, the route ID 48 * must be less than IPA_ROUTE_MAX. 49 * 50 * The offset of registers related to resource types is computed by a macro 51 * that is supplied a parameter "rt". The "rt" represents a resource type, 52 * which is a member of the ipa_resource_type_src enumerated type for 53 * source endpoint resources or the ipa_resource_type_dst enumerated type 54 * for destination endpoint resources. 55 * 56 * Some registers encode multiple fields within them. For these, each field 57 * has a symbol below defining a field mask that encodes both the position 58 * and width of the field within its register. 59 * 60 * In some cases, different versions of IPA hardware use different offset or 61 * field mask values. In such cases an inline_function(ipa) is used rather 62 * than a MACRO to define the offset or field mask to use. 63 * 64 * Finally, some registers hold bitmasks representing endpoints. In such 65 * cases the @available field in the @ipa structure defines the "full" set 66 * of valid bits for the register. 67 */ 68 69 /* enum ipa_reg_id - IPA register IDs */ 70 enum ipa_reg_id { 71 COMP_CFG, 72 CLKON_CFG, 73 ROUTE, 74 SHARED_MEM_SIZE, 75 QSB_MAX_WRITES, 76 QSB_MAX_READS, 77 FILT_ROUT_HASH_EN, 78 FILT_ROUT_HASH_FLUSH, 79 STATE_AGGR_ACTIVE, 80 IPA_BCR, /* Not IPA v4.5+ */ 81 LOCAL_PKT_PROC_CNTXT, 82 AGGR_FORCE_CLOSE, 83 COUNTER_CFG, /* Not IPA v4.5+ */ 84 IPA_TX_CFG, /* IPA v3.5+ */ 85 FLAVOR_0, /* IPA v3.5+ */ 86 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 87 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 88 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 89 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 90 SRC_RSRC_GRP_01_RSRC_TYPE, 91 SRC_RSRC_GRP_23_RSRC_TYPE, 92 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 93 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 94 DST_RSRC_GRP_01_RSRC_TYPE, 95 DST_RSRC_GRP_23_RSRC_TYPE, 96 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 97 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 98 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 99 ENDP_INIT_CFG, 100 ENDP_INIT_NAT, /* TX only */ 101 ENDP_INIT_HDR, 102 ENDP_INIT_HDR_EXT, 103 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 104 ENDP_INIT_MODE, /* TX only */ 105 ENDP_INIT_AGGR, 106 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 107 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 108 ENDP_INIT_DEAGGR, /* TX only */ 109 ENDP_INIT_RSRC_GRP, 110 ENDP_INIT_SEQ, /* TX only */ 111 ENDP_STATUS, 112 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 113 /* The IRQ registers are only used for GSI_EE_AP */ 114 IPA_IRQ_STTS, 115 IPA_IRQ_EN, 116 IPA_IRQ_CLR, 117 IPA_IRQ_UC, 118 IRQ_SUSPEND_INFO, 119 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 120 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 121 IPA_REG_ID_COUNT, /* Last; not an ID */ 122 }; 123 124 /** 125 * struct ipa_reg - An IPA register descriptor 126 * @offset: Register offset relative to base of the "ipa-reg" memory 127 * @stride: Distance between two instances, if parameterized 128 * @fcount: Number of entries in the @fmask array 129 * @fmask: Array of mask values defining position and width of fields 130 * @name: Upper-case name of the IPA register 131 */ 132 struct ipa_reg { 133 u32 offset; 134 u32 stride; 135 u32 fcount; 136 const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ 137 const char *name; 138 }; 139 140 /* Helper macro for defining "simple" (non-parameterized) registers */ 141 #define IPA_REG(__NAME, __reg_id, __offset) \ 142 IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 143 144 /* Helper macro for defining parameterized registers, specifying stride */ 145 #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 146 static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 147 .name = #__NAME, \ 148 .offset = __offset, \ 149 .stride = __stride, \ 150 } 151 152 #define IPA_REG_FIELDS(__NAME, __name, __offset) \ 153 IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) 154 155 #define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ 156 static const struct ipa_reg ipa_reg_ ## __name = { \ 157 .name = #__NAME, \ 158 .offset = __offset, \ 159 .stride = __stride, \ 160 .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ 161 .fmask = ipa_reg_ ## __name ## _fmask, \ 162 } 163 164 /** 165 * struct ipa_regs - Description of registers supported by hardware 166 * @reg_count: Number of registers in the @reg[] array 167 * @reg: Array of register descriptors 168 */ 169 struct ipa_regs { 170 u32 reg_count; 171 const struct ipa_reg **reg; 172 }; 173 174 /* COMP_CFG register */ 175 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 176 #define ENABLE_FMASK GENMASK(0, 0) 177 /* The next field is present for IPA v4.7+ */ 178 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 179 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 180 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 181 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 182 /* The next field is not present for IPA v4.5+ */ 183 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 184 /* The next twelve fields are present for IPA v4.0+ */ 185 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 186 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 187 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 188 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 189 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 190 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 191 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 192 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 193 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 194 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 195 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 196 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 197 /* The next five fields are present for IPA v4.9+ */ 198 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 199 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 200 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 201 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 202 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 203 204 /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ 205 static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, 206 u32 mask) 207 { 208 WARN_ON(version < IPA_VERSION_4_0); 209 210 if (version < IPA_VERSION_4_9) 211 return u32_encode_bits(mask, GENMASK(20, 17)); 212 213 if (version == IPA_VERSION_4_9) 214 return u32_encode_bits(mask, GENMASK(24, 22)); 215 216 return u32_encode_bits(mask, GENMASK(23, 22)); 217 } 218 219 /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ 220 static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, 221 bool enable) 222 { 223 u32 val = enable ? 1 : 0; 224 225 WARN_ON(version < IPA_VERSION_4_5); 226 227 if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) 228 return u32_encode_bits(val, GENMASK(21, 21)); 229 230 return u32_encode_bits(val, GENMASK(17, 17)); 231 } 232 233 /* CLKON_CFG register */ 234 #define RX_FMASK GENMASK(0, 0) 235 #define PROC_FMASK GENMASK(1, 1) 236 #define TX_WRAPPER_FMASK GENMASK(2, 2) 237 #define MISC_FMASK GENMASK(3, 3) 238 #define RAM_ARB_FMASK GENMASK(4, 4) 239 #define FTCH_HPS_FMASK GENMASK(5, 5) 240 #define FTCH_DPS_FMASK GENMASK(6, 6) 241 #define HPS_FMASK GENMASK(7, 7) 242 #define DPS_FMASK GENMASK(8, 8) 243 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 244 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 245 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 246 #define RSRC_MNGR_FMASK GENMASK(12, 12) 247 #define CTX_HANDLER_FMASK GENMASK(13, 13) 248 #define ACK_MNGR_FMASK GENMASK(14, 14) 249 #define D_DCPH_FMASK GENMASK(15, 15) 250 #define H_DCPH_FMASK GENMASK(16, 16) 251 /* The next field is not present for IPA v4.5+ */ 252 #define DCMP_FMASK GENMASK(17, 17) 253 /* The next three fields are present for IPA v3.5+ */ 254 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 255 #define TX_0_FMASK GENMASK(19, 19) 256 #define TX_1_FMASK GENMASK(20, 20) 257 /* The next field is present for IPA v3.5.1+ */ 258 #define FNR_FMASK GENMASK(21, 21) 259 /* The next eight fields are present for IPA v4.0+ */ 260 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 261 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 262 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 263 #define QMB_FMASK GENMASK(25, 25) 264 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 265 #define GSI_IF_FMASK GENMASK(27, 27) 266 #define GLOBAL_FMASK GENMASK(28, 28) 267 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 268 /* The next field is present for IPA v4.5+ */ 269 #define DPL_FIFO_FMASK GENMASK(30, 30) 270 /* The next field is present for IPA v4.7+ */ 271 #define DRBIP_FMASK GENMASK(31, 31) 272 273 /* ROUTE register */ 274 #define ROUTE_DIS_FMASK GENMASK(0, 0) 275 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 276 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 277 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 278 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 279 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 280 281 /* SHARED_MEM_SIZE register */ 282 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 283 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 284 285 /* QSB_MAX_WRITES register */ 286 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 287 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 288 289 /* QSB_MAX_READS register */ 290 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 291 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 292 /* The next two fields are present for IPA v4.0+ */ 293 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 294 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 295 296 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 297 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 298 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 299 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 300 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 301 302 /* BCR register */ 303 enum ipa_bcr_compat { 304 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 305 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 306 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 307 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 308 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 309 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 310 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 311 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 312 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 313 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 314 }; 315 316 /* LOCAL_PKT_PROC_CNTXT register */ 317 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 318 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 319 u32 addr) 320 { 321 if (version < IPA_VERSION_4_5) 322 return u32_encode_bits(addr, GENMASK(16, 0)); 323 324 return u32_encode_bits(addr, GENMASK(17, 0)); 325 } 326 327 /* COUNTER_CFG register */ 328 /* The next field is not present for IPA v3.5+ */ 329 #define EOT_COAL_GRANULARITY_FMASK GENMASK(3, 0) 330 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 331 332 /* IPA_TX_CFG register */ 333 /* The next three fields are not present for IPA v4.0+ */ 334 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 335 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 336 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 337 /* The next six fields are present for IPA v4.0+ */ 338 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 339 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 340 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 341 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 342 #define PA_MASK_EN_FMASK GENMASK(12, 12) 343 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 344 /* The next field is present for IPA v4.5+ */ 345 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 346 /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 347 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 348 /* The next field is present for IPA v4.2 only */ 349 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 350 351 /* FLAVOR_0 register */ 352 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 353 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 354 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 355 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 356 357 /* IDLE_INDICATION_CFG register */ 358 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 359 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 360 361 /* QTIME_TIMESTAMP_CFG register */ 362 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 363 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 364 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 365 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 366 367 /* TIMERS_XO_CLK_DIV_CFG register */ 368 #define DIV_VALUE_FMASK GENMASK(8, 0) 369 #define DIV_ENABLE_FMASK GENMASK(31, 31) 370 371 /* TIMERS_PULSE_GRAN_CFG register */ 372 #define GRAN_0_FMASK GENMASK(2, 0) 373 #define GRAN_1_FMASK GENMASK(5, 3) 374 #define GRAN_2_FMASK GENMASK(8, 6) 375 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 376 enum ipa_pulse_gran { 377 IPA_GRAN_10_US = 0x0, 378 IPA_GRAN_20_US = 0x1, 379 IPA_GRAN_50_US = 0x2, 380 IPA_GRAN_100_US = 0x3, 381 IPA_GRAN_1_MS = 0x4, 382 IPA_GRAN_10_MS = 0x5, 383 IPA_GRAN_100_MS = 0x6, 384 IPA_GRAN_655350_US = 0x7, 385 }; 386 387 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 388 #define X_MIN_LIM_FMASK GENMASK(5, 0) 389 #define X_MAX_LIM_FMASK GENMASK(13, 8) 390 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 391 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 392 393 /* ENDP_INIT_CTRL register */ 394 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 395 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 396 /* Valid only for TX (IPA consumer) endpoints */ 397 #define ENDP_DELAY_FMASK GENMASK(1, 1) 398 399 /* ENDP_INIT_CFG register */ 400 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 401 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 402 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 403 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 404 405 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 406 enum ipa_cs_offload_en { 407 IPA_CS_OFFLOAD_NONE = 0x0, 408 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 409 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 410 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 411 }; 412 413 /* ENDP_INIT_NAT register */ 414 #define NAT_EN_FMASK GENMASK(1, 0) 415 416 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 417 enum ipa_nat_en { 418 IPA_NAT_BYPASS = 0x0, 419 IPA_NAT_SRC = 0x1, 420 IPA_NAT_DST = 0x2, 421 }; 422 423 /* ENDP_INIT_HDR register */ 424 #define HDR_LEN_FMASK GENMASK(5, 0) 425 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 426 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 427 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 428 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 429 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 430 /* The next field is not present for IPA v4.9+ */ 431 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 432 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 433 /* The next field is not present for IPA v4.5+ */ 434 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 435 /* The next two fields are present for IPA v4.5+ */ 436 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 437 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 438 439 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 440 static inline u32 ipa_header_size_encoded(enum ipa_version version, 441 u32 header_size) 442 { 443 u32 size = header_size & field_mask(HDR_LEN_FMASK); 444 u32 val; 445 446 val = u32_encode_bits(size, HDR_LEN_FMASK); 447 if (version < IPA_VERSION_4_5) { 448 WARN_ON(header_size != size); 449 return val; 450 } 451 452 /* IPA v4.5 adds a few more most-significant bits */ 453 size = header_size >> hweight32(HDR_LEN_FMASK); 454 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 455 456 return val; 457 } 458 459 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 460 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 461 u32 offset) 462 { 463 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 464 u32 val; 465 466 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 467 if (version < IPA_VERSION_4_5) { 468 WARN_ON(offset != off); 469 return val; 470 } 471 472 /* IPA v4.5 adds a few more most-significant bits */ 473 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 474 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 475 476 return val; 477 } 478 479 /* ENDP_INIT_HDR_EXT register */ 480 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 481 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 482 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 483 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 484 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 485 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 486 /* The next three fields are present for IPA v4.5+ */ 487 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 488 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 489 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 490 491 /* ENDP_INIT_MODE register */ 492 #define MODE_FMASK GENMASK(2, 0) 493 /* The next field is present for IPA v4.5+ */ 494 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 495 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 496 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 497 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 498 #define PAD_EN_FMASK GENMASK(29, 29) 499 /* The next field is not present for IPA v4.5+ */ 500 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 501 /* The next field is present for IPA v4.9+ */ 502 #define DRBIP_ACL_ENABLE_FMASK GENMASK(30, 30) 503 504 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 505 enum ipa_mode { 506 IPA_BASIC = 0x0, 507 IPA_ENABLE_FRAMING_HDLC = 0x1, 508 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 509 IPA_DMA = 0x3, 510 }; 511 512 /* ENDP_INIT_AGGR register */ 513 #define AGGR_EN_FMASK GENMASK(1, 0) 514 #define AGGR_TYPE_FMASK GENMASK(4, 2) 515 516 /* The legacy value is used for IPA hardware before IPA v4.5 */ 517 static inline u32 aggr_byte_limit_fmask(bool legacy) 518 { 519 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 520 } 521 522 /* The legacy value is used for IPA hardware before IPA v4.5 */ 523 static inline u32 aggr_time_limit_fmask(bool legacy) 524 { 525 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 526 } 527 528 /* The legacy value is used for IPA hardware before IPA v4.5 */ 529 static inline u32 aggr_pkt_limit_fmask(bool legacy) 530 { 531 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 532 } 533 534 /* The legacy value is used for IPA hardware before IPA v4.5 */ 535 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 536 { 537 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 538 } 539 540 /* The legacy value is used for IPA hardware before IPA v4.5 */ 541 static inline u32 aggr_force_close_fmask(bool legacy) 542 { 543 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 544 } 545 546 /* The legacy value is used for IPA hardware before IPA v4.5 */ 547 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 548 { 549 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 550 } 551 552 /* The next field is present for IPA v4.5+ */ 553 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 554 555 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 556 enum ipa_aggr_en { 557 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 558 IPA_ENABLE_AGGR /* RX */ = 0x1, 559 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 560 }; 561 562 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 563 enum ipa_aggr_type { 564 IPA_MBIM_16 = 0x0, 565 IPA_HDLC = 0x1, 566 IPA_TLP = 0x2, 567 IPA_RNDIS = 0x3, 568 IPA_GENERIC = 0x4, 569 IPA_COALESCE = 0x5, 570 IPA_QCMAP = 0x6, 571 }; 572 573 /* ENDP_INIT_HOL_BLOCK_EN register */ 574 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 575 576 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 577 /* The next two fields are present for IPA v4.2 only */ 578 #define BASE_VALUE_FMASK GENMASK(4, 0) 579 #define SCALE_FMASK GENMASK(12, 8) 580 /* The next two fields are present for IPA v4.5 */ 581 #define TIME_LIMIT_FMASK GENMASK(4, 0) 582 #define GRAN_SEL_FMASK GENMASK(8, 8) 583 584 /* ENDP_INIT_DEAGGR register */ 585 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 586 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 587 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 588 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 589 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 590 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 591 592 /* ENDP_INIT_RSRC_GRP register */ 593 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 594 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 595 { 596 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 597 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 598 599 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 600 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 601 602 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 603 } 604 605 /* ENDP_INIT_SEQ register */ 606 #define SEQ_TYPE_FMASK GENMASK(7, 0) 607 /* The next field must be zero for IPA v4.5+ */ 608 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 609 610 /** 611 * enum ipa_seq_type - HPS and DPS sequencer type 612 * @IPA_SEQ_DMA: Perform DMA only 613 * @IPA_SEQ_1_PASS: One pass through the pipeline 614 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 615 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 616 * @IPA_SEQ_2_PASS: Two passes through the pipeline 617 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 618 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 619 * 620 * The low-order byte of the sequencer type register defines the number of 621 * passes a packet takes through the IPA pipeline. The last pass through can 622 * optionally skip the microprocessor. Deciphering is optional for all types; 623 * if enabled, an additional mask (two bits) is added to the type value. 624 * 625 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 626 * supported (or meaningful). 627 */ 628 enum ipa_seq_type { 629 IPA_SEQ_DMA = 0x00, 630 IPA_SEQ_1_PASS = 0x02, 631 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 632 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 633 IPA_SEQ_2_PASS = 0x0a, 634 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 635 /* The next value can be ORed with the above */ 636 IPA_SEQ_DECIPHER = 0x11, 637 }; 638 639 /** 640 * enum ipa_seq_rep_type - replicated packet sequencer type 641 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 642 * 643 * This goes in the second byte of the endpoint sequencer type register. 644 * 645 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 646 * supported (or meaningful). 647 */ 648 enum ipa_seq_rep_type { 649 IPA_SEQ_REP_DMA_PARSER = 0x08, 650 }; 651 652 /* ENDP_STATUS register */ 653 #define STATUS_EN_FMASK GENMASK(0, 0) 654 #define STATUS_ENDP_FMASK GENMASK(5, 1) 655 /* The next field is not present for IPA v4.5+ */ 656 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 657 /* The next field is present for IPA v4.0+ */ 658 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 659 660 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 661 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 662 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 663 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 664 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 665 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 666 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 667 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 668 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 669 670 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 671 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 672 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 673 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 674 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 675 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 676 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 677 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 678 679 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 680 /** 681 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 682 * @IPA_IRQ_UC_0: Microcontroller event interrupt 683 * @IPA_IRQ_UC_1: Microcontroller response interrupt 684 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 685 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 686 * 687 * IRQ types not described above are not currently used. 688 * 689 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 690 * @IPA_IRQ_EOT_COAL: (Not currently used) 691 * @IPA_IRQ_UC_2: (Not currently used) 692 * @IPA_IRQ_UC_3: (Not currently used) 693 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 694 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 695 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 696 * @IPA_IRQ_RX_ERR: (Not currently used) 697 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 698 * @IPA_IRQ_TX_ERR: (Not currently used) 699 * @IPA_IRQ_STEP_MODE: (Not currently used) 700 * @IPA_IRQ_PROC_ERR: (Not currently used) 701 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 702 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 703 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 704 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 705 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 706 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 707 * @IPA_IRQ_UCP: (Not currently used) 708 * @IPA_IRQ_DCMP: (Not currently used) 709 * @IPA_IRQ_GSI_EE: (Not currently used) 710 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 711 * @IPA_IRQ_GSI_UC: (Not currently used) 712 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 713 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 714 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 715 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 716 */ 717 enum ipa_irq_id { 718 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 719 /* The next bit is not present for IPA v3.5+ */ 720 IPA_IRQ_EOT_COAL = 0x1, 721 IPA_IRQ_UC_0 = 0x2, 722 IPA_IRQ_UC_1 = 0x3, 723 IPA_IRQ_UC_2 = 0x4, 724 IPA_IRQ_UC_3 = 0x5, 725 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 726 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 727 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 728 IPA_IRQ_RX_ERR = 0x9, 729 IPA_IRQ_DEAGGR_ERR = 0xa, 730 IPA_IRQ_TX_ERR = 0xb, 731 IPA_IRQ_STEP_MODE = 0xc, 732 IPA_IRQ_PROC_ERR = 0xd, 733 IPA_IRQ_TX_SUSPEND = 0xe, 734 IPA_IRQ_TX_HOLB_DROP = 0xf, 735 IPA_IRQ_BAM_GSI_IDLE = 0x10, 736 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 737 IPA_IRQ_PIPE_RED_BELOW = 0x12, 738 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 739 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 740 IPA_IRQ_UCP = 0x15, 741 /* The next bit is not present for IPA v4.5+ */ 742 IPA_IRQ_DCMP = 0x16, 743 IPA_IRQ_GSI_EE = 0x17, 744 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 745 IPA_IRQ_GSI_UC = 0x19, 746 /* The next bit is present for IPA v4.5+ */ 747 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 748 /* The next three bits are present for IPA v4.9+ */ 749 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 750 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 751 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 752 IPA_IRQ_COUNT, /* Last; not an id */ 753 }; 754 755 /* IPA_IRQ_UC register */ 756 #define UC_INTR_FMASK GENMASK(0, 0) 757 758 extern const struct ipa_regs ipa_regs_v3_1; 759 extern const struct ipa_regs ipa_regs_v3_5_1; 760 extern const struct ipa_regs ipa_regs_v4_2; 761 extern const struct ipa_regs ipa_regs_v4_5; 762 extern const struct ipa_regs ipa_regs_v4_9; 763 extern const struct ipa_regs ipa_regs_v4_11; 764 765 /* Return the field mask for a field in a register */ 766 static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) 767 { 768 if (!reg || WARN_ON(field_id >= reg->fcount)) 769 return 0; 770 771 return reg->fmask[field_id]; 772 } 773 774 /* Return the mask for a single-bit field in a register */ 775 static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) 776 { 777 u32 fmask = ipa_reg_fmask(reg, field_id); 778 779 WARN_ON(!is_power_of_2(fmask)); 780 781 return fmask; 782 } 783 784 /* Encode a value into the given field of a register */ 785 static inline u32 786 ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) 787 { 788 u32 fmask = ipa_reg_fmask(reg, field_id); 789 790 if (!fmask) 791 return 0; 792 793 val <<= __ffs(fmask); 794 if (WARN_ON(val & ~fmask)) 795 return 0; 796 797 return val; 798 } 799 800 /* Given a register value, decode (extract) the value in the given field */ 801 static inline u32 802 ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) 803 { 804 u32 fmask = ipa_reg_fmask(reg, field_id); 805 806 return fmask ? (val & fmask) >> __ffs(fmask) : 0; 807 } 808 809 /* Return the maximum value representable by the given field; always 2^n - 1 */ 810 static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) 811 { 812 u32 fmask = ipa_reg_fmask(reg, field_id); 813 814 return fmask ? fmask >> __ffs(fmask) : 0; 815 } 816 817 const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 818 819 /* Returns 0 for NULL reg; warning will have already been issued */ 820 static inline u32 ipa_reg_offset(const struct ipa_reg *reg) 821 { 822 return reg ? reg->offset : 0; 823 } 824 825 /* Returns 0 for NULL reg; warning will have already been issued */ 826 static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) 827 { 828 return reg ? reg->offset + n * reg->stride : 0; 829 } 830 831 int ipa_reg_init(struct ipa *ipa); 832 void ipa_reg_exit(struct ipa *ipa); 833 834 #endif /* _IPA_REG_H_ */ 835