1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 69 70 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 71 #define ENABLE_FMASK GENMASK(0, 0) 72 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 73 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 74 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 75 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 76 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 77 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 78 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 79 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 80 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 81 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 82 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 83 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 84 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 85 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 86 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 87 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 88 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 89 90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 91 #define RX_FMASK GENMASK(0, 0) 92 #define PROC_FMASK GENMASK(1, 1) 93 #define TX_WRAPPER_FMASK GENMASK(2, 2) 94 #define MISC_FMASK GENMASK(3, 3) 95 #define RAM_ARB_FMASK GENMASK(4, 4) 96 #define FTCH_HPS_FMASK GENMASK(5, 5) 97 #define FTCH_DPS_FMASK GENMASK(6, 6) 98 #define HPS_FMASK GENMASK(7, 7) 99 #define DPS_FMASK GENMASK(8, 8) 100 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 101 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 102 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 103 #define RSRC_MNGR_FMASK GENMASK(12, 12) 104 #define CTX_HANDLER_FMASK GENMASK(13, 13) 105 #define ACK_MNGR_FMASK GENMASK(14, 14) 106 #define D_DCPH_FMASK GENMASK(15, 15) 107 #define H_DCPH_FMASK GENMASK(16, 16) 108 #define DCMP_FMASK GENMASK(17, 17) 109 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 110 #define TX_0_FMASK GENMASK(19, 19) 111 #define TX_1_FMASK GENMASK(20, 20) 112 #define FNR_FMASK GENMASK(21, 21) 113 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 114 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 115 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 116 #define QMB_FMASK GENMASK(25, 25) 117 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 118 #define GSI_IF_FMASK GENMASK(27, 27) 119 #define GLOBAL_FMASK GENMASK(28, 28) 120 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 121 122 #define IPA_REG_ROUTE_OFFSET 0x00000048 123 #define ROUTE_DIS_FMASK GENMASK(0, 0) 124 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 125 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 126 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 127 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 128 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 129 130 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 131 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 132 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 133 134 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 135 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 136 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 137 138 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 139 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 140 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 141 /* The next two fields are present for IPA v4.0 and above */ 142 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 143 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 144 145 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 146 { 147 if (version == IPA_VERSION_3_5_1) 148 return 0x0000010c; 149 150 return 0x000000b4; 151 } 152 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 153 154 /* The next register is present for IPA v4.2 and above */ 155 #define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 156 #define IPV6_ROUTER_HASH_EN GENMASK(0, 0) 157 #define IPV6_FILTER_HASH_EN GENMASK(4, 4) 158 #define IPV4_ROUTER_HASH_EN GENMASK(8, 8) 159 #define IPV4_FILTER_HASH_EN GENMASK(12, 12) 160 161 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 162 { 163 if (version == IPA_VERSION_3_5_1) 164 return 0x0000090; 165 166 return 0x000014c; 167 } 168 169 #define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0) 170 #define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4) 171 #define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8) 172 #define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12) 173 174 #define IPA_REG_BCR_OFFSET 0x000001d0 175 #define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) 176 #define BCR_TX_NOT_USING_BRESP BIT(1) 177 #define BCR_SUSPEND_L2_IRQ BIT(3) 178 #define BCR_HOLB_DROP_L2_IRQ BIT(4) 179 #define BCR_DUAL_TX BIT(5) 180 181 /* Backward compatibility register value to use for each version */ 182 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 183 { 184 if (version == IPA_VERSION_3_5_1) 185 return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP | 186 BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; 187 188 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 189 return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ | 190 BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; 191 192 return 0x00000000; 193 } 194 195 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 196 197 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 198 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 199 200 /* The internal inactivity timer clock is used for the aggregation timer */ 201 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 202 203 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 204 #define AGGR_GRANULARITY GENMASK(8, 4) 205 /* Compute the value to use in the AGGR_GRANULARITY field representing the 206 * given number of microseconds. The value is one less than the number of 207 * timer ticks in the requested period. Zero not a valid granularity value. 208 */ 209 static inline u32 ipa_aggr_granularity_val(u32 usec) 210 { 211 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 212 } 213 214 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 215 /* The first three fields are present for IPA v3.5.1 only */ 216 #define TX0_PREFETCH_DISABLE GENMASK(0, 0) 217 #define TX1_PREFETCH_DISABLE GENMASK(1, 1) 218 #define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2) 219 /* The next fields are present for IPA v4.0 and above */ 220 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2) 221 #define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6) 222 #define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10) 223 #define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11) 224 #define PA_MASK_EN GENMASK(12, 12) 225 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13) 226 /* The last two fields are present for IPA v4.2 and above */ 227 #define SSPND_PA_NO_START_STATE GENMASK(18, 18) 228 #define SSPND_PA_NO_BQ_STATE GENMASK(19, 19) 229 230 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 231 #define BAM_MAX_PIPES_FMASK GENMASK(4, 0) 232 #define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 233 #define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 234 #define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) 235 236 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 237 { 238 if (version == IPA_VERSION_4_2) 239 return 0x00000240; 240 241 return 0x00000220; 242 } 243 244 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 245 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 246 247 /* # IPA source resource groups available based on version */ 248 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 249 { 250 switch (version) { 251 case IPA_VERSION_3_5_1: 252 case IPA_VERSION_4_0: 253 case IPA_VERSION_4_1: 254 return 4; 255 256 case IPA_VERSION_4_2: 257 return 1; 258 259 default: 260 return 0; 261 } 262 } 263 264 /* # IPA destination resource groups available based on version */ 265 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 266 { 267 switch (version) { 268 case IPA_VERSION_3_5_1: 269 return 3; 270 271 case IPA_VERSION_4_0: 272 case IPA_VERSION_4_1: 273 return 4; 274 275 case IPA_VERSION_4_2: 276 return 1; 277 278 default: 279 return 0; 280 } 281 } 282 283 /* Not all of the following are valid (depends on the count, above) */ 284 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 285 (0x00000400 + 0x0020 * (rt)) 286 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 287 (0x00000404 + 0x0020 * (rt)) 288 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 289 (0x00000408 + 0x0020 * (rt)) 290 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 291 (0x00000500 + 0x0020 * (rt)) 292 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 293 (0x00000504 + 0x0020 * (rt)) 294 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 295 (0x00000508 + 0x0020 * (rt)) 296 #define X_MIN_LIM_FMASK GENMASK(5, 0) 297 #define X_MAX_LIM_FMASK GENMASK(13, 8) 298 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 299 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 300 301 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 302 (0x00000800 + 0x0070 * (ep)) 303 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 304 #define ENDP_DELAY_FMASK GENMASK(1, 1) 305 306 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 307 (0x00000808 + 0x0070 * (ep)) 308 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 309 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 310 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 311 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 312 313 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 314 (0x00000810 + 0x0070 * (ep)) 315 #define HDR_LEN_FMASK GENMASK(5, 0) 316 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 317 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 318 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 319 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 320 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 321 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 322 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 323 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 324 325 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 326 (0x00000814 + 0x0070 * (ep)) 327 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 328 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 329 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 330 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 331 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 332 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 333 334 /* Valid only for RX (IPA producer) endpoints */ 335 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 336 (0x00000818 + 0x0070 * (rxep)) 337 338 /* Valid only for TX (IPA consumer) endpoints */ 339 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 340 (0x00000820 + 0x0070 * (txep)) 341 #define MODE_FMASK GENMASK(2, 0) 342 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 343 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 344 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 345 #define PAD_EN_FMASK GENMASK(29, 29) 346 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 347 348 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 349 (0x00000824 + 0x0070 * (ep)) 350 #define AGGR_EN_FMASK GENMASK(1, 0) 351 #define AGGR_TYPE_FMASK GENMASK(4, 2) 352 #define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) 353 #define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) 354 #define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) 355 #define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) 356 #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) 357 #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) 358 359 /* Valid only for RX (IPA producer) endpoints */ 360 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 361 (0x0000082c + 0x0070 * (rxep)) 362 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 363 364 /* Valid only for RX (IPA producer) endpoints */ 365 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 366 (0x00000830 + 0x0070 * (rxep)) 367 /* The next fields are present for IPA v4.2 only */ 368 #define BASE_VALUE_FMASK GENMASK(4, 0) 369 #define SCALE_FMASK GENMASK(12, 8) 370 371 /* Valid only for TX (IPA consumer) endpoints */ 372 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 373 (0x00000834 + 0x0070 * (txep)) 374 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 375 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 376 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 377 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 378 379 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 380 (0x00000838 + 0x0070 * (ep)) 381 /* Encoded value for RSRC_GRP endpoint register RSRC_GRP field */ 382 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 383 { 384 switch (version) { 385 case IPA_VERSION_4_2: 386 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 387 default: 388 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 389 } 390 } 391 392 /* Valid only for TX (IPA consumer) endpoints */ 393 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 394 (0x0000083c + 0x0070 * (txep)) 395 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) 396 #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) 397 #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) 398 #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) 399 400 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 401 (0x00000840 + 0x0070 * (ep)) 402 #define STATUS_EN_FMASK GENMASK(0, 0) 403 #define STATUS_ENDP_FMASK GENMASK(5, 1) 404 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 405 /* The next field is present for IPA v4.0 and above */ 406 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 407 408 /* "er" is either an endpoint ID (for filters) or a route ID (for routes) */ 409 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 410 (0x0000085c + 0x0070 * (er)) 411 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 412 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 413 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 414 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 415 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 416 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 417 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 418 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 419 420 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 421 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 422 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 423 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 424 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 425 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 426 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 427 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 428 429 #define IPA_REG_IRQ_STTS_OFFSET \ 430 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 431 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 432 (0x00003008 + 0x1000 * (ee)) 433 434 #define IPA_REG_IRQ_EN_OFFSET \ 435 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 436 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 437 (0x0000300c + 0x1000 * (ee)) 438 439 #define IPA_REG_IRQ_CLR_OFFSET \ 440 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 441 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 442 (0x00003010 + 0x1000 * (ee)) 443 444 #define IPA_REG_IRQ_UC_OFFSET \ 445 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 446 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 447 (0x0000301c + 0x1000 * (ee)) 448 449 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 450 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 451 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 452 (0x00003030 + 0x1000 * (ee)) 453 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 454 455 #define IPA_REG_SUSPEND_IRQ_EN_OFFSET \ 456 IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 457 #define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \ 458 (0x00003034 + 0x1000 * (ee)) 459 /* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */ 460 461 #define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \ 462 IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 463 #define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \ 464 (0x00003038 + 0x1000 * (ee)) 465 /* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */ 466 467 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 468 enum ipa_cs_offload_en { 469 IPA_CS_OFFLOAD_NONE = 0, 470 IPA_CS_OFFLOAD_UL = 1, 471 IPA_CS_OFFLOAD_DL = 2, 472 IPA_CS_RSVD 473 }; 474 475 /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ 476 enum ipa_aggr_en { 477 IPA_BYPASS_AGGR = 0, 478 IPA_ENABLE_AGGR = 1, 479 IPA_ENABLE_DEAGGR = 2, 480 }; 481 482 /** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ 483 enum ipa_aggr_type { 484 IPA_MBIM_16 = 0, 485 IPA_HDLC = 1, 486 IPA_TLP = 2, 487 IPA_RNDIS = 3, 488 IPA_GENERIC = 4, 489 IPA_COALESCE = 5, 490 IPA_QCMAP = 6, 491 }; 492 493 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 494 enum ipa_mode { 495 IPA_BASIC = 0, 496 IPA_ENABLE_FRAMING_HDLC = 1, 497 IPA_ENABLE_DEFRAMING_HDLC = 2, 498 IPA_DMA = 3, 499 }; 500 501 /** 502 * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N 503 * @IPA_SEQ_DMA_ONLY: only DMA is performed 504 * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: 505 * packet processing + no decipher + microcontroller (Ethernet Bridging) 506 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: 507 * second packet processing pass + no decipher + microcontroller 508 * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher 509 * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression 510 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: 511 * packet processing + no decipher + no uCP + HPS REP DMA parser 512 * @IPA_SEQ_INVALID: invalid sequencer type 513 * 514 * The values defined here are broken into 4-bit nibbles that are written 515 * into fields of the INIT_SEQ_N endpoint registers. 516 */ 517 enum ipa_seq_type { 518 IPA_SEQ_DMA_ONLY = 0x0000, 519 IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, 520 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, 521 IPA_SEQ_DMA_DEC = 0x0011, 522 IPA_SEQ_DMA_COMP_DECOMP = 0x0020, 523 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, 524 IPA_SEQ_INVALID = 0xffff, 525 }; 526 527 int ipa_reg_init(struct ipa *ipa); 528 void ipa_reg_exit(struct ipa *ipa); 529 530 #endif /* _IPA_REG_H_ */ 531