1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 /* The next field is not supported for IPA v4.1 */ 69 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 70 #define ENABLE_FMASK GENMASK(0, 0) 71 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 72 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 73 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 74 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 75 /* The remaining fields are not present for IPA v3.5.1 */ 76 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 77 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 78 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 79 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 80 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 81 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 82 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 83 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 84 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 85 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 86 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 87 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 88 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 89 90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 91 #define RX_FMASK GENMASK(0, 0) 92 #define PROC_FMASK GENMASK(1, 1) 93 #define TX_WRAPPER_FMASK GENMASK(2, 2) 94 #define MISC_FMASK GENMASK(3, 3) 95 #define RAM_ARB_FMASK GENMASK(4, 4) 96 #define FTCH_HPS_FMASK GENMASK(5, 5) 97 #define FTCH_DPS_FMASK GENMASK(6, 6) 98 #define HPS_FMASK GENMASK(7, 7) 99 #define DPS_FMASK GENMASK(8, 8) 100 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 101 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 102 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 103 #define RSRC_MNGR_FMASK GENMASK(12, 12) 104 #define CTX_HANDLER_FMASK GENMASK(13, 13) 105 #define ACK_MNGR_FMASK GENMASK(14, 14) 106 #define D_DCPH_FMASK GENMASK(15, 15) 107 #define H_DCPH_FMASK GENMASK(16, 16) 108 #define DCMP_FMASK GENMASK(17, 17) 109 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 110 #define TX_0_FMASK GENMASK(19, 19) 111 #define TX_1_FMASK GENMASK(20, 20) 112 #define FNR_FMASK GENMASK(21, 21) 113 /* The remaining fields are not present for IPA v3.5.1 */ 114 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 115 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 116 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 117 #define QMB_FMASK GENMASK(25, 25) 118 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 119 #define GSI_IF_FMASK GENMASK(27, 27) 120 #define GLOBAL_FMASK GENMASK(28, 28) 121 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 122 123 #define IPA_REG_ROUTE_OFFSET 0x00000048 124 #define ROUTE_DIS_FMASK GENMASK(0, 0) 125 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 126 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 127 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 128 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 129 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 130 131 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 132 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 133 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 134 135 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 136 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 137 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 138 139 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 140 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 141 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 142 /* The next two fields are not present for IPA v3.5.1 */ 143 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 144 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 145 146 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 147 { 148 if (version == IPA_VERSION_3_5_1) 149 return 0x000008c; 150 151 return 0x0000148; 152 } 153 154 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 155 { 156 if (version == IPA_VERSION_3_5_1) 157 return 0x0000090; 158 159 return 0x000014c; 160 } 161 162 /* The next four fields are used for the hash enable and flush registers */ 163 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 164 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 165 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 166 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 167 168 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 169 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 170 { 171 if (version == IPA_VERSION_3_5_1) 172 return 0x0000010c; 173 174 return 0x000000b4; 175 } 176 177 #define IPA_REG_BCR_OFFSET 0x000001d0 178 /* The next two fields are not present for IPA v4.2 */ 179 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 180 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 181 /* The next field is invalid for IPA v4.1 */ 182 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 183 /* The next two fields are not present for IPA v4.2 */ 184 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 185 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 186 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 187 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 188 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 189 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 190 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 191 192 /* Backward compatibility register value to use for each version */ 193 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 194 { 195 if (version == IPA_VERSION_3_5_1) 196 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 197 BCR_TX_NOT_USING_BRESP_FMASK | 198 BCR_SUSPEND_L2_IRQ_FMASK | 199 BCR_HOLB_DROP_L2_IRQ_FMASK | 200 BCR_DUAL_TX_FMASK; 201 202 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 203 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 204 BCR_SUSPEND_L2_IRQ_FMASK | 205 BCR_HOLB_DROP_L2_IRQ_FMASK | 206 BCR_DUAL_TX_FMASK; 207 208 return 0x00000000; 209 } 210 211 /* The value of the next register must be a multiple of 8 */ 212 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 213 214 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 215 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 216 217 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 218 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 219 220 /* The internal inactivity timer clock is used for the aggregation timer */ 221 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 222 223 /* Compute the value to use in the AGGR_GRANULARITY field representing the 224 * given number of microseconds. The value is one less than the number of 225 * timer ticks in the requested period. 0 not a valid granularity value. 226 */ 227 static inline u32 ipa_aggr_granularity_val(u32 usec) 228 { 229 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 230 } 231 232 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 233 /* The first three fields are present for IPA v3.5.1 only */ 234 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 235 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 236 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 237 /* The next six fields are present for IPA v4.0 and above */ 238 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 239 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 240 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 241 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 242 #define PA_MASK_EN_FMASK GENMASK(12, 12) 243 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 244 /* The next two fields are present for IPA v4.2 only */ 245 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 246 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 247 248 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 249 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 250 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 251 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 252 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 253 254 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 255 { 256 if (version == IPA_VERSION_4_2) 257 return 0x00000240; 258 259 return 0x00000220; 260 } 261 262 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 263 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 264 265 /* # IPA source resource groups available based on version */ 266 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 267 { 268 switch (version) { 269 case IPA_VERSION_3_5_1: 270 case IPA_VERSION_4_0: 271 case IPA_VERSION_4_1: 272 return 4; 273 274 case IPA_VERSION_4_2: 275 return 1; 276 277 default: 278 return 0; 279 } 280 } 281 282 /* # IPA destination resource groups available based on version */ 283 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 284 { 285 switch (version) { 286 case IPA_VERSION_3_5_1: 287 return 3; 288 289 case IPA_VERSION_4_0: 290 case IPA_VERSION_4_1: 291 return 4; 292 293 case IPA_VERSION_4_2: 294 return 1; 295 296 default: 297 return 0; 298 } 299 } 300 301 /* Not all of the following are valid (depends on the count, above) */ 302 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 303 (0x00000400 + 0x0020 * (rt)) 304 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 305 (0x00000404 + 0x0020 * (rt)) 306 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 307 (0x00000408 + 0x0020 * (rt)) 308 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 309 (0x00000500 + 0x0020 * (rt)) 310 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 311 (0x00000504 + 0x0020 * (rt)) 312 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 313 (0x00000508 + 0x0020 * (rt)) 314 /* The next four fields are used for all resource group registers */ 315 #define X_MIN_LIM_FMASK GENMASK(5, 0) 316 #define X_MAX_LIM_FMASK GENMASK(13, 8) 317 /* The next two fields are not always present (if resource count is odd) */ 318 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 319 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 320 321 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 322 (0x00000800 + 0x0070 * (ep)) 323 /* The next field should only used for IPA v3.5.1 */ 324 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 325 #define ENDP_DELAY_FMASK GENMASK(1, 1) 326 327 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 328 (0x00000808 + 0x0070 * (ep)) 329 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 330 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 331 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 332 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 333 334 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 335 enum ipa_cs_offload_en { 336 IPA_CS_OFFLOAD_NONE = 0x0, 337 IPA_CS_OFFLOAD_UL = 0x1, 338 IPA_CS_OFFLOAD_DL = 0x2, 339 }; 340 341 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 342 (0x00000810 + 0x0070 * (ep)) 343 #define HDR_LEN_FMASK GENMASK(5, 0) 344 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 345 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 346 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 347 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 348 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 349 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 350 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 351 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 352 353 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 354 (0x00000814 + 0x0070 * (ep)) 355 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 356 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 357 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 358 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 359 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 360 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 361 362 /* Valid only for RX (IPA producer) endpoints */ 363 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 364 (0x00000818 + 0x0070 * (rxep)) 365 366 /* Valid only for TX (IPA consumer) endpoints */ 367 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 368 (0x00000820 + 0x0070 * (txep)) 369 #define MODE_FMASK GENMASK(2, 0) 370 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 371 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 372 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 373 #define PAD_EN_FMASK GENMASK(29, 29) 374 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 375 376 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 377 enum ipa_mode { 378 IPA_BASIC = 0x0, 379 IPA_ENABLE_FRAMING_HDLC = 0x1, 380 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 381 IPA_DMA = 0x3, 382 }; 383 384 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 385 (0x00000824 + 0x0070 * (ep)) 386 #define AGGR_EN_FMASK GENMASK(1, 0) 387 #define AGGR_TYPE_FMASK GENMASK(4, 2) 388 #define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) 389 #define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) 390 #define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) 391 #define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) 392 #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) 393 #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) 394 395 /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ 396 enum ipa_aggr_en { 397 IPA_BYPASS_AGGR = 0x0, 398 IPA_ENABLE_AGGR = 0x1, 399 IPA_ENABLE_DEAGGR = 0x2, 400 }; 401 402 /** enum ipa_aggr_type - aggregation type field in ENDP_INIT_AGGR_N */ 403 enum ipa_aggr_type { 404 IPA_MBIM_16 = 0x0, 405 IPA_HDLC = 0x1, 406 IPA_TLP = 0x2, 407 IPA_RNDIS = 0x3, 408 IPA_GENERIC = 0x4, 409 IPA_COALESCE = 0x5, 410 IPA_QCMAP = 0x6, 411 }; 412 413 /* Valid only for RX (IPA producer) endpoints */ 414 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 415 (0x0000082c + 0x0070 * (rxep)) 416 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 417 418 /* Valid only for RX (IPA producer) endpoints */ 419 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 420 (0x00000830 + 0x0070 * (rxep)) 421 /* The next two fields are present for IPA v4.2 only */ 422 #define BASE_VALUE_FMASK GENMASK(4, 0) 423 #define SCALE_FMASK GENMASK(12, 8) 424 425 /* Valid only for TX (IPA consumer) endpoints */ 426 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 427 (0x00000834 + 0x0070 * (txep)) 428 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 429 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 430 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 431 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 432 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 433 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 434 435 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 436 (0x00000838 + 0x0070 * (ep)) 437 /* Encoded value for RSRC_GRP endpoint register RSRC_GRP field */ 438 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 439 { 440 switch (version) { 441 case IPA_VERSION_4_2: 442 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 443 default: 444 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 445 } 446 } 447 448 /* Valid only for TX (IPA consumer) endpoints */ 449 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 450 (0x0000083c + 0x0070 * (txep)) 451 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) 452 #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) 453 #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) 454 #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) 455 456 /** 457 * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N 458 * @IPA_SEQ_DMA_ONLY: only DMA is performed 459 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: 460 * second packet processing pass + no decipher + microcontroller 461 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: 462 * packet processing + no decipher + no uCP + HPS REP DMA parser 463 * @IPA_SEQ_INVALID: invalid sequencer type 464 * 465 * The values defined here are broken into 4-bit nibbles that are written 466 * into fields of the INIT_SEQ_N endpoint registers. 467 */ 468 enum ipa_seq_type { 469 IPA_SEQ_DMA_ONLY = 0x0000, 470 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, 471 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, 472 IPA_SEQ_INVALID = 0xffff, 473 }; 474 475 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 476 (0x00000840 + 0x0070 * (ep)) 477 #define STATUS_EN_FMASK GENMASK(0, 0) 478 #define STATUS_ENDP_FMASK GENMASK(5, 1) 479 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 480 /* The next field is not present for IPA v3.5.1 */ 481 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 482 483 /* The next register is only present for IPA versions that support hashing */ 484 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 485 (0x0000085c + 0x0070 * (er)) 486 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 487 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 488 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 489 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 490 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 491 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 492 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 493 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 494 495 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 496 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 497 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 498 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 499 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 500 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 501 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 502 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 503 504 #define IPA_REG_IRQ_STTS_OFFSET \ 505 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 506 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 507 (0x00003008 + 0x1000 * (ee)) 508 509 #define IPA_REG_IRQ_EN_OFFSET \ 510 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 511 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 512 (0x0000300c + 0x1000 * (ee)) 513 514 #define IPA_REG_IRQ_CLR_OFFSET \ 515 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 516 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 517 (0x00003010 + 0x1000 * (ee)) 518 /** 519 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 520 * @IPA_IRQ_UC_0: Microcontroller event interrupt 521 * @IPA_IRQ_UC_1: Microcontroller response interrupt 522 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 523 * 524 * IRQ types not described above are not currently used. 525 */ 526 enum ipa_irq_id { 527 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 528 /* Type (bit) 0x1 is not defined */ 529 IPA_IRQ_UC_0 = 0x2, 530 IPA_IRQ_UC_1 = 0x3, 531 IPA_IRQ_UC_2 = 0x4, 532 IPA_IRQ_UC_3 = 0x5, 533 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 534 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 535 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 536 IPA_IRQ_RX_ERR = 0x9, 537 IPA_IRQ_DEAGGR_ERR = 0xa, 538 IPA_IRQ_TX_ERR = 0xb, 539 IPA_IRQ_STEP_MODE = 0xc, 540 IPA_IRQ_PROC_ERR = 0xd, 541 IPA_IRQ_TX_SUSPEND = 0xe, 542 IPA_IRQ_TX_HOLB_DROP = 0xf, 543 IPA_IRQ_BAM_GSI_IDLE = 0x10, 544 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 545 IPA_IRQ_PIPE_RED_BELOW = 0x12, 546 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 547 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 548 IPA_IRQ_UCP = 0x15, 549 IPA_IRQ_DCMP = 0x16, 550 IPA_IRQ_GSI_EE = 0x17, 551 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 552 IPA_IRQ_GSI_UC = 0x19, 553 IPA_IRQ_COUNT, /* Last; not an id */ 554 }; 555 556 #define IPA_REG_IRQ_UC_OFFSET \ 557 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 558 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 559 (0x0000301c + 0x1000 * (ee)) 560 #define UC_INTR_FMASK GENMASK(0, 0) 561 562 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 563 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 564 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 565 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 566 (0x00003030 + 0x1000 * (ee)) 567 568 /* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ 569 #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ 570 IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) 571 #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ 572 (0x00003034 + 0x1000 * (ee)) 573 574 /* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ 575 #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ 576 IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) 577 #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ 578 (0x00003038 + 0x1000 * (ee)) 579 580 int ipa_reg_init(struct ipa *ipa); 581 void ipa_reg_exit(struct ipa *ipa); 582 583 #endif /* _IPA_REG_H_ */ 584