1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint id is computed by a macro 36 * that is supplied a parameter "ep". The "ep" value is assumed to be less 37 * than the maximum endpoint value for the current hardware, and that will 38 * not exceed IPA_ENDPOINT_MAX. 39 * 40 * The offset of registers related to filter and route tables is computed 41 * by a macro that is supplied a parameter "er". The "er" represents an 42 * endpoint ID for filters, or a route ID for routes. For filters, the 43 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 44 * because not all endpoints support filtering. For routes, the route ID 45 * must be less than IPA_ROUTE_MAX. 46 * 47 * The offset of registers related to resource types is computed by a macro 48 * that is supplied a parameter "rt". The "rt" represents a resource type, 49 * which is is a member of the ipa_resource_type_src enumerated type for 50 * source endpoint resources or the ipa_resource_type_dst enumerated type 51 * for destination endpoint resources. 52 * 53 * Some registers encode multiple fields within them. For these, each field 54 * has a symbol below defining a field mask that encodes both the position 55 * and width of the field within its register. 56 * 57 * In some cases, different versions of IPA hardware use different offset or 58 * field mask values. In such cases an inline_function(ipa) is used rather 59 * than a MACRO to define the offset or field mask to use. 60 * 61 * Finally, some registers hold bitmasks representing endpoints. In such 62 * cases the @available field in the @ipa structure defines the "full" set 63 * of valid bits for the register. 64 */ 65 66 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 #define ENABLE_FMASK GENMASK(0, 0) 70 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 71 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 72 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 73 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 74 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 75 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 76 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 77 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 78 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 79 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 80 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 81 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 82 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 83 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 84 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 85 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 86 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 87 88 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 89 #define RX_FMASK GENMASK(0, 0) 90 #define PROC_FMASK GENMASK(1, 1) 91 #define TX_WRAPPER_FMASK GENMASK(2, 2) 92 #define MISC_FMASK GENMASK(3, 3) 93 #define RAM_ARB_FMASK GENMASK(4, 4) 94 #define FTCH_HPS_FMASK GENMASK(5, 5) 95 #define FTCH_DPS_FMASK GENMASK(6, 6) 96 #define HPS_FMASK GENMASK(7, 7) 97 #define DPS_FMASK GENMASK(8, 8) 98 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 99 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 100 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 101 #define RSRC_MNGR_FMASK GENMASK(12, 12) 102 #define CTX_HANDLER_FMASK GENMASK(13, 13) 103 #define ACK_MNGR_FMASK GENMASK(14, 14) 104 #define D_DCPH_FMASK GENMASK(15, 15) 105 #define H_DCPH_FMASK GENMASK(16, 16) 106 #define DCMP_FMASK GENMASK(17, 17) 107 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 108 #define TX_0_FMASK GENMASK(19, 19) 109 #define TX_1_FMASK GENMASK(20, 20) 110 #define FNR_FMASK GENMASK(21, 21) 111 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 112 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 113 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 114 #define QMB_FMASK GENMASK(25, 25) 115 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 116 #define GSI_IF_FMASK GENMASK(27, 27) 117 #define GLOBAL_FMASK GENMASK(28, 28) 118 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 119 120 #define IPA_REG_ROUTE_OFFSET 0x00000048 121 #define ROUTE_DIS_FMASK GENMASK(0, 0) 122 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 123 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 124 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 125 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 126 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 127 128 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 129 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 130 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 131 132 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 133 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 134 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 135 136 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 137 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 138 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 139 /* The next two fields are present for IPA v4.0 and above */ 140 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 141 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 142 143 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 144 { 145 if (version == IPA_VERSION_3_5_1) 146 return 0x0000010c; 147 148 return 0x000000b4; 149 } 150 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 151 152 /* The next register is present for IPA v4.2 and above */ 153 #define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 154 #define IPV6_ROUTER_HASH_EN GENMASK(0, 0) 155 #define IPV6_FILTER_HASH_EN GENMASK(4, 4) 156 #define IPV4_ROUTER_HASH_EN GENMASK(8, 8) 157 #define IPV4_FILTER_HASH_EN GENMASK(12, 12) 158 159 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 160 { 161 if (version == IPA_VERSION_3_5_1) 162 return 0x0000090; 163 164 return 0x000014c; 165 } 166 167 #define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0) 168 #define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4) 169 #define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8) 170 #define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12) 171 172 #define IPA_REG_BCR_OFFSET 0x000001d0 173 #define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) 174 #define BCR_TX_NOT_USING_BRESP BIT(1) 175 #define BCR_SUSPEND_L2_IRQ BIT(3) 176 #define BCR_HOLB_DROP_L2_IRQ BIT(4) 177 #define BCR_DUAL_TX BIT(5) 178 179 /* Backward compatibility register value to use for each version */ 180 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 181 { 182 if (version == IPA_VERSION_3_5_1) 183 return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP | 184 BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; 185 186 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 187 return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ | 188 BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; 189 190 return 0x00000000; 191 } 192 193 194 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 195 196 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 197 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 198 199 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 200 #define AGGR_GRANULARITY GENMASK(8, 4) 201 /* Compute the value to use in the AGGR_GRANULARITY field representing 202 * the given number of microseconds (up to 1 millisecond). 203 * x = (32 * usec) / 1000 - 1 204 */ 205 static inline u32 ipa_aggr_granularity_val(u32 microseconds) 206 { 207 /* assert(microseconds >= 16); (?) */ 208 /* assert(microseconds <= 1015); */ 209 210 return DIV_ROUND_CLOSEST(32 * microseconds, 1000) - 1; 211 } 212 213 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 214 /* The first three fields are present for IPA v3.5.1 only */ 215 #define TX0_PREFETCH_DISABLE GENMASK(0, 0) 216 #define TX1_PREFETCH_DISABLE GENMASK(1, 1) 217 #define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2) 218 /* The next fields are present for IPA v4.0 and above */ 219 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2) 220 #define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6) 221 #define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10) 222 #define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11) 223 #define PA_MASK_EN GENMASK(12, 12) 224 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13) 225 /* The last two fields are present for IPA v4.2 and above */ 226 #define SSPND_PA_NO_START_STATE GENMASK(18, 18) 227 #define SSPND_PA_NO_BQ_STATE GENMASK(19, 19) 228 229 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 230 #define BAM_MAX_PIPES_FMASK GENMASK(4, 0) 231 #define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 232 #define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 233 #define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) 234 235 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 236 { 237 if (version == IPA_VERSION_4_2) 238 return 0x00000240; 239 240 return 0x00000220; 241 } 242 243 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 244 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 245 246 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 247 (0x00000400 + 0x0020 * (rt)) 248 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 249 (0x00000404 + 0x0020 * (rt)) 250 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 251 (0x00000408 + 0x0020 * (rt)) 252 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 253 (0x00000500 + 0x0020 * (rt)) 254 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 255 (0x00000504 + 0x0020 * (rt)) 256 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 257 (0x00000508 + 0x0020 * (rt)) 258 #define X_MIN_LIM_FMASK GENMASK(5, 0) 259 #define X_MAX_LIM_FMASK GENMASK(13, 8) 260 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 261 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 262 263 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 264 (0x00000800 + 0x0070 * (ep)) 265 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 266 #define ENDP_DELAY_FMASK GENMASK(1, 1) 267 268 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 269 (0x00000808 + 0x0070 * (ep)) 270 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 271 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 272 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 273 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 274 275 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 276 (0x00000810 + 0x0070 * (ep)) 277 #define HDR_LEN_FMASK GENMASK(5, 0) 278 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 279 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 280 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 281 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 282 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 283 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 284 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 285 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 286 287 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 288 (0x00000814 + 0x0070 * (ep)) 289 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 290 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 291 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 292 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 293 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 294 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 295 296 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(ep) \ 297 (0x00000818 + 0x0070 * (ep)) 298 299 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(ep) \ 300 (0x00000820 + 0x0070 * (ep)) 301 #define MODE_FMASK GENMASK(2, 0) 302 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 303 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 304 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 305 #define PAD_EN_FMASK GENMASK(29, 29) 306 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 307 308 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 309 (0x00000824 + 0x0070 * (ep)) 310 #define AGGR_EN_FMASK GENMASK(1, 0) 311 #define AGGR_TYPE_FMASK GENMASK(4, 2) 312 #define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) 313 #define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) 314 #define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) 315 #define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) 316 #define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) 317 #define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) 318 319 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(ep) \ 320 (0x0000082c + 0x0070 * (ep)) 321 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 322 323 /* The next register is valid only for RX (IPA producer) endpoints */ 324 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(ep) \ 325 (0x00000830 + 0x0070 * (ep)) 326 /* The next fields are present for IPA v4.2 only */ 327 #define BASE_VALUE_FMASK GENMASK(4, 0) 328 #define SCALE_FMASK GENMASK(12, 8) 329 330 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(ep) \ 331 (0x00000834 + 0x0070 * (ep)) 332 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 333 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 334 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 335 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 336 337 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 338 (0x00000838 + 0x0070 * (ep)) 339 #define RSRC_GRP_FMASK GENMASK(1, 0) 340 341 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(ep) \ 342 (0x0000083c + 0x0070 * (ep)) 343 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) 344 #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) 345 #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) 346 #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) 347 348 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 349 (0x00000840 + 0x0070 * (ep)) 350 #define STATUS_EN_FMASK GENMASK(0, 0) 351 #define STATUS_ENDP_FMASK GENMASK(5, 1) 352 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 353 /* The next field is present for IPA v4.0 and above */ 354 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 355 356 /* "er" is either an endpoint id (for filters) or a route id (for routes) */ 357 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 358 (0x0000085c + 0x0070 * (er)) 359 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 360 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 361 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 362 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 363 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 364 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 365 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 366 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 367 368 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 369 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 370 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 371 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 372 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 373 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 374 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 375 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 376 377 #define IPA_REG_IRQ_STTS_OFFSET \ 378 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 379 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 380 (0x00003008 + 0x1000 * (ee)) 381 382 #define IPA_REG_IRQ_EN_OFFSET \ 383 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 384 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 385 (0x0000300c + 0x1000 * (ee)) 386 387 #define IPA_REG_IRQ_CLR_OFFSET \ 388 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 389 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 390 (0x00003010 + 0x1000 * (ee)) 391 392 #define IPA_REG_IRQ_UC_OFFSET \ 393 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 394 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 395 (0x0000301c + 0x1000 * (ee)) 396 397 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 398 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 399 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 400 (0x00003030 + 0x1000 * (ee)) 401 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 402 403 #define IPA_REG_SUSPEND_IRQ_EN_OFFSET \ 404 IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 405 #define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \ 406 (0x00003034 + 0x1000 * (ee)) 407 /* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */ 408 409 #define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \ 410 IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 411 #define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \ 412 (0x00003038 + 0x1000 * (ee)) 413 /* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */ 414 415 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 416 enum ipa_cs_offload_en { 417 IPA_CS_OFFLOAD_NONE = 0, 418 IPA_CS_OFFLOAD_UL = 1, 419 IPA_CS_OFFLOAD_DL = 2, 420 IPA_CS_RSVD 421 }; 422 423 /** enum ipa_aggr_en - aggregation type field in ENDP_INIT_AGGR_N */ 424 enum ipa_aggr_en { 425 IPA_BYPASS_AGGR = 0, 426 IPA_ENABLE_AGGR = 1, 427 IPA_ENABLE_DEAGGR = 2, 428 }; 429 430 /** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ 431 enum ipa_aggr_type { 432 IPA_MBIM_16 = 0, 433 IPA_HDLC = 1, 434 IPA_TLP = 2, 435 IPA_RNDIS = 3, 436 IPA_GENERIC = 4, 437 IPA_COALESCE = 5, 438 IPA_QCMAP = 6, 439 }; 440 441 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 442 enum ipa_mode { 443 IPA_BASIC = 0, 444 IPA_ENABLE_FRAMING_HDLC = 1, 445 IPA_ENABLE_DEFRAMING_HDLC = 2, 446 IPA_DMA = 3, 447 }; 448 449 /** 450 * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N 451 * @IPA_SEQ_DMA_ONLY: only DMA is performed 452 * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: 453 * packet processing + no decipher + microcontroller (Ethernet Bridging) 454 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: 455 * second packet processing pass + no decipher + microcontroller 456 * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher 457 * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression 458 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: 459 * packet processing + no decipher + no uCP + HPS REP DMA parser 460 * @IPA_SEQ_INVALID: invalid sequencer type 461 * 462 * The values defined here are broken into 4-bit nibbles that are written 463 * into fields of the INIT_SEQ_N endpoint registers. 464 */ 465 enum ipa_seq_type { 466 IPA_SEQ_DMA_ONLY = 0x0000, 467 IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, 468 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, 469 IPA_SEQ_DMA_DEC = 0x0011, 470 IPA_SEQ_DMA_COMP_DECOMP = 0x0020, 471 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, 472 IPA_SEQ_INVALID = 0xffff, 473 }; 474 475 int ipa_reg_init(struct ipa *ipa); 476 void ipa_reg_exit(struct ipa *ipa); 477 478 #endif /* _IPA_REG_H_ */ 479