1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 14 struct ipa; 15 16 /** 17 * DOC: IPA Registers 18 * 19 * IPA registers are located within the "ipa-reg" address space defined by 20 * Device Tree. The offset of each register within that space is specified 21 * by symbols defined below. The address space is mapped to virtual memory 22 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 23 * 24 * Certain register types are duplicated for a number of instances of 25 * something. For example, each IPA endpoint has an set of registers 26 * defining its configuration. The offset to an endpoint's set of registers 27 * is computed based on an "base" offset, plus an endpoint's ID multiplied 28 * and a "stride" value for the register. For such registers, the offset is 29 * computed by a function-like macro that takes a parameter used in the 30 * computation. 31 * 32 * Some register offsets depend on execution environment. For these an "ee" 33 * parameter is supplied to the offset macro. The "ee" value is a member of 34 * the gsi_ee enumerated type. 35 * 36 * The offset of a register dependent on endpoint ID is computed by a macro 37 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 38 * "ep" parameter is valid for any endpoint; a register with a "txep" or 39 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 40 * "*ep" value is assumed to be less than the maximum valid endpoint ID 41 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 42 * 43 * The offset of registers related to filter and route tables is computed 44 * by a macro that is supplied a parameter "er". The "er" represents an 45 * endpoint ID for filters, or a route ID for routes. For filters, the 46 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 47 * because not all endpoints support filtering. For routes, the route ID 48 * must be less than IPA_ROUTE_MAX. 49 * 50 * The offset of registers related to resource types is computed by a macro 51 * that is supplied a parameter "rt". The "rt" represents a resource type, 52 * which is a member of the ipa_resource_type_src enumerated type for 53 * source endpoint resources or the ipa_resource_type_dst enumerated type 54 * for destination endpoint resources. 55 * 56 * Some registers encode multiple fields within them. For these, each field 57 * has a symbol below defining a field mask that encodes both the position 58 * and width of the field within its register. 59 * 60 * In some cases, different versions of IPA hardware use different offset or 61 * field mask values. In such cases an inline_function(ipa) is used rather 62 * than a MACRO to define the offset or field mask to use. 63 * 64 * Finally, some registers hold bitmasks representing endpoints. In such 65 * cases the @available field in the @ipa structure defines the "full" set 66 * of valid bits for the register. 67 */ 68 69 /* enum ipa_reg_id - IPA register IDs */ 70 enum ipa_reg_id { 71 COMP_CFG, 72 CLKON_CFG, 73 ROUTE, 74 SHARED_MEM_SIZE, 75 QSB_MAX_WRITES, 76 QSB_MAX_READS, 77 FILT_ROUT_HASH_EN, 78 FILT_ROUT_HASH_FLUSH, 79 STATE_AGGR_ACTIVE, 80 IPA_BCR, /* Not IPA v4.5+ */ 81 LOCAL_PKT_PROC_CNTXT, 82 AGGR_FORCE_CLOSE, 83 COUNTER_CFG, /* Not IPA v4.5+ */ 84 IPA_TX_CFG, /* IPA v3.5+ */ 85 FLAVOR_0, /* IPA v3.5+ */ 86 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 87 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 88 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 89 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 90 SRC_RSRC_GRP_01_RSRC_TYPE, 91 SRC_RSRC_GRP_23_RSRC_TYPE, 92 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 93 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 94 DST_RSRC_GRP_01_RSRC_TYPE, 95 DST_RSRC_GRP_23_RSRC_TYPE, 96 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 97 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 98 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 99 ENDP_INIT_CFG, 100 ENDP_INIT_NAT, /* TX only */ 101 ENDP_INIT_HDR, 102 ENDP_INIT_HDR_EXT, 103 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 104 ENDP_INIT_MODE, /* TX only */ 105 ENDP_INIT_AGGR, 106 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 107 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 108 ENDP_INIT_DEAGGR, /* TX only */ 109 ENDP_INIT_RSRC_GRP, 110 ENDP_INIT_SEQ, /* TX only */ 111 ENDP_STATUS, 112 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 113 /* The IRQ registers are only used for GSI_EE_AP */ 114 IPA_IRQ_STTS, 115 IPA_IRQ_EN, 116 IPA_IRQ_CLR, 117 IPA_IRQ_UC, 118 IRQ_SUSPEND_INFO, 119 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 120 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 121 IPA_REG_ID_COUNT, /* Last; not an ID */ 122 }; 123 124 /** 125 * struct ipa_reg - An IPA register descriptor 126 * @offset: Register offset relative to base of the "ipa-reg" memory 127 * @stride: Distance between two instances, if parameterized 128 * @fcount: Number of entries in the @fmask array 129 * @fmask: Array of mask values defining position and width of fields 130 * @name: Upper-case name of the IPA register 131 */ 132 struct ipa_reg { 133 u32 offset; 134 u32 stride; 135 u32 fcount; 136 const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ 137 const char *name; 138 }; 139 140 /* Helper macro for defining "simple" (non-parameterized) registers */ 141 #define IPA_REG(__NAME, __reg_id, __offset) \ 142 IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 143 144 /* Helper macro for defining parameterized registers, specifying stride */ 145 #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 146 static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 147 .name = #__NAME, \ 148 .offset = __offset, \ 149 .stride = __stride, \ 150 } 151 152 #define IPA_REG_FIELDS(__NAME, __name, __offset) \ 153 IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) 154 155 #define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ 156 static const struct ipa_reg ipa_reg_ ## __name = { \ 157 .name = #__NAME, \ 158 .offset = __offset, \ 159 .stride = __stride, \ 160 .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ 161 .fmask = ipa_reg_ ## __name ## _fmask, \ 162 } 163 164 /** 165 * struct ipa_regs - Description of registers supported by hardware 166 * @reg_count: Number of registers in the @reg[] array 167 * @reg: Array of register descriptors 168 */ 169 struct ipa_regs { 170 u32 reg_count; 171 const struct ipa_reg **reg; 172 }; 173 174 /* COMP_CFG register */ 175 enum ipa_reg_comp_cfg_field_id { 176 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 177 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 178 GSI_SNOC_BYPASS_DIS, 179 GEN_QMB_0_SNOC_BYPASS_DIS, 180 GEN_QMB_1_SNOC_BYPASS_DIS, 181 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 182 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 183 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 184 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 185 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 186 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 187 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 188 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 189 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 190 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 191 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 192 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 193 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 194 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 195 GENQMB_AOOOWR, /* IPA v4.9+ */ 196 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 197 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 198 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 199 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 200 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 201 }; 202 203 /* CLKON_CFG register */ 204 enum ipa_reg_clkon_cfg_field_id { 205 CLKON_RX, 206 CLKON_PROC, 207 TX_WRAPPER, 208 CLKON_MISC, 209 RAM_ARB, 210 FTCH_HPS, 211 FTCH_DPS, 212 CLKON_HPS, 213 CLKON_DPS, 214 RX_HPS_CMDQS, 215 HPS_DPS_CMDQS, 216 DPS_TX_CMDQS, 217 RSRC_MNGR, 218 CTX_HANDLER, 219 ACK_MNGR, 220 D_DCPH, 221 H_DCPH, 222 CLKON_DCMP, /* IPA v4.5+ */ 223 NTF_TX_CMDQS, /* IPA v3.5+ */ 224 CLKON_TX_0, /* IPA v3.5+ */ 225 CLKON_TX_1, /* IPA v3.5+ */ 226 CLKON_FNR, /* IPA v3.5.1+ */ 227 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 228 AGGR_WRAPPER, /* IPA v4.0+ */ 229 RAM_SLAVEWAY, /* IPA v4.0+ */ 230 CLKON_QMB, /* IPA v4.0+ */ 231 WEIGHT_ARB, /* IPA v4.0+ */ 232 GSI_IF, /* IPA v4.0+ */ 233 CLKON_GLOBAL, /* IPA v4.0+ */ 234 GLOBAL_2X_CLK, /* IPA v4.0+ */ 235 DPL_FIFO, /* IPA v4.5+ */ 236 DRBIP, /* IPA v4.7+ */ 237 }; 238 239 /* ROUTE register */ 240 enum ipa_reg_route_field_id { 241 ROUTE_DIS, 242 ROUTE_DEF_PIPE, 243 ROUTE_DEF_HDR_TABLE, 244 ROUTE_DEF_HDR_OFST, 245 ROUTE_FRAG_DEF_PIPE, 246 ROUTE_DEF_RETAIN_HDR, 247 }; 248 249 /* SHARED_MEM_SIZE register */ 250 enum ipa_reg_shared_mem_size_field_id { 251 MEM_SIZE, 252 MEM_BADDR, 253 }; 254 255 /* QSB_MAX_WRITES register */ 256 enum ipa_reg_qsb_max_writes_field_id { 257 GEN_QMB_0_MAX_WRITES, 258 GEN_QMB_1_MAX_WRITES, 259 }; 260 261 /* QSB_MAX_READS register */ 262 enum ipa_reg_qsb_max_reads_field_id { 263 GEN_QMB_0_MAX_READS, 264 GEN_QMB_1_MAX_READS, 265 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 266 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 267 }; 268 269 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 270 enum ipa_reg_rout_hash_field_id { 271 IPV6_ROUTER_HASH, 272 IPV6_FILTER_HASH, 273 IPV4_ROUTER_HASH, 274 IPV4_FILTER_HASH, 275 }; 276 277 /* BCR register */ 278 enum ipa_bcr_compat { 279 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 280 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 281 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 282 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 283 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 284 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 285 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 286 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 287 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 288 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 289 }; 290 291 /* LOCAL_PKT_PROC_CNTXT register */ 292 enum ipa_reg_local_pkt_proc_cntxt_field_id { 293 IPA_BASE_ADDR, 294 }; 295 296 /* COUNTER_CFG register */ 297 enum ipa_reg_counter_cfg_field_id { 298 EOT_COAL_GRANULARITY, /* Not v3.5+ */ 299 AGGR_GRANULARITY, 300 }; 301 302 /* IPA_TX_CFG register */ 303 enum ipa_reg_ipa_tx_cfg_field_id { 304 TX0_PREFETCH_DISABLE, /* Not v4.0+ */ 305 TX1_PREFETCH_DISABLE, /* Not v4.0+ */ 306 PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ 307 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ 308 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ 309 DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ 310 DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ 311 PA_MASK_EN, /* v4.0+ */ 312 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ 313 DUAL_TX_ENABLE, /* v4.5+ */ 314 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ 315 SSPND_PA_NO_BQ_STATE, /* v4.2 only */ 316 }; 317 318 /* FLAVOR_0 register */ 319 enum ipa_reg_flavor_0_field_id { 320 MAX_PIPES, 321 MAX_CONS_PIPES, 322 MAX_PROD_PIPES, 323 PROD_LOWEST, 324 }; 325 326 /* IDLE_INDICATION_CFG register */ 327 enum ipa_reg_idle_indication_cfg_field_id { 328 ENTER_IDLE_DEBOUNCE_THRESH, 329 CONST_NON_IDLE_ENABLE, 330 }; 331 332 /* QTIME_TIMESTAMP_CFG register */ 333 enum ipa_reg_qtime_timestamp_cfg_field_id { 334 DPL_TIMESTAMP_LSB, 335 DPL_TIMESTAMP_SEL, 336 TAG_TIMESTAMP_LSB, 337 NAT_TIMESTAMP_LSB, 338 }; 339 340 /* TIMERS_XO_CLK_DIV_CFG register */ 341 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 342 DIV_VALUE, 343 DIV_ENABLE, 344 }; 345 346 /* TIMERS_PULSE_GRAN_CFG register */ 347 enum ipa_reg_timers_pulse_gran_cfg_field_id { 348 PULSE_GRAN_0, 349 PULSE_GRAN_1, 350 PULSE_GRAN_2, 351 }; 352 353 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 354 enum ipa_pulse_gran { 355 IPA_GRAN_10_US = 0x0, 356 IPA_GRAN_20_US = 0x1, 357 IPA_GRAN_50_US = 0x2, 358 IPA_GRAN_100_US = 0x3, 359 IPA_GRAN_1_MS = 0x4, 360 IPA_GRAN_10_MS = 0x5, 361 IPA_GRAN_100_MS = 0x6, 362 IPA_GRAN_655350_US = 0x7, 363 }; 364 365 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 366 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 367 X_MIN_LIM, 368 X_MAX_LIM, 369 Y_MIN_LIM, 370 Y_MAX_LIM, 371 }; 372 373 /* ENDP_INIT_CTRL register */ 374 enum ipa_reg_endp_init_ctrl_field_id { 375 ENDP_SUSPEND, /* Not v4.0+ */ 376 ENDP_DELAY, /* Not v4.2+ */ 377 }; 378 379 /* ENDP_INIT_CFG register */ 380 enum ipa_reg_endp_init_cfg_field_id { 381 FRAG_OFFLOAD_EN, 382 CS_OFFLOAD_EN, 383 CS_METADATA_HDR_OFFSET, 384 CS_GEN_QMB_MASTER_SEL, 385 }; 386 387 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 388 enum ipa_cs_offload_en { 389 IPA_CS_OFFLOAD_NONE = 0x0, 390 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 391 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 392 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 393 }; 394 395 /* ENDP_INIT_NAT register */ 396 enum ipa_reg_endp_init_nat_field_id { 397 NAT_EN, 398 }; 399 400 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 401 enum ipa_nat_en { 402 IPA_NAT_BYPASS = 0x0, 403 IPA_NAT_SRC = 0x1, 404 IPA_NAT_DST = 0x2, 405 }; 406 407 /* ENDP_INIT_HDR register */ 408 enum ipa_reg_endp_init_hdr_field_id { 409 HDR_LEN, 410 HDR_OFST_METADATA_VALID, 411 HDR_OFST_METADATA, 412 HDR_ADDITIONAL_CONST_LEN, 413 HDR_OFST_PKT_SIZE_VALID, 414 HDR_OFST_PKT_SIZE, 415 HDR_A5_MUX, /* Not v4.9+ */ 416 HDR_LEN_INC_DEAGG_HDR, 417 HDR_METADATA_REG_VALID, /* Not v4.5+ */ 418 HDR_LEN_MSB, /* v4.5+ */ 419 HDR_OFST_METADATA_MSB, /* v4.5+ */ 420 }; 421 422 /* ENDP_INIT_HDR_EXT register */ 423 enum ipa_reg_endp_init_hdr_ext_field_id { 424 HDR_ENDIANNESS, 425 HDR_TOTAL_LEN_OR_PAD_VALID, 426 HDR_TOTAL_LEN_OR_PAD, 427 HDR_PAYLOAD_LEN_INC_PADDING, 428 HDR_TOTAL_LEN_OR_PAD_OFFSET, 429 HDR_PAD_TO_ALIGNMENT, 430 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ 431 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ 432 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ 433 }; 434 435 /* ENDP_INIT_MODE register */ 436 enum ipa_reg_endp_init_mode_field_id { 437 ENDP_MODE, 438 DCPH_ENABLE, /* v4.5+ */ 439 DEST_PIPE_INDEX, 440 BYTE_THRESHOLD, 441 PIPE_REPLICATION_EN, 442 PAD_EN, 443 HDR_FTCH_DISABLE, /* v4.5+ */ 444 DRBIP_ACL_ENABLE, /* v4.9+ */ 445 }; 446 447 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 448 enum ipa_mode { 449 IPA_BASIC = 0x0, 450 IPA_ENABLE_FRAMING_HDLC = 0x1, 451 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 452 IPA_DMA = 0x3, 453 }; 454 455 /* ENDP_INIT_AGGR register */ 456 enum ipa_reg_endp_init_aggr_field_id { 457 AGGR_EN, 458 AGGR_TYPE, 459 BYTE_LIMIT, 460 TIME_LIMIT, 461 PKT_LIMIT, 462 SW_EOF_ACTIVE, 463 FORCE_CLOSE, 464 HARD_BYTE_LIMIT_EN, 465 AGGR_GRAN_SEL, 466 }; 467 468 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 469 enum ipa_aggr_en { 470 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 471 IPA_ENABLE_AGGR /* RX */ = 0x1, 472 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 473 }; 474 475 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 476 enum ipa_aggr_type { 477 IPA_MBIM_16 = 0x0, 478 IPA_HDLC = 0x1, 479 IPA_TLP = 0x2, 480 IPA_RNDIS = 0x3, 481 IPA_GENERIC = 0x4, 482 IPA_COALESCE = 0x5, 483 IPA_QCMAP = 0x6, 484 }; 485 486 /* ENDP_INIT_HOL_BLOCK_EN register */ 487 enum ipa_reg_endp_init_hol_block_en_field_id { 488 HOL_BLOCK_EN, 489 }; 490 491 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 492 enum ipa_reg_endp_init_hol_block_timer_field_id { 493 TIMER_BASE_VALUE, /* Not v4.5+ */ 494 TIMER_SCALE, /* v4.2 only */ 495 TIMER_LIMIT, /* v4.5+ */ 496 TIMER_GRAN_SEL, /* v4.5+ */ 497 }; 498 499 /* ENDP_INIT_DEAGGR register */ 500 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 501 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 502 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 503 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 504 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 505 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 506 507 /* ENDP_INIT_RSRC_GRP register */ 508 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 509 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 510 { 511 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 512 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 513 514 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 515 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 516 517 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 518 } 519 520 /* ENDP_INIT_SEQ register */ 521 #define SEQ_TYPE_FMASK GENMASK(7, 0) 522 /* The next field must be zero for IPA v4.5+ */ 523 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 524 525 /** 526 * enum ipa_seq_type - HPS and DPS sequencer type 527 * @IPA_SEQ_DMA: Perform DMA only 528 * @IPA_SEQ_1_PASS: One pass through the pipeline 529 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 530 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 531 * @IPA_SEQ_2_PASS: Two passes through the pipeline 532 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 533 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 534 * 535 * The low-order byte of the sequencer type register defines the number of 536 * passes a packet takes through the IPA pipeline. The last pass through can 537 * optionally skip the microprocessor. Deciphering is optional for all types; 538 * if enabled, an additional mask (two bits) is added to the type value. 539 * 540 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 541 * supported (or meaningful). 542 */ 543 enum ipa_seq_type { 544 IPA_SEQ_DMA = 0x00, 545 IPA_SEQ_1_PASS = 0x02, 546 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 547 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 548 IPA_SEQ_2_PASS = 0x0a, 549 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 550 /* The next value can be ORed with the above */ 551 IPA_SEQ_DECIPHER = 0x11, 552 }; 553 554 /** 555 * enum ipa_seq_rep_type - replicated packet sequencer type 556 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 557 * 558 * This goes in the second byte of the endpoint sequencer type register. 559 * 560 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 561 * supported (or meaningful). 562 */ 563 enum ipa_seq_rep_type { 564 IPA_SEQ_REP_DMA_PARSER = 0x08, 565 }; 566 567 /* ENDP_STATUS register */ 568 #define STATUS_EN_FMASK GENMASK(0, 0) 569 #define STATUS_ENDP_FMASK GENMASK(5, 1) 570 /* The next field is not present for IPA v4.5+ */ 571 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 572 /* The next field is present for IPA v4.0+ */ 573 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 574 575 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 576 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 577 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 578 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 579 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 580 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 581 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 582 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 583 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 584 585 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 586 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 587 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 588 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 589 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 590 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 591 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 592 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 593 594 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 595 /** 596 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 597 * @IPA_IRQ_UC_0: Microcontroller event interrupt 598 * @IPA_IRQ_UC_1: Microcontroller response interrupt 599 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 600 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 601 * 602 * IRQ types not described above are not currently used. 603 * 604 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 605 * @IPA_IRQ_EOT_COAL: (Not currently used) 606 * @IPA_IRQ_UC_2: (Not currently used) 607 * @IPA_IRQ_UC_3: (Not currently used) 608 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 609 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 610 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 611 * @IPA_IRQ_RX_ERR: (Not currently used) 612 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 613 * @IPA_IRQ_TX_ERR: (Not currently used) 614 * @IPA_IRQ_STEP_MODE: (Not currently used) 615 * @IPA_IRQ_PROC_ERR: (Not currently used) 616 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 617 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 618 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 619 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 620 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 621 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 622 * @IPA_IRQ_UCP: (Not currently used) 623 * @IPA_IRQ_DCMP: (Not currently used) 624 * @IPA_IRQ_GSI_EE: (Not currently used) 625 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 626 * @IPA_IRQ_GSI_UC: (Not currently used) 627 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 628 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 629 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 630 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 631 */ 632 enum ipa_irq_id { 633 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 634 /* The next bit is not present for IPA v3.5+ */ 635 IPA_IRQ_EOT_COAL = 0x1, 636 IPA_IRQ_UC_0 = 0x2, 637 IPA_IRQ_UC_1 = 0x3, 638 IPA_IRQ_UC_2 = 0x4, 639 IPA_IRQ_UC_3 = 0x5, 640 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 641 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 642 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 643 IPA_IRQ_RX_ERR = 0x9, 644 IPA_IRQ_DEAGGR_ERR = 0xa, 645 IPA_IRQ_TX_ERR = 0xb, 646 IPA_IRQ_STEP_MODE = 0xc, 647 IPA_IRQ_PROC_ERR = 0xd, 648 IPA_IRQ_TX_SUSPEND = 0xe, 649 IPA_IRQ_TX_HOLB_DROP = 0xf, 650 IPA_IRQ_BAM_GSI_IDLE = 0x10, 651 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 652 IPA_IRQ_PIPE_RED_BELOW = 0x12, 653 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 654 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 655 IPA_IRQ_UCP = 0x15, 656 /* The next bit is not present for IPA v4.5+ */ 657 IPA_IRQ_DCMP = 0x16, 658 IPA_IRQ_GSI_EE = 0x17, 659 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 660 IPA_IRQ_GSI_UC = 0x19, 661 /* The next bit is present for IPA v4.5+ */ 662 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 663 /* The next three bits are present for IPA v4.9+ */ 664 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 665 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 666 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 667 IPA_IRQ_COUNT, /* Last; not an id */ 668 }; 669 670 /* IPA_IRQ_UC register */ 671 #define UC_INTR_FMASK GENMASK(0, 0) 672 673 extern const struct ipa_regs ipa_regs_v3_1; 674 extern const struct ipa_regs ipa_regs_v3_5_1; 675 extern const struct ipa_regs ipa_regs_v4_2; 676 extern const struct ipa_regs ipa_regs_v4_5; 677 extern const struct ipa_regs ipa_regs_v4_9; 678 extern const struct ipa_regs ipa_regs_v4_11; 679 680 /* Return the field mask for a field in a register */ 681 static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) 682 { 683 if (!reg || WARN_ON(field_id >= reg->fcount)) 684 return 0; 685 686 return reg->fmask[field_id]; 687 } 688 689 /* Return the mask for a single-bit field in a register */ 690 static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) 691 { 692 u32 fmask = ipa_reg_fmask(reg, field_id); 693 694 WARN_ON(!is_power_of_2(fmask)); 695 696 return fmask; 697 } 698 699 /* Encode a value into the given field of a register */ 700 static inline u32 701 ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) 702 { 703 u32 fmask = ipa_reg_fmask(reg, field_id); 704 705 if (!fmask) 706 return 0; 707 708 val <<= __ffs(fmask); 709 if (WARN_ON(val & ~fmask)) 710 return 0; 711 712 return val; 713 } 714 715 /* Given a register value, decode (extract) the value in the given field */ 716 static inline u32 717 ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) 718 { 719 u32 fmask = ipa_reg_fmask(reg, field_id); 720 721 return fmask ? (val & fmask) >> __ffs(fmask) : 0; 722 } 723 724 /* Return the maximum value representable by the given field; always 2^n - 1 */ 725 static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) 726 { 727 u32 fmask = ipa_reg_fmask(reg, field_id); 728 729 return fmask ? fmask >> __ffs(fmask) : 0; 730 } 731 732 const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 733 734 /* Returns 0 for NULL reg; warning will have already been issued */ 735 static inline u32 ipa_reg_offset(const struct ipa_reg *reg) 736 { 737 return reg ? reg->offset : 0; 738 } 739 740 /* Returns 0 for NULL reg; warning will have already been issued */ 741 static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) 742 { 743 return reg ? reg->offset + n * reg->stride : 0; 744 } 745 746 int ipa_reg_init(struct ipa *ipa); 747 void ipa_reg_exit(struct ipa *ipa); 748 749 #endif /* _IPA_REG_H_ */ 750