1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2022 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 14 struct ipa; 15 16 /** 17 * DOC: IPA Registers 18 * 19 * IPA registers are located within the "ipa-reg" address space defined by 20 * Device Tree. Each register has a specified offset within that space, 21 * which is mapped into virtual memory space in ipa_mem_init(). Each 22 * has a unique identifer, taken from the ipa_reg_id enumerated type. 23 * All IPA registers are 32 bits wide. 24 * 25 * Certain "parameterized" register types are duplicated for a number of 26 * instances of something. For example, each IPA endpoint has an set of 27 * registers defining its configuration. The offset to an endpoint's set 28 * of registers is computed based on an "base" offset, plus an endpoint's 29 * ID multiplied and a "stride" value for the register. Similarly, some 30 * registers have an offset that depends on execution environment. In 31 * this case, the stride is multiplied by a member of the gsi_ee_id 32 * enumerated type. 33 * 34 * Each version of IPA implements an array of ipa_reg structures indexed 35 * by register ID. Each entry in the array specifies the base offset and 36 * (for parameterized registers) a non-zero stride value. Not all versions 37 * of IPA define all registers. The offset for a register is returned by 38 * ipa_reg_offset() when the register's ipa_reg structure is supplied; 39 * zero is returned for an undefined register (this should never happen). 40 * 41 * Some registers encode multiple fields within them. Each field in 42 * such a register has a unique identifier (from an enumerated type). 43 * The position and width of the fields in a register are defined by 44 * an array of field masks, indexed by field ID. Two functions are 45 * used to access register fields; both take an ipa_reg structure as 46 * argument. To encode a value to be represented in a register field, 47 * the value and field ID are passed to ipa_reg_encode(). To extract 48 * a value encoded in a register field, the field ID is passed to 49 * ipa_reg_decode(). In addition, for single-bit fields, ipa_reg_bit() 50 * can be used to either encode the bit value, or to generate a mask 51 * used to extract the bit value. 52 */ 53 54 /* enum ipa_reg_id - IPA register IDs */ 55 enum ipa_reg_id { 56 COMP_CFG, 57 CLKON_CFG, 58 ROUTE, 59 SHARED_MEM_SIZE, 60 QSB_MAX_WRITES, 61 QSB_MAX_READS, 62 FILT_ROUT_HASH_EN, 63 FILT_ROUT_HASH_FLUSH, 64 STATE_AGGR_ACTIVE, 65 IPA_BCR, /* Not IPA v4.5+ */ 66 LOCAL_PKT_PROC_CNTXT, 67 AGGR_FORCE_CLOSE, 68 COUNTER_CFG, /* Not IPA v4.5+ */ 69 IPA_TX_CFG, /* IPA v3.5+ */ 70 FLAVOR_0, /* IPA v3.5+ */ 71 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 72 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 73 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 74 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 75 SRC_RSRC_GRP_01_RSRC_TYPE, 76 SRC_RSRC_GRP_23_RSRC_TYPE, 77 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 78 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 79 DST_RSRC_GRP_01_RSRC_TYPE, 80 DST_RSRC_GRP_23_RSRC_TYPE, 81 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 82 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 83 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 84 ENDP_INIT_CFG, 85 ENDP_INIT_NAT, /* TX only */ 86 ENDP_INIT_HDR, 87 ENDP_INIT_HDR_EXT, 88 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 89 ENDP_INIT_MODE, /* TX only */ 90 ENDP_INIT_AGGR, 91 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 92 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 93 ENDP_INIT_DEAGGR, /* TX only */ 94 ENDP_INIT_RSRC_GRP, 95 ENDP_INIT_SEQ, /* TX only */ 96 ENDP_STATUS, 97 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 98 /* The IRQ registers are only used for GSI_EE_AP */ 99 IPA_IRQ_STTS, 100 IPA_IRQ_EN, 101 IPA_IRQ_CLR, 102 IPA_IRQ_UC, 103 IRQ_SUSPEND_INFO, 104 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 105 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 106 IPA_REG_ID_COUNT, /* Last; not an ID */ 107 }; 108 109 /** 110 * struct ipa_reg - An IPA register descriptor 111 * @offset: Register offset relative to base of the "ipa-reg" memory 112 * @stride: Distance between two instances, if parameterized 113 * @fcount: Number of entries in the @fmask array 114 * @fmask: Array of mask values defining position and width of fields 115 * @name: Upper-case name of the IPA register 116 */ 117 struct ipa_reg { 118 u32 offset; 119 u32 stride; 120 u32 fcount; 121 const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ 122 const char *name; 123 }; 124 125 /* Helper macro for defining "simple" (non-parameterized) registers */ 126 #define IPA_REG(__NAME, __reg_id, __offset) \ 127 IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 128 129 /* Helper macro for defining parameterized registers, specifying stride */ 130 #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 131 static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 132 .name = #__NAME, \ 133 .offset = __offset, \ 134 .stride = __stride, \ 135 } 136 137 #define IPA_REG_FIELDS(__NAME, __name, __offset) \ 138 IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) 139 140 #define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ 141 static const struct ipa_reg ipa_reg_ ## __name = { \ 142 .name = #__NAME, \ 143 .offset = __offset, \ 144 .stride = __stride, \ 145 .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ 146 .fmask = ipa_reg_ ## __name ## _fmask, \ 147 } 148 149 /** 150 * struct ipa_regs - Description of registers supported by hardware 151 * @reg_count: Number of registers in the @reg[] array 152 * @reg: Array of register descriptors 153 */ 154 struct ipa_regs { 155 u32 reg_count; 156 const struct ipa_reg **reg; 157 }; 158 159 /* COMP_CFG register */ 160 enum ipa_reg_comp_cfg_field_id { 161 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 162 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 163 GSI_SNOC_BYPASS_DIS, 164 GEN_QMB_0_SNOC_BYPASS_DIS, 165 GEN_QMB_1_SNOC_BYPASS_DIS, 166 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 167 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 168 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 169 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 170 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 171 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 172 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 173 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 174 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 175 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 176 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 177 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 178 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 179 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 180 GENQMB_AOOOWR, /* IPA v4.9+ */ 181 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 182 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 183 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 184 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 185 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 186 }; 187 188 /* CLKON_CFG register */ 189 enum ipa_reg_clkon_cfg_field_id { 190 CLKON_RX, 191 CLKON_PROC, 192 TX_WRAPPER, 193 CLKON_MISC, 194 RAM_ARB, 195 FTCH_HPS, 196 FTCH_DPS, 197 CLKON_HPS, 198 CLKON_DPS, 199 RX_HPS_CMDQS, 200 HPS_DPS_CMDQS, 201 DPS_TX_CMDQS, 202 RSRC_MNGR, 203 CTX_HANDLER, 204 ACK_MNGR, 205 D_DCPH, 206 H_DCPH, 207 CLKON_DCMP, /* IPA v4.5+ */ 208 NTF_TX_CMDQS, /* IPA v3.5+ */ 209 CLKON_TX_0, /* IPA v3.5+ */ 210 CLKON_TX_1, /* IPA v3.5+ */ 211 CLKON_FNR, /* IPA v3.5.1+ */ 212 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 213 AGGR_WRAPPER, /* IPA v4.0+ */ 214 RAM_SLAVEWAY, /* IPA v4.0+ */ 215 CLKON_QMB, /* IPA v4.0+ */ 216 WEIGHT_ARB, /* IPA v4.0+ */ 217 GSI_IF, /* IPA v4.0+ */ 218 CLKON_GLOBAL, /* IPA v4.0+ */ 219 GLOBAL_2X_CLK, /* IPA v4.0+ */ 220 DPL_FIFO, /* IPA v4.5+ */ 221 DRBIP, /* IPA v4.7+ */ 222 }; 223 224 /* ROUTE register */ 225 enum ipa_reg_route_field_id { 226 ROUTE_DIS, 227 ROUTE_DEF_PIPE, 228 ROUTE_DEF_HDR_TABLE, 229 ROUTE_DEF_HDR_OFST, 230 ROUTE_FRAG_DEF_PIPE, 231 ROUTE_DEF_RETAIN_HDR, 232 }; 233 234 /* SHARED_MEM_SIZE register */ 235 enum ipa_reg_shared_mem_size_field_id { 236 MEM_SIZE, 237 MEM_BADDR, 238 }; 239 240 /* QSB_MAX_WRITES register */ 241 enum ipa_reg_qsb_max_writes_field_id { 242 GEN_QMB_0_MAX_WRITES, 243 GEN_QMB_1_MAX_WRITES, 244 }; 245 246 /* QSB_MAX_READS register */ 247 enum ipa_reg_qsb_max_reads_field_id { 248 GEN_QMB_0_MAX_READS, 249 GEN_QMB_1_MAX_READS, 250 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 251 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 252 }; 253 254 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 255 enum ipa_reg_rout_hash_field_id { 256 IPV6_ROUTER_HASH, 257 IPV6_FILTER_HASH, 258 IPV4_ROUTER_HASH, 259 IPV4_FILTER_HASH, 260 }; 261 262 /* BCR register */ 263 enum ipa_bcr_compat { 264 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 265 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 266 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 267 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 268 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 269 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 270 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 271 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 272 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 273 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 274 }; 275 276 /* LOCAL_PKT_PROC_CNTXT register */ 277 enum ipa_reg_local_pkt_proc_cntxt_field_id { 278 IPA_BASE_ADDR, 279 }; 280 281 /* COUNTER_CFG register */ 282 enum ipa_reg_counter_cfg_field_id { 283 EOT_COAL_GRANULARITY, /* Not v3.5+ */ 284 AGGR_GRANULARITY, 285 }; 286 287 /* IPA_TX_CFG register */ 288 enum ipa_reg_ipa_tx_cfg_field_id { 289 TX0_PREFETCH_DISABLE, /* Not v4.0+ */ 290 TX1_PREFETCH_DISABLE, /* Not v4.0+ */ 291 PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ 292 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ 293 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ 294 DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ 295 DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ 296 PA_MASK_EN, /* v4.0+ */ 297 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ 298 DUAL_TX_ENABLE, /* v4.5+ */ 299 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ 300 SSPND_PA_NO_BQ_STATE, /* v4.2 only */ 301 }; 302 303 /* FLAVOR_0 register */ 304 enum ipa_reg_flavor_0_field_id { 305 MAX_PIPES, 306 MAX_CONS_PIPES, 307 MAX_PROD_PIPES, 308 PROD_LOWEST, 309 }; 310 311 /* IDLE_INDICATION_CFG register */ 312 enum ipa_reg_idle_indication_cfg_field_id { 313 ENTER_IDLE_DEBOUNCE_THRESH, 314 CONST_NON_IDLE_ENABLE, 315 }; 316 317 /* QTIME_TIMESTAMP_CFG register */ 318 enum ipa_reg_qtime_timestamp_cfg_field_id { 319 DPL_TIMESTAMP_LSB, 320 DPL_TIMESTAMP_SEL, 321 TAG_TIMESTAMP_LSB, 322 NAT_TIMESTAMP_LSB, 323 }; 324 325 /* TIMERS_XO_CLK_DIV_CFG register */ 326 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 327 DIV_VALUE, 328 DIV_ENABLE, 329 }; 330 331 /* TIMERS_PULSE_GRAN_CFG register */ 332 enum ipa_reg_timers_pulse_gran_cfg_field_id { 333 PULSE_GRAN_0, 334 PULSE_GRAN_1, 335 PULSE_GRAN_2, 336 }; 337 338 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 339 enum ipa_pulse_gran { 340 IPA_GRAN_10_US = 0x0, 341 IPA_GRAN_20_US = 0x1, 342 IPA_GRAN_50_US = 0x2, 343 IPA_GRAN_100_US = 0x3, 344 IPA_GRAN_1_MS = 0x4, 345 IPA_GRAN_10_MS = 0x5, 346 IPA_GRAN_100_MS = 0x6, 347 IPA_GRAN_655350_US = 0x7, 348 }; 349 350 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 351 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 352 X_MIN_LIM, 353 X_MAX_LIM, 354 Y_MIN_LIM, 355 Y_MAX_LIM, 356 }; 357 358 /* ENDP_INIT_CTRL register */ 359 enum ipa_reg_endp_init_ctrl_field_id { 360 ENDP_SUSPEND, /* Not v4.0+ */ 361 ENDP_DELAY, /* Not v4.2+ */ 362 }; 363 364 /* ENDP_INIT_CFG register */ 365 enum ipa_reg_endp_init_cfg_field_id { 366 FRAG_OFFLOAD_EN, 367 CS_OFFLOAD_EN, 368 CS_METADATA_HDR_OFFSET, 369 CS_GEN_QMB_MASTER_SEL, 370 }; 371 372 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 373 enum ipa_cs_offload_en { 374 IPA_CS_OFFLOAD_NONE = 0x0, 375 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 376 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 377 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 378 }; 379 380 /* ENDP_INIT_NAT register */ 381 enum ipa_reg_endp_init_nat_field_id { 382 NAT_EN, 383 }; 384 385 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 386 enum ipa_nat_en { 387 IPA_NAT_BYPASS = 0x0, 388 IPA_NAT_SRC = 0x1, 389 IPA_NAT_DST = 0x2, 390 }; 391 392 /* ENDP_INIT_HDR register */ 393 enum ipa_reg_endp_init_hdr_field_id { 394 HDR_LEN, 395 HDR_OFST_METADATA_VALID, 396 HDR_OFST_METADATA, 397 HDR_ADDITIONAL_CONST_LEN, 398 HDR_OFST_PKT_SIZE_VALID, 399 HDR_OFST_PKT_SIZE, 400 HDR_A5_MUX, /* Not v4.9+ */ 401 HDR_LEN_INC_DEAGG_HDR, 402 HDR_METADATA_REG_VALID, /* Not v4.5+ */ 403 HDR_LEN_MSB, /* v4.5+ */ 404 HDR_OFST_METADATA_MSB, /* v4.5+ */ 405 }; 406 407 /* ENDP_INIT_HDR_EXT register */ 408 enum ipa_reg_endp_init_hdr_ext_field_id { 409 HDR_ENDIANNESS, 410 HDR_TOTAL_LEN_OR_PAD_VALID, 411 HDR_TOTAL_LEN_OR_PAD, 412 HDR_PAYLOAD_LEN_INC_PADDING, 413 HDR_TOTAL_LEN_OR_PAD_OFFSET, 414 HDR_PAD_TO_ALIGNMENT, 415 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ 416 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ 417 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ 418 }; 419 420 /* ENDP_INIT_MODE register */ 421 enum ipa_reg_endp_init_mode_field_id { 422 ENDP_MODE, 423 DCPH_ENABLE, /* v4.5+ */ 424 DEST_PIPE_INDEX, 425 BYTE_THRESHOLD, 426 PIPE_REPLICATION_EN, 427 PAD_EN, 428 HDR_FTCH_DISABLE, /* v4.5+ */ 429 DRBIP_ACL_ENABLE, /* v4.9+ */ 430 }; 431 432 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 433 enum ipa_mode { 434 IPA_BASIC = 0x0, 435 IPA_ENABLE_FRAMING_HDLC = 0x1, 436 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 437 IPA_DMA = 0x3, 438 }; 439 440 /* ENDP_INIT_AGGR register */ 441 enum ipa_reg_endp_init_aggr_field_id { 442 AGGR_EN, 443 AGGR_TYPE, 444 BYTE_LIMIT, 445 TIME_LIMIT, 446 PKT_LIMIT, 447 SW_EOF_ACTIVE, 448 FORCE_CLOSE, 449 HARD_BYTE_LIMIT_EN, 450 AGGR_GRAN_SEL, 451 }; 452 453 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 454 enum ipa_aggr_en { 455 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 456 IPA_ENABLE_AGGR /* RX */ = 0x1, 457 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 458 }; 459 460 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 461 enum ipa_aggr_type { 462 IPA_MBIM_16 = 0x0, 463 IPA_HDLC = 0x1, 464 IPA_TLP = 0x2, 465 IPA_RNDIS = 0x3, 466 IPA_GENERIC = 0x4, 467 IPA_COALESCE = 0x5, 468 IPA_QCMAP = 0x6, 469 }; 470 471 /* ENDP_INIT_HOL_BLOCK_EN register */ 472 enum ipa_reg_endp_init_hol_block_en_field_id { 473 HOL_BLOCK_EN, 474 }; 475 476 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 477 enum ipa_reg_endp_init_hol_block_timer_field_id { 478 TIMER_BASE_VALUE, /* Not v4.5+ */ 479 TIMER_SCALE, /* v4.2 only */ 480 TIMER_LIMIT, /* v4.5+ */ 481 TIMER_GRAN_SEL, /* v4.5+ */ 482 }; 483 484 /* ENDP_INIT_DEAGGR register */ 485 enum ipa_reg_endp_deaggr_field_id { 486 DEAGGR_HDR_LEN, 487 SYSPIPE_ERR_DETECTION, 488 PACKET_OFFSET_VALID, 489 PACKET_OFFSET_LOCATION, 490 IGNORE_MIN_PKT_ERR, 491 MAX_PACKET_LEN, 492 }; 493 494 /* ENDP_INIT_RSRC_GRP register */ 495 enum ipa_reg_endp_init_rsrc_grp_field_id { 496 ENDP_RSRC_GRP, 497 }; 498 499 /* ENDP_INIT_SEQ register */ 500 enum ipa_reg_endp_init_seq_field_id { 501 SEQ_TYPE, 502 SEQ_REP_TYPE, /* Not v4.5+ */ 503 }; 504 505 /** 506 * enum ipa_seq_type - HPS and DPS sequencer type 507 * @IPA_SEQ_DMA: Perform DMA only 508 * @IPA_SEQ_1_PASS: One pass through the pipeline 509 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 510 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 511 * @IPA_SEQ_2_PASS: Two passes through the pipeline 512 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 513 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 514 * 515 * The low-order byte of the sequencer type register defines the number of 516 * passes a packet takes through the IPA pipeline. The last pass through can 517 * optionally skip the microprocessor. Deciphering is optional for all types; 518 * if enabled, an additional mask (two bits) is added to the type value. 519 * 520 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 521 * supported (or meaningful). 522 */ 523 enum ipa_seq_type { 524 IPA_SEQ_DMA = 0x00, 525 IPA_SEQ_1_PASS = 0x02, 526 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 527 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 528 IPA_SEQ_2_PASS = 0x0a, 529 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 530 /* The next value can be ORed with the above */ 531 IPA_SEQ_DECIPHER = 0x11, 532 }; 533 534 /** 535 * enum ipa_seq_rep_type - replicated packet sequencer type 536 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 537 * 538 * This goes in the second byte of the endpoint sequencer type register. 539 * 540 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 541 * supported (or meaningful). 542 */ 543 enum ipa_seq_rep_type { 544 IPA_SEQ_REP_DMA_PARSER = 0x08, 545 }; 546 547 /* ENDP_STATUS register */ 548 enum ipa_reg_endp_status_field_id { 549 STATUS_EN, 550 STATUS_ENDP, 551 STATUS_LOCATION, /* Not v4.5+ */ 552 STATUS_PKT_SUPPRESS, /* v4.0+ */ 553 }; 554 555 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 556 enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 557 FILTER_HASH_MSK_SRC_ID, 558 FILTER_HASH_MSK_SRC_IP, 559 FILTER_HASH_MSK_DST_IP, 560 FILTER_HASH_MSK_SRC_PORT, 561 FILTER_HASH_MSK_DST_PORT, 562 FILTER_HASH_MSK_PROTOCOL, 563 FILTER_HASH_MSK_METADATA, 564 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 565 566 ROUTER_HASH_MSK_SRC_ID, 567 ROUTER_HASH_MSK_SRC_IP, 568 ROUTER_HASH_MSK_DST_IP, 569 ROUTER_HASH_MSK_SRC_PORT, 570 ROUTER_HASH_MSK_DST_PORT, 571 ROUTER_HASH_MSK_PROTOCOL, 572 ROUTER_HASH_MSK_METADATA, 573 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 574 }; 575 576 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 577 /** 578 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 579 * @IPA_IRQ_UC_0: Microcontroller event interrupt 580 * @IPA_IRQ_UC_1: Microcontroller response interrupt 581 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 582 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 583 * 584 * IRQ types not described above are not currently used. 585 * 586 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 587 * @IPA_IRQ_EOT_COAL: (Not currently used) 588 * @IPA_IRQ_UC_2: (Not currently used) 589 * @IPA_IRQ_UC_3: (Not currently used) 590 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 591 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 592 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 593 * @IPA_IRQ_RX_ERR: (Not currently used) 594 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 595 * @IPA_IRQ_TX_ERR: (Not currently used) 596 * @IPA_IRQ_STEP_MODE: (Not currently used) 597 * @IPA_IRQ_PROC_ERR: (Not currently used) 598 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 599 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 600 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 601 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 602 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 603 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 604 * @IPA_IRQ_UCP: (Not currently used) 605 * @IPA_IRQ_DCMP: (Not currently used) 606 * @IPA_IRQ_GSI_EE: (Not currently used) 607 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 608 * @IPA_IRQ_GSI_UC: (Not currently used) 609 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 610 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 611 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 612 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 613 */ 614 enum ipa_irq_id { 615 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 616 /* The next bit is not present for IPA v3.5+ */ 617 IPA_IRQ_EOT_COAL = 0x1, 618 IPA_IRQ_UC_0 = 0x2, 619 IPA_IRQ_UC_1 = 0x3, 620 IPA_IRQ_UC_2 = 0x4, 621 IPA_IRQ_UC_3 = 0x5, 622 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 623 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 624 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 625 IPA_IRQ_RX_ERR = 0x9, 626 IPA_IRQ_DEAGGR_ERR = 0xa, 627 IPA_IRQ_TX_ERR = 0xb, 628 IPA_IRQ_STEP_MODE = 0xc, 629 IPA_IRQ_PROC_ERR = 0xd, 630 IPA_IRQ_TX_SUSPEND = 0xe, 631 IPA_IRQ_TX_HOLB_DROP = 0xf, 632 IPA_IRQ_BAM_GSI_IDLE = 0x10, 633 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 634 IPA_IRQ_PIPE_RED_BELOW = 0x12, 635 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 636 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 637 IPA_IRQ_UCP = 0x15, 638 /* The next bit is not present for IPA v4.5+ */ 639 IPA_IRQ_DCMP = 0x16, 640 IPA_IRQ_GSI_EE = 0x17, 641 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 642 IPA_IRQ_GSI_UC = 0x19, 643 /* The next bit is present for IPA v4.5+ */ 644 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 645 /* The next three bits are present for IPA v4.9+ */ 646 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 647 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 648 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 649 IPA_IRQ_COUNT, /* Last; not an id */ 650 }; 651 652 /* IPA_IRQ_UC register */ 653 enum ipa_reg_ipa_irq_uc_field_id { 654 UC_INTR, 655 }; 656 657 extern const struct ipa_regs ipa_regs_v3_1; 658 extern const struct ipa_regs ipa_regs_v3_5_1; 659 extern const struct ipa_regs ipa_regs_v4_2; 660 extern const struct ipa_regs ipa_regs_v4_5; 661 extern const struct ipa_regs ipa_regs_v4_9; 662 extern const struct ipa_regs ipa_regs_v4_11; 663 664 /* Return the field mask for a field in a register */ 665 static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) 666 { 667 if (!reg || WARN_ON(field_id >= reg->fcount)) 668 return 0; 669 670 return reg->fmask[field_id]; 671 } 672 673 /* Return the mask for a single-bit field in a register */ 674 static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) 675 { 676 u32 fmask = ipa_reg_fmask(reg, field_id); 677 678 WARN_ON(!is_power_of_2(fmask)); 679 680 return fmask; 681 } 682 683 /* Encode a value into the given field of a register */ 684 static inline u32 685 ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) 686 { 687 u32 fmask = ipa_reg_fmask(reg, field_id); 688 689 if (!fmask) 690 return 0; 691 692 val <<= __ffs(fmask); 693 if (WARN_ON(val & ~fmask)) 694 return 0; 695 696 return val; 697 } 698 699 /* Given a register value, decode (extract) the value in the given field */ 700 static inline u32 701 ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) 702 { 703 u32 fmask = ipa_reg_fmask(reg, field_id); 704 705 return fmask ? (val & fmask) >> __ffs(fmask) : 0; 706 } 707 708 /* Return the maximum value representable by the given field; always 2^n - 1 */ 709 static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) 710 { 711 u32 fmask = ipa_reg_fmask(reg, field_id); 712 713 return fmask ? fmask >> __ffs(fmask) : 0; 714 } 715 716 const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 717 718 /* Returns 0 for NULL reg; warning will have already been issued */ 719 static inline u32 ipa_reg_offset(const struct ipa_reg *reg) 720 { 721 return reg ? reg->offset : 0; 722 } 723 724 /* Returns 0 for NULL reg; warning will have already been issued */ 725 static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) 726 { 727 return reg ? reg->offset + n * reg->stride : 0; 728 } 729 730 int ipa_reg_init(struct ipa *ipa); 731 void ipa_reg_exit(struct ipa *ipa); 732 733 #endif /* _IPA_REG_H_ */ 734