1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 14 struct ipa; 15 16 /** 17 * DOC: IPA Registers 18 * 19 * IPA registers are located within the "ipa-reg" address space defined by 20 * Device Tree. The offset of each register within that space is specified 21 * by symbols defined below. The address space is mapped to virtual memory 22 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 23 * 24 * Certain register types are duplicated for a number of instances of 25 * something. For example, each IPA endpoint has an set of registers 26 * defining its configuration. The offset to an endpoint's set of registers 27 * is computed based on an "base" offset, plus an endpoint's ID multiplied 28 * and a "stride" value for the register. For such registers, the offset is 29 * computed by a function-like macro that takes a parameter used in the 30 * computation. 31 * 32 * Some register offsets depend on execution environment. For these an "ee" 33 * parameter is supplied to the offset macro. The "ee" value is a member of 34 * the gsi_ee enumerated type. 35 * 36 * The offset of a register dependent on endpoint ID is computed by a macro 37 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 38 * "ep" parameter is valid for any endpoint; a register with a "txep" or 39 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 40 * "*ep" value is assumed to be less than the maximum valid endpoint ID 41 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 42 * 43 * The offset of registers related to filter and route tables is computed 44 * by a macro that is supplied a parameter "er". The "er" represents an 45 * endpoint ID for filters, or a route ID for routes. For filters, the 46 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 47 * because not all endpoints support filtering. For routes, the route ID 48 * must be less than IPA_ROUTE_MAX. 49 * 50 * The offset of registers related to resource types is computed by a macro 51 * that is supplied a parameter "rt". The "rt" represents a resource type, 52 * which is a member of the ipa_resource_type_src enumerated type for 53 * source endpoint resources or the ipa_resource_type_dst enumerated type 54 * for destination endpoint resources. 55 * 56 * Some registers encode multiple fields within them. For these, each field 57 * has a symbol below defining a field mask that encodes both the position 58 * and width of the field within its register. 59 * 60 * In some cases, different versions of IPA hardware use different offset or 61 * field mask values. In such cases an inline_function(ipa) is used rather 62 * than a MACRO to define the offset or field mask to use. 63 * 64 * Finally, some registers hold bitmasks representing endpoints. In such 65 * cases the @available field in the @ipa structure defines the "full" set 66 * of valid bits for the register. 67 */ 68 69 /* enum ipa_reg_id - IPA register IDs */ 70 enum ipa_reg_id { 71 COMP_CFG, 72 CLKON_CFG, 73 ROUTE, 74 SHARED_MEM_SIZE, 75 QSB_MAX_WRITES, 76 QSB_MAX_READS, 77 FILT_ROUT_HASH_EN, 78 FILT_ROUT_HASH_FLUSH, 79 STATE_AGGR_ACTIVE, 80 IPA_BCR, /* Not IPA v4.5+ */ 81 LOCAL_PKT_PROC_CNTXT, 82 AGGR_FORCE_CLOSE, 83 COUNTER_CFG, /* Not IPA v4.5+ */ 84 IPA_TX_CFG, /* IPA v3.5+ */ 85 FLAVOR_0, /* IPA v3.5+ */ 86 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 87 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 88 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 89 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 90 SRC_RSRC_GRP_01_RSRC_TYPE, 91 SRC_RSRC_GRP_23_RSRC_TYPE, 92 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 93 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 94 DST_RSRC_GRP_01_RSRC_TYPE, 95 DST_RSRC_GRP_23_RSRC_TYPE, 96 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 97 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 98 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 99 ENDP_INIT_CFG, 100 ENDP_INIT_NAT, /* TX only */ 101 ENDP_INIT_HDR, 102 ENDP_INIT_HDR_EXT, 103 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 104 ENDP_INIT_MODE, /* TX only */ 105 ENDP_INIT_AGGR, 106 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 107 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 108 ENDP_INIT_DEAGGR, /* TX only */ 109 ENDP_INIT_RSRC_GRP, 110 ENDP_INIT_SEQ, /* TX only */ 111 ENDP_STATUS, 112 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 113 /* The IRQ registers are only used for GSI_EE_AP */ 114 IPA_IRQ_STTS, 115 IPA_IRQ_EN, 116 IPA_IRQ_CLR, 117 IPA_IRQ_UC, 118 IRQ_SUSPEND_INFO, 119 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 120 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 121 IPA_REG_ID_COUNT, /* Last; not an ID */ 122 }; 123 124 /** 125 * struct ipa_reg - An IPA register descriptor 126 * @offset: Register offset relative to base of the "ipa-reg" memory 127 * @stride: Distance between two instances, if parameterized 128 * @name: Upper-case name of the IPA register 129 */ 130 struct ipa_reg { 131 u32 offset; 132 u32 stride; 133 const char *name; 134 }; 135 136 /* Helper macro for defining "simple" (non-parameterized) registers */ 137 #define IPA_REG(__NAME, __reg_id, __offset) \ 138 IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 139 140 /* Helper macro for defining parameterized registers, specifying stride */ 141 #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 142 static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 143 .name = #__NAME, \ 144 .offset = __offset, \ 145 .stride = __stride, \ 146 } 147 148 /** 149 * struct ipa_regs - Description of registers supported by hardware 150 * @reg_count: Number of registers in the @reg[] array 151 * @reg: Array of register descriptors 152 */ 153 struct ipa_regs { 154 u32 reg_count; 155 const struct ipa_reg **reg; 156 }; 157 158 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 159 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 160 #define ENABLE_FMASK GENMASK(0, 0) 161 /* The next field is present for IPA v4.7+ */ 162 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 163 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 164 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 165 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 166 /* The next field is not present for IPA v4.5+ */ 167 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 168 /* The next twelve fields are present for IPA v4.0+ */ 169 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 170 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 171 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 172 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 173 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 174 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 175 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 176 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 177 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 178 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 179 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 180 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 181 /* The next five fields are present for IPA v4.9+ */ 182 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 183 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 184 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 185 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 186 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 187 188 /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ 189 static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, 190 u32 mask) 191 { 192 WARN_ON(version < IPA_VERSION_4_0); 193 194 if (version < IPA_VERSION_4_9) 195 return u32_encode_bits(mask, GENMASK(20, 17)); 196 197 if (version == IPA_VERSION_4_9) 198 return u32_encode_bits(mask, GENMASK(24, 22)); 199 200 return u32_encode_bits(mask, GENMASK(23, 22)); 201 } 202 203 /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ 204 static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, 205 bool enable) 206 { 207 u32 val = enable ? 1 : 0; 208 209 WARN_ON(version < IPA_VERSION_4_5); 210 211 if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) 212 return u32_encode_bits(val, GENMASK(21, 21)); 213 214 return u32_encode_bits(val, GENMASK(17, 17)); 215 } 216 217 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 218 #define RX_FMASK GENMASK(0, 0) 219 #define PROC_FMASK GENMASK(1, 1) 220 #define TX_WRAPPER_FMASK GENMASK(2, 2) 221 #define MISC_FMASK GENMASK(3, 3) 222 #define RAM_ARB_FMASK GENMASK(4, 4) 223 #define FTCH_HPS_FMASK GENMASK(5, 5) 224 #define FTCH_DPS_FMASK GENMASK(6, 6) 225 #define HPS_FMASK GENMASK(7, 7) 226 #define DPS_FMASK GENMASK(8, 8) 227 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 228 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 229 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 230 #define RSRC_MNGR_FMASK GENMASK(12, 12) 231 #define CTX_HANDLER_FMASK GENMASK(13, 13) 232 #define ACK_MNGR_FMASK GENMASK(14, 14) 233 #define D_DCPH_FMASK GENMASK(15, 15) 234 #define H_DCPH_FMASK GENMASK(16, 16) 235 /* The next field is not present for IPA v4.5+ */ 236 #define DCMP_FMASK GENMASK(17, 17) 237 /* The next three fields are present for IPA v3.5+ */ 238 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 239 #define TX_0_FMASK GENMASK(19, 19) 240 #define TX_1_FMASK GENMASK(20, 20) 241 /* The next field is present for IPA v3.5.1+ */ 242 #define FNR_FMASK GENMASK(21, 21) 243 /* The next eight fields are present for IPA v4.0+ */ 244 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 245 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 246 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 247 #define QMB_FMASK GENMASK(25, 25) 248 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 249 #define GSI_IF_FMASK GENMASK(27, 27) 250 #define GLOBAL_FMASK GENMASK(28, 28) 251 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 252 /* The next field is present for IPA v4.5+ */ 253 #define DPL_FIFO_FMASK GENMASK(30, 30) 254 /* The next field is present for IPA v4.7+ */ 255 #define DRBIP_FMASK GENMASK(31, 31) 256 257 #define IPA_REG_ROUTE_OFFSET 0x00000048 258 #define ROUTE_DIS_FMASK GENMASK(0, 0) 259 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 260 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 261 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 262 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 263 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 264 265 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 266 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 267 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 268 269 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 270 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 271 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 272 273 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 274 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 275 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 276 /* The next two fields are present for IPA v4.0+ */ 277 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 278 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 279 280 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 281 { 282 if (version < IPA_VERSION_4_0) 283 return 0x000008c; 284 285 return 0x0000148; 286 } 287 288 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 289 { 290 if (version < IPA_VERSION_4_0) 291 return 0x0000090; 292 293 return 0x000014c; 294 } 295 296 /* The next four fields are used for the hash enable and flush registers */ 297 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 298 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 299 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 300 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 301 302 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 303 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 304 { 305 if (version < IPA_VERSION_4_0) 306 return 0x0000010c; 307 308 return 0x000000b4; 309 } 310 311 /* The next register is not present for IPA v4.5+ */ 312 #define IPA_REG_BCR_OFFSET 0x000001d0 313 enum ipa_bcr_compat { 314 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 315 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 316 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 317 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 318 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 319 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 320 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 321 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 322 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 323 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 324 }; 325 326 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 327 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 328 329 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 330 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 331 u32 addr) 332 { 333 if (version < IPA_VERSION_4_5) 334 return u32_encode_bits(addr, GENMASK(16, 0)); 335 336 return u32_encode_bits(addr, GENMASK(17, 0)); 337 } 338 339 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 340 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 341 342 /* The next register is not present for IPA v4.5+ */ 343 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 344 /* The next field is not present for IPA v3.5+ */ 345 #define EOT_COAL_GRANULARITY_FMASK GENMASK(3, 0) 346 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 347 348 /* The next register is present for IPA v3.5+ */ 349 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 350 /* The next three fields are not present for IPA v4.0+ */ 351 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 352 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 353 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 354 /* The next six fields are present for IPA v4.0+ */ 355 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 356 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 357 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 358 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 359 #define PA_MASK_EN_FMASK GENMASK(12, 12) 360 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 361 /* The next field is present for IPA v4.5+ */ 362 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 363 /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 364 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 365 /* The next field is present for IPA v4.2 only */ 366 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 367 368 /* The next register is present for IPA v3.5+ */ 369 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 370 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 371 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 372 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 373 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 374 375 /* The next register is present for IPA v3.5+ */ 376 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 377 { 378 if (version >= IPA_VERSION_4_2) 379 return 0x00000240; 380 381 return 0x00000220; 382 } 383 384 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 385 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 386 387 /* The next register is present for IPA v4.5+ */ 388 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 389 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 390 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 391 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 392 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 393 394 /* The next register is present for IPA v4.5+ */ 395 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 396 #define DIV_VALUE_FMASK GENMASK(8, 0) 397 #define DIV_ENABLE_FMASK GENMASK(31, 31) 398 399 /* The next register is present for IPA v4.5+ */ 400 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 401 #define GRAN_0_FMASK GENMASK(2, 0) 402 #define GRAN_1_FMASK GENMASK(5, 3) 403 #define GRAN_2_FMASK GENMASK(8, 6) 404 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 405 enum ipa_pulse_gran { 406 IPA_GRAN_10_US = 0x0, 407 IPA_GRAN_20_US = 0x1, 408 IPA_GRAN_50_US = 0x2, 409 IPA_GRAN_100_US = 0x3, 410 IPA_GRAN_1_MS = 0x4, 411 IPA_GRAN_10_MS = 0x5, 412 IPA_GRAN_100_MS = 0x6, 413 IPA_GRAN_655350_US = 0x7, 414 }; 415 416 /* Not all of the following are present (depends on IPA version) */ 417 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 418 (0x00000400 + 0x0020 * (rt)) 419 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 420 (0x00000404 + 0x0020 * (rt)) 421 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 422 (0x00000408 + 0x0020 * (rt)) 423 #define IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 424 (0x0000040c + 0x0020 * (rt)) 425 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 426 (0x00000500 + 0x0020 * (rt)) 427 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 428 (0x00000504 + 0x0020 * (rt)) 429 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 430 (0x00000508 + 0x0020 * (rt)) 431 #define IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 432 (0x0000050c + 0x0020 * (rt)) 433 /* The next four fields are used for all resource group registers */ 434 #define X_MIN_LIM_FMASK GENMASK(5, 0) 435 #define X_MAX_LIM_FMASK GENMASK(13, 8) 436 /* The next two fields are not always present (if resource count is odd) */ 437 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 438 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 439 440 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 441 (0x00000800 + 0x0070 * (ep)) 442 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 443 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 444 /* Valid only for TX (IPA consumer) endpoints */ 445 #define ENDP_DELAY_FMASK GENMASK(1, 1) 446 447 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 448 (0x00000808 + 0x0070 * (ep)) 449 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 450 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 451 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 452 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 453 454 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 455 enum ipa_cs_offload_en { 456 IPA_CS_OFFLOAD_NONE = 0x0, 457 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 458 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 459 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 460 }; 461 462 /* Valid only for TX (IPA consumer) endpoints */ 463 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 464 (0x0000080c + 0x0070 * (ep)) 465 #define NAT_EN_FMASK GENMASK(1, 0) 466 467 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 468 enum ipa_nat_en { 469 IPA_NAT_BYPASS = 0x0, 470 IPA_NAT_SRC = 0x1, 471 IPA_NAT_DST = 0x2, 472 }; 473 474 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 475 (0x00000810 + 0x0070 * (ep)) 476 #define HDR_LEN_FMASK GENMASK(5, 0) 477 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 478 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 479 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 480 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 481 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 482 /* The next field is not present for IPA v4.9+ */ 483 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 484 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 485 /* The next field is not present for IPA v4.5+ */ 486 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 487 /* The next two fields are present for IPA v4.5+ */ 488 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 489 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 490 491 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 492 static inline u32 ipa_header_size_encoded(enum ipa_version version, 493 u32 header_size) 494 { 495 u32 size = header_size & field_mask(HDR_LEN_FMASK); 496 u32 val; 497 498 val = u32_encode_bits(size, HDR_LEN_FMASK); 499 if (version < IPA_VERSION_4_5) { 500 WARN_ON(header_size != size); 501 return val; 502 } 503 504 /* IPA v4.5 adds a few more most-significant bits */ 505 size = header_size >> hweight32(HDR_LEN_FMASK); 506 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 507 508 return val; 509 } 510 511 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 512 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 513 u32 offset) 514 { 515 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 516 u32 val; 517 518 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 519 if (version < IPA_VERSION_4_5) { 520 WARN_ON(offset != off); 521 return val; 522 } 523 524 /* IPA v4.5 adds a few more most-significant bits */ 525 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 526 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 527 528 return val; 529 } 530 531 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 532 (0x00000814 + 0x0070 * (ep)) 533 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 534 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 535 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 536 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 537 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 538 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 539 /* The next three fields are present for IPA v4.5+ */ 540 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 541 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 542 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 543 544 /* Valid only for RX (IPA producer) endpoints */ 545 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 546 (0x00000818 + 0x0070 * (rxep)) 547 548 /* Valid only for TX (IPA consumer) endpoints */ 549 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 550 (0x00000820 + 0x0070 * (txep)) 551 #define MODE_FMASK GENMASK(2, 0) 552 /* The next field is present for IPA v4.5+ */ 553 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 554 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 555 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 556 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 557 #define PAD_EN_FMASK GENMASK(29, 29) 558 /* The next field is not present for IPA v4.5+ */ 559 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 560 /* The next field is present for IPA v4.9+ */ 561 #define DRBIP_ACL_ENABLE_FMASK GENMASK(30, 30) 562 563 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 564 enum ipa_mode { 565 IPA_BASIC = 0x0, 566 IPA_ENABLE_FRAMING_HDLC = 0x1, 567 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 568 IPA_DMA = 0x3, 569 }; 570 571 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 572 (0x00000824 + 0x0070 * (ep)) 573 #define AGGR_EN_FMASK GENMASK(1, 0) 574 #define AGGR_TYPE_FMASK GENMASK(4, 2) 575 576 /* The legacy value is used for IPA hardware before IPA v4.5 */ 577 static inline u32 aggr_byte_limit_fmask(bool legacy) 578 { 579 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 580 } 581 582 /* The legacy value is used for IPA hardware before IPA v4.5 */ 583 static inline u32 aggr_time_limit_fmask(bool legacy) 584 { 585 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 586 } 587 588 /* The legacy value is used for IPA hardware before IPA v4.5 */ 589 static inline u32 aggr_pkt_limit_fmask(bool legacy) 590 { 591 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 592 } 593 594 /* The legacy value is used for IPA hardware before IPA v4.5 */ 595 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 596 { 597 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 598 } 599 600 /* The legacy value is used for IPA hardware before IPA v4.5 */ 601 static inline u32 aggr_force_close_fmask(bool legacy) 602 { 603 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 604 } 605 606 /* The legacy value is used for IPA hardware before IPA v4.5 */ 607 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 608 { 609 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 610 } 611 612 /* The next field is present for IPA v4.5+ */ 613 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 614 615 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 616 enum ipa_aggr_en { 617 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 618 IPA_ENABLE_AGGR /* RX */ = 0x1, 619 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 620 }; 621 622 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 623 enum ipa_aggr_type { 624 IPA_MBIM_16 = 0x0, 625 IPA_HDLC = 0x1, 626 IPA_TLP = 0x2, 627 IPA_RNDIS = 0x3, 628 IPA_GENERIC = 0x4, 629 IPA_COALESCE = 0x5, 630 IPA_QCMAP = 0x6, 631 }; 632 633 /* Valid only for RX (IPA producer) endpoints */ 634 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 635 (0x0000082c + 0x0070 * (rxep)) 636 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 637 638 /* Valid only for RX (IPA producer) endpoints */ 639 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 640 (0x00000830 + 0x0070 * (rxep)) 641 /* The next two fields are present for IPA v4.2 only */ 642 #define BASE_VALUE_FMASK GENMASK(4, 0) 643 #define SCALE_FMASK GENMASK(12, 8) 644 /* The next two fields are present for IPA v4.5 */ 645 #define TIME_LIMIT_FMASK GENMASK(4, 0) 646 #define GRAN_SEL_FMASK GENMASK(8, 8) 647 648 /* Valid only for TX (IPA consumer) endpoints */ 649 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 650 (0x00000834 + 0x0070 * (txep)) 651 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 652 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 653 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 654 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 655 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 656 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 657 658 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 659 (0x00000838 + 0x0070 * (ep)) 660 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 661 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 662 { 663 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 664 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 665 666 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 667 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 668 669 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 670 } 671 672 /* Valid only for TX (IPA consumer) endpoints */ 673 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 674 (0x0000083c + 0x0070 * (txep)) 675 #define SEQ_TYPE_FMASK GENMASK(7, 0) 676 /* The next field must be zero for IPA v4.5+ */ 677 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 678 679 /** 680 * enum ipa_seq_type - HPS and DPS sequencer type 681 * @IPA_SEQ_DMA: Perform DMA only 682 * @IPA_SEQ_1_PASS: One pass through the pipeline 683 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 684 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 685 * @IPA_SEQ_2_PASS: Two passes through the pipeline 686 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 687 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 688 * 689 * The low-order byte of the sequencer type register defines the number of 690 * passes a packet takes through the IPA pipeline. The last pass through can 691 * optionally skip the microprocessor. Deciphering is optional for all types; 692 * if enabled, an additional mask (two bits) is added to the type value. 693 * 694 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 695 * supported (or meaningful). 696 */ 697 enum ipa_seq_type { 698 IPA_SEQ_DMA = 0x00, 699 IPA_SEQ_1_PASS = 0x02, 700 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 701 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 702 IPA_SEQ_2_PASS = 0x0a, 703 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 704 /* The next value can be ORed with the above */ 705 IPA_SEQ_DECIPHER = 0x11, 706 }; 707 708 /** 709 * enum ipa_seq_rep_type - replicated packet sequencer type 710 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 711 * 712 * This goes in the second byte of the endpoint sequencer type register. 713 * 714 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 715 * supported (or meaningful). 716 */ 717 enum ipa_seq_rep_type { 718 IPA_SEQ_REP_DMA_PARSER = 0x08, 719 }; 720 721 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 722 (0x00000840 + 0x0070 * (ep)) 723 #define STATUS_EN_FMASK GENMASK(0, 0) 724 #define STATUS_ENDP_FMASK GENMASK(5, 1) 725 /* The next field is not present for IPA v4.5+ */ 726 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 727 /* The next field is present for IPA v4.0+ */ 728 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 729 730 /* The next register is not present for IPA v4.2 (which no hashing support) */ 731 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 732 (0x0000085c + 0x0070 * (er)) 733 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 734 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 735 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 736 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 737 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 738 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 739 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 740 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 741 742 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 743 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 744 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 745 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 746 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 747 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 748 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 749 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 750 751 static inline u32 ipa_reg_irq_stts_ee_n_offset(enum ipa_version version, 752 u32 ee) 753 { 754 if (version < IPA_VERSION_4_9) 755 return 0x00003008 + 0x1000 * ee; 756 757 return 0x00004008 + 0x1000 * ee; 758 } 759 760 static inline u32 ipa_reg_irq_stts_offset(enum ipa_version version) 761 { 762 return ipa_reg_irq_stts_ee_n_offset(version, GSI_EE_AP); 763 } 764 765 static inline u32 ipa_reg_irq_en_ee_n_offset(enum ipa_version version, u32 ee) 766 { 767 if (version < IPA_VERSION_4_9) 768 return 0x0000300c + 0x1000 * ee; 769 770 return 0x0000400c + 0x1000 * ee; 771 } 772 773 static inline u32 ipa_reg_irq_en_offset(enum ipa_version version) 774 { 775 return ipa_reg_irq_en_ee_n_offset(version, GSI_EE_AP); 776 } 777 778 static inline u32 ipa_reg_irq_clr_ee_n_offset(enum ipa_version version, u32 ee) 779 { 780 if (version < IPA_VERSION_4_9) 781 return 0x00003010 + 0x1000 * ee; 782 783 return 0x00004010 + 0x1000 * ee; 784 } 785 786 static inline u32 ipa_reg_irq_clr_offset(enum ipa_version version) 787 { 788 return ipa_reg_irq_clr_ee_n_offset(version, GSI_EE_AP); 789 } 790 791 /** 792 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 793 * @IPA_IRQ_UC_0: Microcontroller event interrupt 794 * @IPA_IRQ_UC_1: Microcontroller response interrupt 795 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 796 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 797 * 798 * IRQ types not described above are not currently used. 799 * 800 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 801 * @IPA_IRQ_EOT_COAL: (Not currently used) 802 * @IPA_IRQ_UC_2: (Not currently used) 803 * @IPA_IRQ_UC_3: (Not currently used) 804 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 805 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 806 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 807 * @IPA_IRQ_RX_ERR: (Not currently used) 808 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 809 * @IPA_IRQ_TX_ERR: (Not currently used) 810 * @IPA_IRQ_STEP_MODE: (Not currently used) 811 * @IPA_IRQ_PROC_ERR: (Not currently used) 812 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 813 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 814 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 815 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 816 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 817 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 818 * @IPA_IRQ_UCP: (Not currently used) 819 * @IPA_IRQ_DCMP: (Not currently used) 820 * @IPA_IRQ_GSI_EE: (Not currently used) 821 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 822 * @IPA_IRQ_GSI_UC: (Not currently used) 823 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 824 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 825 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 826 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 827 */ 828 enum ipa_irq_id { 829 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 830 /* The next bit is not present for IPA v3.5+ */ 831 IPA_IRQ_EOT_COAL = 0x1, 832 IPA_IRQ_UC_0 = 0x2, 833 IPA_IRQ_UC_1 = 0x3, 834 IPA_IRQ_UC_2 = 0x4, 835 IPA_IRQ_UC_3 = 0x5, 836 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 837 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 838 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 839 IPA_IRQ_RX_ERR = 0x9, 840 IPA_IRQ_DEAGGR_ERR = 0xa, 841 IPA_IRQ_TX_ERR = 0xb, 842 IPA_IRQ_STEP_MODE = 0xc, 843 IPA_IRQ_PROC_ERR = 0xd, 844 IPA_IRQ_TX_SUSPEND = 0xe, 845 IPA_IRQ_TX_HOLB_DROP = 0xf, 846 IPA_IRQ_BAM_GSI_IDLE = 0x10, 847 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 848 IPA_IRQ_PIPE_RED_BELOW = 0x12, 849 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 850 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 851 IPA_IRQ_UCP = 0x15, 852 /* The next bit is not present for IPA v4.5+ */ 853 IPA_IRQ_DCMP = 0x16, 854 IPA_IRQ_GSI_EE = 0x17, 855 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 856 IPA_IRQ_GSI_UC = 0x19, 857 /* The next bit is present for IPA v4.5+ */ 858 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 859 /* The next three bits are present for IPA v4.9+ */ 860 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 861 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 862 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 863 IPA_IRQ_COUNT, /* Last; not an id */ 864 }; 865 866 static inline u32 ipa_reg_irq_uc_ee_n_offset(enum ipa_version version, u32 ee) 867 { 868 if (version < IPA_VERSION_4_9) 869 return 0x0000301c + 0x1000 * ee; 870 871 return 0x0000401c + 0x1000 * ee; 872 } 873 874 static inline u32 ipa_reg_irq_uc_offset(enum ipa_version version) 875 { 876 return ipa_reg_irq_uc_ee_n_offset(version, GSI_EE_AP); 877 } 878 879 #define UC_INTR_FMASK GENMASK(0, 0) 880 881 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 882 static inline u32 883 ipa_reg_irq_suspend_info_ee_n_offset(enum ipa_version version, u32 ee) 884 { 885 if (version == IPA_VERSION_3_0) 886 return 0x00003098 + 0x1000 * ee; 887 888 if (version < IPA_VERSION_4_9) 889 return 0x00003030 + 0x1000 * ee; 890 891 return 0x00004030 + 0x1000 * ee; 892 } 893 894 static inline u32 895 ipa_reg_irq_suspend_info_offset(enum ipa_version version) 896 { 897 return ipa_reg_irq_suspend_info_ee_n_offset(version, GSI_EE_AP); 898 } 899 900 /* ipa->available defines the valid bits in the SUSPEND_EN register */ 901 static inline u32 902 ipa_reg_irq_suspend_en_ee_n_offset(enum ipa_version version, u32 ee) 903 { 904 WARN_ON(version == IPA_VERSION_3_0); 905 906 if (version < IPA_VERSION_4_9) 907 return 0x00003034 + 0x1000 * ee; 908 909 return 0x00004034 + 0x1000 * ee; 910 } 911 912 static inline u32 913 ipa_reg_irq_suspend_en_offset(enum ipa_version version) 914 { 915 return ipa_reg_irq_suspend_en_ee_n_offset(version, GSI_EE_AP); 916 } 917 918 /* ipa->available defines the valid bits in the SUSPEND_CLR register */ 919 static inline u32 920 ipa_reg_irq_suspend_clr_ee_n_offset(enum ipa_version version, u32 ee) 921 { 922 WARN_ON(version == IPA_VERSION_3_0); 923 924 if (version < IPA_VERSION_4_9) 925 return 0x00003038 + 0x1000 * ee; 926 927 return 0x00004038 + 0x1000 * ee; 928 } 929 930 static inline u32 931 ipa_reg_irq_suspend_clr_offset(enum ipa_version version) 932 { 933 return ipa_reg_irq_suspend_clr_ee_n_offset(version, GSI_EE_AP); 934 } 935 936 extern const struct ipa_regs ipa_regs_v3_1; 937 extern const struct ipa_regs ipa_regs_v3_5_1; 938 extern const struct ipa_regs ipa_regs_v4_2; 939 extern const struct ipa_regs ipa_regs_v4_5; 940 extern const struct ipa_regs ipa_regs_v4_9; 941 extern const struct ipa_regs ipa_regs_v4_11; 942 943 u32 __ipa_reg_offset(struct ipa *ipa, enum ipa_reg_id reg_id, u32 n); 944 945 const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 946 947 static inline u32 ipa_reg_offset(struct ipa *ipa, enum ipa_reg_id reg_id) 948 { 949 return __ipa_reg_offset(ipa, reg_id, 0); 950 } 951 952 static inline u32 953 ipa_reg_n_offset(struct ipa *ipa, enum ipa_reg_id reg_id, u32 n) 954 { 955 return __ipa_reg_offset(ipa, reg_id, n); 956 } 957 958 int ipa_reg_init(struct ipa *ipa); 959 void ipa_reg_exit(struct ipa *ipa); 960 961 #endif /* _IPA_REG_H_ */ 962