1ba764c4dSAlex Elder // SPDX-License-Identifier: GPL-2.0 2ba764c4dSAlex Elder 3ba764c4dSAlex Elder /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4a4388da5SAlex Elder * Copyright (C) 2018-2022 Linaro Ltd. 5ba764c4dSAlex Elder */ 6ba764c4dSAlex Elder 7ba764c4dSAlex Elder /* DOC: IPA Interrupts 8ba764c4dSAlex Elder * 9ba764c4dSAlex Elder * The IPA has an interrupt line distinct from the interrupt used by the GSI 10ba764c4dSAlex Elder * code. Whereas GSI interrupts are generally related to channel events (like 11ba764c4dSAlex Elder * transfer completions), IPA interrupts are related to other events related 12ba764c4dSAlex Elder * to the IPA. Some of the IPA interrupts come from a microcontroller 13ba764c4dSAlex Elder * embedded in the IPA. Each IPA interrupt type can be both masked and 14ba764c4dSAlex Elder * acknowledged independent of the others. 15ba764c4dSAlex Elder * 16ba764c4dSAlex Elder * Two of the IPA interrupts are initiated by the microcontroller. A third 17ba764c4dSAlex Elder * can be generated to signal the need for a wakeup/resume when an IPA 18ba764c4dSAlex Elder * endpoint has been suspended. There are other IPA events, but at this 19ba764c4dSAlex Elder * time only these three are supported. 20ba764c4dSAlex Elder */ 21ba764c4dSAlex Elder 22ba764c4dSAlex Elder #include <linux/types.h> 23ba764c4dSAlex Elder #include <linux/interrupt.h> 24c3f115aaSAlex Elder #include <linux/pm_runtime.h> 25*df54fde4SCaleb Connolly #include <linux/pm_wakeirq.h> 26ba764c4dSAlex Elder 27ba764c4dSAlex Elder #include "ipa.h" 28ba764c4dSAlex Elder #include "ipa_reg.h" 29ba764c4dSAlex Elder #include "ipa_endpoint.h" 30482ae3a9SAlex Elder #include "ipa_power.h" 31482ae3a9SAlex Elder #include "ipa_uc.h" 32ba764c4dSAlex Elder #include "ipa_interrupt.h" 33ba764c4dSAlex Elder 34ba764c4dSAlex Elder /** 35ba764c4dSAlex Elder * struct ipa_interrupt - IPA interrupt information 36ba764c4dSAlex Elder * @ipa: IPA pointer 37ba764c4dSAlex Elder * @irq: Linux IRQ number used for IPA interrupts 38ba764c4dSAlex Elder * @enabled: Mask indicating which interrupts are enabled 39ba764c4dSAlex Elder */ 40ba764c4dSAlex Elder struct ipa_interrupt { 41ba764c4dSAlex Elder struct ipa *ipa; 42ba764c4dSAlex Elder u32 irq; 43ba764c4dSAlex Elder u32 enabled; 44ba764c4dSAlex Elder }; 45ba764c4dSAlex Elder 46ba764c4dSAlex Elder /* Process a particular interrupt type that has been received */ 47ba764c4dSAlex Elder static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) 48ba764c4dSAlex Elder { 49ba764c4dSAlex Elder struct ipa *ipa = interrupt->ipa; 506a244b75SAlex Elder const struct ipa_reg *reg; 51ba764c4dSAlex Elder u32 mask = BIT(irq_id); 52e666aa97SAlex Elder u32 offset; 53ba764c4dSAlex Elder 546a244b75SAlex Elder reg = ipa_reg(ipa, IPA_IRQ_CLR); 556a244b75SAlex Elder offset = ipa_reg_offset(reg); 56ba764c4dSAlex Elder 57bfb79854SAlex Elder switch (irq_id) { 58bfb79854SAlex Elder case IPA_IRQ_UC_0: 59bfb79854SAlex Elder case IPA_IRQ_UC_1: 60bfb79854SAlex Elder /* For microcontroller interrupts, clear the interrupt right 61bfb79854SAlex Elder * away, "to avoid clearing unhandled interrupts." 62ba764c4dSAlex Elder */ 63e666aa97SAlex Elder iowrite32(mask, ipa->reg_virt + offset); 64bfb79854SAlex Elder ipa_uc_interrupt_handler(ipa, irq_id); 65bfb79854SAlex Elder break; 66bfb79854SAlex Elder 67bfb79854SAlex Elder case IPA_IRQ_TX_SUSPEND: 68bfb79854SAlex Elder /* Clearing the SUSPEND_TX interrupt also clears the 69bfb79854SAlex Elder * register that tells us which suspended endpoint(s) 70bfb79854SAlex Elder * caused the interrupt, so defer clearing until after 71bfb79854SAlex Elder * the handler has been called. 72bfb79854SAlex Elder */ 73bfb79854SAlex Elder ipa_power_suspend_handler(ipa, irq_id); 74bfb79854SAlex Elder fallthrough; 75bfb79854SAlex Elder 76bfb79854SAlex Elder default: /* Silently ignore (and clear) any other condition */ 77bfb79854SAlex Elder iowrite32(mask, ipa->reg_virt + offset); 78bfb79854SAlex Elder break; 79bfb79854SAlex Elder } 80ba764c4dSAlex Elder } 81ba764c4dSAlex Elder 82176086d8SAlex Elder /* IPA IRQ handler is threaded */ 83176086d8SAlex Elder static irqreturn_t ipa_isr_thread(int irq, void *dev_id) 84ba764c4dSAlex Elder { 85176086d8SAlex Elder struct ipa_interrupt *interrupt = dev_id; 86ba764c4dSAlex Elder struct ipa *ipa = interrupt->ipa; 87ba764c4dSAlex Elder u32 enabled = interrupt->enabled; 886a244b75SAlex Elder const struct ipa_reg *reg; 89c3f115aaSAlex Elder struct device *dev; 90e70e410fSAlex Elder u32 pending; 91e666aa97SAlex Elder u32 offset; 92ba764c4dSAlex Elder u32 mask; 937ebd168cSAlex Elder int ret; 94ba764c4dSAlex Elder 95c3f115aaSAlex Elder dev = &ipa->pdev->dev; 96c3f115aaSAlex Elder ret = pm_runtime_get_sync(dev); 977ebd168cSAlex Elder if (WARN_ON(ret < 0)) 98c3f115aaSAlex Elder goto out_power_put; 99176086d8SAlex Elder 100ba764c4dSAlex Elder /* The status register indicates which conditions are present, 101ba764c4dSAlex Elder * including conditions whose interrupt is not enabled. Handle 102ba764c4dSAlex Elder * only the enabled ones. 103ba764c4dSAlex Elder */ 1046a244b75SAlex Elder reg = ipa_reg(ipa, IPA_IRQ_STTS); 1056a244b75SAlex Elder offset = ipa_reg_offset(reg); 106e70e410fSAlex Elder pending = ioread32(ipa->reg_virt + offset); 107e70e410fSAlex Elder while ((mask = pending & enabled)) { 108ba764c4dSAlex Elder do { 109ba764c4dSAlex Elder u32 irq_id = __ffs(mask); 110ba764c4dSAlex Elder 111ba764c4dSAlex Elder mask ^= BIT(irq_id); 112ba764c4dSAlex Elder 113ba764c4dSAlex Elder ipa_interrupt_process(interrupt, irq_id); 114ba764c4dSAlex Elder } while (mask); 115e70e410fSAlex Elder pending = ioread32(ipa->reg_virt + offset); 116e70e410fSAlex Elder } 117e70e410fSAlex Elder 118e70e410fSAlex Elder /* If any disabled interrupts are pending, clear them */ 119e70e410fSAlex Elder if (pending) { 120e70e410fSAlex Elder dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n", 121e70e410fSAlex Elder pending); 1226a244b75SAlex Elder reg = ipa_reg(ipa, IPA_IRQ_CLR); 1236a244b75SAlex Elder offset = ipa_reg_offset(reg); 124e70e410fSAlex Elder iowrite32(pending, ipa->reg_virt + offset); 125ba764c4dSAlex Elder } 126c3f115aaSAlex Elder out_power_put: 1271aac309dSAlex Elder pm_runtime_mark_last_busy(dev); 1281aac309dSAlex Elder (void)pm_runtime_put_autosuspend(dev); 129937a0da4SAlex Elder 130ba764c4dSAlex Elder return IRQ_HANDLED; 131ba764c4dSAlex Elder } 132ba764c4dSAlex Elder 1338e461e1fSAlex Elder static void ipa_interrupt_enabled_update(struct ipa *ipa) 1348e461e1fSAlex Elder { 1358e461e1fSAlex Elder const struct ipa_reg *reg = ipa_reg(ipa, IPA_IRQ_EN); 1368e461e1fSAlex Elder 1378e461e1fSAlex Elder iowrite32(ipa->interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg)); 1388e461e1fSAlex Elder } 1398e461e1fSAlex Elder 1408e461e1fSAlex Elder /* Enable an IPA interrupt type */ 141d50ed355SAlex Elder void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq) 1428e461e1fSAlex Elder { 1438e461e1fSAlex Elder /* Update the IPA interrupt mask to enable it */ 1448e461e1fSAlex Elder ipa->interrupt->enabled |= BIT(ipa_irq); 1458e461e1fSAlex Elder ipa_interrupt_enabled_update(ipa); 1468e461e1fSAlex Elder } 1478e461e1fSAlex Elder 1488e461e1fSAlex Elder /* Disable an IPA interrupt type */ 149d50ed355SAlex Elder void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq) 1508e461e1fSAlex Elder { 1518e461e1fSAlex Elder /* Update the IPA interrupt mask to disable it */ 1528e461e1fSAlex Elder ipa->interrupt->enabled &= ~BIT(ipa_irq); 1538e461e1fSAlex Elder ipa_interrupt_enabled_update(ipa); 1548e461e1fSAlex Elder } 1558e461e1fSAlex Elder 1569ec9b2a3SCaleb Connolly void ipa_interrupt_irq_disable(struct ipa *ipa) 1579ec9b2a3SCaleb Connolly { 1589ec9b2a3SCaleb Connolly disable_irq(ipa->interrupt->irq); 1599ec9b2a3SCaleb Connolly } 1609ec9b2a3SCaleb Connolly 1619ec9b2a3SCaleb Connolly void ipa_interrupt_irq_enable(struct ipa *ipa) 1629ec9b2a3SCaleb Connolly { 1639ec9b2a3SCaleb Connolly enable_irq(ipa->interrupt->irq); 1649ec9b2a3SCaleb Connolly } 1659ec9b2a3SCaleb Connolly 166ba764c4dSAlex Elder /* Common function used to enable/disable TX_SUSPEND for an endpoint */ 167ba764c4dSAlex Elder static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt, 168ba764c4dSAlex Elder u32 endpoint_id, bool enable) 169ba764c4dSAlex Elder { 170ba764c4dSAlex Elder struct ipa *ipa = interrupt->ipa; 171d9d71a89SAlex Elder u32 mask = BIT(endpoint_id % 32); 172f298ba78SAlex Elder u32 unit = endpoint_id / 32; 1736a244b75SAlex Elder const struct ipa_reg *reg; 174e666aa97SAlex Elder u32 offset; 175ba764c4dSAlex Elder u32 val; 176ba764c4dSAlex Elder 17788de7672SAlex Elder WARN_ON(!test_bit(endpoint_id, ipa->available)); 178e666aa97SAlex Elder 179e666aa97SAlex Elder /* IPA version 3.0 does not support TX_SUSPEND interrupt control */ 180e666aa97SAlex Elder if (ipa->version == IPA_VERSION_3_0) 181e666aa97SAlex Elder return; 182e666aa97SAlex Elder 1836a244b75SAlex Elder reg = ipa_reg(ipa, IRQ_SUSPEND_EN); 184f298ba78SAlex Elder offset = ipa_reg_n_offset(reg, unit); 185e666aa97SAlex Elder val = ioread32(ipa->reg_virt + offset); 18688de7672SAlex Elder 187ba764c4dSAlex Elder if (enable) 188ba764c4dSAlex Elder val |= mask; 189ba764c4dSAlex Elder else 190ba764c4dSAlex Elder val &= ~mask; 19188de7672SAlex Elder 192e666aa97SAlex Elder iowrite32(val, ipa->reg_virt + offset); 193ba764c4dSAlex Elder } 194ba764c4dSAlex Elder 195ba764c4dSAlex Elder /* Enable TX_SUSPEND for an endpoint */ 196ba764c4dSAlex Elder void 197ba764c4dSAlex Elder ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id) 198ba764c4dSAlex Elder { 199ba764c4dSAlex Elder ipa_interrupt_suspend_control(interrupt, endpoint_id, true); 200ba764c4dSAlex Elder } 201ba764c4dSAlex Elder 202ba764c4dSAlex Elder /* Disable TX_SUSPEND for an endpoint */ 203ba764c4dSAlex Elder void 204ba764c4dSAlex Elder ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id) 205ba764c4dSAlex Elder { 206ba764c4dSAlex Elder ipa_interrupt_suspend_control(interrupt, endpoint_id, false); 207ba764c4dSAlex Elder } 208ba764c4dSAlex Elder 209ba764c4dSAlex Elder /* Clear the suspend interrupt for all endpoints that signaled it */ 210ba764c4dSAlex Elder void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) 211ba764c4dSAlex Elder { 212ba764c4dSAlex Elder struct ipa *ipa = interrupt->ipa; 213f298ba78SAlex Elder u32 unit_count; 214f298ba78SAlex Elder u32 unit; 215f298ba78SAlex Elder 216f298ba78SAlex Elder unit_count = roundup(ipa->endpoint_count, 32); 217f298ba78SAlex Elder for (unit = 0; unit < unit_count; unit++) { 2186a244b75SAlex Elder const struct ipa_reg *reg; 219ba764c4dSAlex Elder u32 val; 220ba764c4dSAlex Elder 2216a244b75SAlex Elder reg = ipa_reg(ipa, IRQ_SUSPEND_INFO); 222f298ba78SAlex Elder val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit)); 223e666aa97SAlex Elder 224e666aa97SAlex Elder /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ 225e666aa97SAlex Elder if (ipa->version == IPA_VERSION_3_0) 226f298ba78SAlex Elder continue; 227e666aa97SAlex Elder 2286a244b75SAlex Elder reg = ipa_reg(ipa, IRQ_SUSPEND_CLR); 229f298ba78SAlex Elder iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, unit)); 230f298ba78SAlex Elder } 231ba764c4dSAlex Elder } 232ba764c4dSAlex Elder 233ba764c4dSAlex Elder /* Simulate arrival of an IPA TX_SUSPEND interrupt */ 234ba764c4dSAlex Elder void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt) 235ba764c4dSAlex Elder { 236ba764c4dSAlex Elder ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND); 237ba764c4dSAlex Elder } 238ba764c4dSAlex Elder 2391118a147SAlex Elder /* Configure the IPA interrupt framework */ 2401118a147SAlex Elder struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa) 241ba764c4dSAlex Elder { 242ba764c4dSAlex Elder struct device *dev = &ipa->pdev->dev; 243ba764c4dSAlex Elder struct ipa_interrupt *interrupt; 2446a244b75SAlex Elder const struct ipa_reg *reg; 245ba764c4dSAlex Elder unsigned int irq; 246ba764c4dSAlex Elder int ret; 247ba764c4dSAlex Elder 248ba764c4dSAlex Elder ret = platform_get_irq_byname(ipa->pdev, "ipa"); 249ba764c4dSAlex Elder if (ret <= 0) { 250ba764c4dSAlex Elder dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n", 251ba764c4dSAlex Elder ret); 252ba764c4dSAlex Elder return ERR_PTR(ret ? : -EINVAL); 253ba764c4dSAlex Elder } 254ba764c4dSAlex Elder irq = ret; 255ba764c4dSAlex Elder 256ba764c4dSAlex Elder interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL); 257ba764c4dSAlex Elder if (!interrupt) 258ba764c4dSAlex Elder return ERR_PTR(-ENOMEM); 259ba764c4dSAlex Elder interrupt->ipa = ipa; 260ba764c4dSAlex Elder interrupt->irq = irq; 261ba764c4dSAlex Elder 262ba764c4dSAlex Elder /* Start with all IPA interrupts disabled */ 2636a244b75SAlex Elder reg = ipa_reg(ipa, IPA_IRQ_EN); 2646a244b75SAlex Elder iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg)); 265ba764c4dSAlex Elder 266937a0da4SAlex Elder ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT, 267ba764c4dSAlex Elder "ipa", interrupt); 268ba764c4dSAlex Elder if (ret) { 269ba764c4dSAlex Elder dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret); 270ba764c4dSAlex Elder goto err_kfree; 271ba764c4dSAlex Elder } 272ba764c4dSAlex Elder 273*df54fde4SCaleb Connolly ret = dev_pm_set_wake_irq(dev, irq); 274d1b5126aSAlex Elder if (ret) { 275*df54fde4SCaleb Connolly dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n", ret); 276d1b5126aSAlex Elder goto err_free_irq; 277d1b5126aSAlex Elder } 278d1b5126aSAlex Elder 279ba764c4dSAlex Elder return interrupt; 280ba764c4dSAlex Elder 281d1b5126aSAlex Elder err_free_irq: 282d1b5126aSAlex Elder free_irq(interrupt->irq, interrupt); 283ba764c4dSAlex Elder err_kfree: 284ba764c4dSAlex Elder kfree(interrupt); 285ba764c4dSAlex Elder 286ba764c4dSAlex Elder return ERR_PTR(ret); 287ba764c4dSAlex Elder } 288ba764c4dSAlex Elder 2891118a147SAlex Elder /* Inverse of ipa_interrupt_config() */ 2901118a147SAlex Elder void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt) 291ba764c4dSAlex Elder { 292d1b5126aSAlex Elder struct device *dev = &interrupt->ipa->pdev->dev; 293d1b5126aSAlex Elder 294*df54fde4SCaleb Connolly dev_pm_clear_wake_irq(dev); 295ba764c4dSAlex Elder free_irq(interrupt->irq, interrupt); 296ba764c4dSAlex Elder kfree(interrupt); 297ba764c4dSAlex Elder } 298