1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2019-2021 Linaro Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/device.h> 9 #include <linux/slab.h> 10 #include <linux/bitfield.h> 11 #include <linux/dma-direction.h> 12 13 #include "gsi.h" 14 #include "gsi_trans.h" 15 #include "ipa.h" 16 #include "ipa_endpoint.h" 17 #include "ipa_table.h" 18 #include "ipa_cmd.h" 19 #include "ipa_mem.h" 20 21 /** 22 * DOC: IPA Immediate Commands 23 * 24 * The AP command TX endpoint is used to issue immediate commands to the IPA. 25 * An immediate command is generally used to request the IPA do something 26 * other than data transfer to another endpoint. 27 * 28 * Immediate commands are represented by GSI transactions just like other 29 * transfer requests, represented by a single GSI TRE. Each immediate 30 * command has a well-defined format, having a payload of a known length. 31 * This allows the transfer element's length field to be used to hold an 32 * immediate command's opcode. The payload for a command resides in DRAM 33 * and is described by a single scatterlist entry in its transaction. 34 * Commands do not require a transaction completion callback. To commit 35 * an immediate command transaction, either gsi_trans_commit_wait() or 36 * gsi_trans_commit_wait_timeout() is used. 37 */ 38 39 /* Some commands can wait until indicated pipeline stages are clear */ 40 enum pipeline_clear_options { 41 pipeline_clear_hps = 0x0, 42 pipeline_clear_src_grp = 0x1, 43 pipeline_clear_full = 0x2, 44 }; 45 46 /* IPA_CMD_IP_V{4,6}_{FILTER,ROUTING}_INIT */ 47 48 struct ipa_cmd_hw_ip_fltrt_init { 49 __le64 hash_rules_addr; 50 __le64 flags; 51 __le64 nhash_rules_addr; 52 }; 53 54 /* Field masks for ipa_cmd_hw_ip_fltrt_init structure fields */ 55 #define IP_FLTRT_FLAGS_HASH_SIZE_FMASK GENMASK_ULL(11, 0) 56 #define IP_FLTRT_FLAGS_HASH_ADDR_FMASK GENMASK_ULL(27, 12) 57 #define IP_FLTRT_FLAGS_NHASH_SIZE_FMASK GENMASK_ULL(39, 28) 58 #define IP_FLTRT_FLAGS_NHASH_ADDR_FMASK GENMASK_ULL(55, 40) 59 60 /* IPA_CMD_HDR_INIT_LOCAL */ 61 62 struct ipa_cmd_hw_hdr_init_local { 63 __le64 hdr_table_addr; 64 __le32 flags; 65 __le32 reserved; 66 }; 67 68 /* Field masks for ipa_cmd_hw_hdr_init_local structure fields */ 69 #define HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK GENMASK(11, 0) 70 #define HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK GENMASK(27, 12) 71 72 /* IPA_CMD_REGISTER_WRITE */ 73 74 /* For IPA v4.0+, the pipeline clear options are encoded in the opcode */ 75 #define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) 76 #define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) 77 78 struct ipa_cmd_register_write { 79 __le16 flags; /* Unused/reserved prior to IPA v4.0 */ 80 __le16 offset; 81 __le32 value; 82 __le32 value_mask; 83 __le32 clear_options; /* Unused/reserved for IPA v4.0+ */ 84 }; 85 86 /* Field masks for ipa_cmd_register_write structure fields */ 87 /* The next field is present for IPA v4.0+ */ 88 #define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11) 89 /* The next field is not present for IPA v4.0+ */ 90 #define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15) 91 92 /* The next field and its values are not present for IPA v4.0+ */ 93 #define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0) 94 95 /* IPA_CMD_IP_PACKET_INIT */ 96 97 struct ipa_cmd_ip_packet_init { 98 u8 dest_endpoint; 99 u8 reserved[7]; 100 }; 101 102 /* Field masks for ipa_cmd_ip_packet_init dest_endpoint field */ 103 #define IPA_PACKET_INIT_DEST_ENDPOINT_FMASK GENMASK(4, 0) 104 105 /* IPA_CMD_DMA_SHARED_MEM */ 106 107 /* For IPA v4.0+, this opcode gets modified with pipeline clear options */ 108 109 #define DMA_SHARED_MEM_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8) 110 #define DMA_SHARED_MEM_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9) 111 112 struct ipa_cmd_hw_dma_mem_mem { 113 __le16 clear_after_read; /* 0 or DMA_SHARED_MEM_CLEAR_AFTER_READ */ 114 __le16 size; 115 __le16 local_addr; 116 __le16 flags; 117 __le64 system_addr; 118 }; 119 120 /* Flag allowing atomic clear of target region after reading data (v4.0+)*/ 121 #define DMA_SHARED_MEM_CLEAR_AFTER_READ GENMASK(15, 15) 122 123 /* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */ 124 #define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0) 125 /* The next two fields are not present for IPA v4.0+ */ 126 #define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1) 127 #define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2) 128 129 /* IPA_CMD_IP_PACKET_TAG_STATUS */ 130 131 struct ipa_cmd_ip_packet_tag_status { 132 __le64 tag; 133 }; 134 135 #define IP_PACKET_TAG_STATUS_TAG_FMASK GENMASK_ULL(63, 16) 136 137 /* Immediate command payload */ 138 union ipa_cmd_payload { 139 struct ipa_cmd_hw_ip_fltrt_init table_init; 140 struct ipa_cmd_hw_hdr_init_local hdr_init_local; 141 struct ipa_cmd_register_write register_write; 142 struct ipa_cmd_ip_packet_init ip_packet_init; 143 struct ipa_cmd_hw_dma_mem_mem dma_shared_mem; 144 struct ipa_cmd_ip_packet_tag_status ip_packet_tag_status; 145 }; 146 147 static void ipa_cmd_validate_build(void) 148 { 149 /* The sizes of a filter and route tables need to fit into fields 150 * in the ipa_cmd_hw_ip_fltrt_init structure. Although hashed tables 151 * might not be used, non-hashed and hashed tables have the same 152 * maximum size. IPv4 and IPv6 filter tables have the same number 153 * of entries, as and IPv4 and IPv6 route tables have the same number 154 * of entries. 155 */ 156 #define TABLE_SIZE (TABLE_COUNT_MAX * sizeof(__le64)) 157 #define TABLE_COUNT_MAX max_t(u32, IPA_ROUTE_COUNT_MAX, IPA_FILTER_COUNT_MAX) 158 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_HASH_SIZE_FMASK)); 159 BUILD_BUG_ON(TABLE_SIZE > field_max(IP_FLTRT_FLAGS_NHASH_SIZE_FMASK)); 160 #undef TABLE_COUNT_MAX 161 #undef TABLE_SIZE 162 } 163 164 #ifdef IPA_VALIDATE 165 166 /* Validate a memory region holding a table */ 167 bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem, 168 bool route, bool ipv6, bool hashed) 169 { 170 struct device *dev = &ipa->pdev->dev; 171 u32 offset_max; 172 173 offset_max = hashed ? field_max(IP_FLTRT_FLAGS_HASH_ADDR_FMASK) 174 : field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); 175 if (mem->offset > offset_max || 176 ipa->mem_offset > offset_max - mem->offset) { 177 dev_err(dev, "IPv%c %s%s table region offset too large\n", 178 ipv6 ? '6' : '4', hashed ? "hashed " : "", 179 route ? "route" : "filter"); 180 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 181 ipa->mem_offset, mem->offset, offset_max); 182 183 return false; 184 } 185 186 if (mem->offset > ipa->mem_size || 187 mem->size > ipa->mem_size - mem->offset) { 188 dev_err(dev, "IPv%c %s%s table region out of range\n", 189 ipv6 ? '6' : '4', hashed ? "hashed " : "", 190 route ? "route" : "filter"); 191 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 192 mem->offset, mem->size, ipa->mem_size); 193 194 return false; 195 } 196 197 return true; 198 } 199 200 /* Validate the memory region that holds headers */ 201 static bool ipa_cmd_header_valid(struct ipa *ipa) 202 { 203 struct device *dev = &ipa->pdev->dev; 204 const struct ipa_mem *mem; 205 u32 offset_max; 206 u32 size_max; 207 u32 offset; 208 u32 size; 209 210 /* In ipa_cmd_hdr_init_local_add() we record the offset and size of 211 * the header table memory area in an immediate command. Make sure 212 * the offset and size fit in the fields that need to hold them, and 213 * that the entire range is within the overall IPA memory range. 214 */ 215 offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); 216 size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); 217 218 /* The header memory area contains both the modem and AP header 219 * regions. The modem portion defines the address of the region. 220 */ 221 mem = ipa_mem_find(ipa, IPA_MEM_MODEM_HEADER); 222 offset = mem->offset; 223 size = mem->size; 224 225 /* Make sure the offset fits in the IPA command */ 226 if (offset > offset_max || ipa->mem_offset > offset_max - offset) { 227 dev_err(dev, "header table region offset too large\n"); 228 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 229 ipa->mem_offset, offset, offset_max); 230 231 return false; 232 } 233 234 /* Add the size of the AP portion (if defined) to the combined size */ 235 mem = ipa_mem_find(ipa, IPA_MEM_AP_HEADER); 236 if (mem) 237 size += mem->size; 238 239 /* Make sure the combined size fits in the IPA command */ 240 if (size > size_max) { 241 dev_err(dev, "header table region size too large\n"); 242 dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max); 243 244 return false; 245 } 246 247 /* Make sure the entire combined area fits in IPA memory */ 248 if (size > ipa->mem_size || offset > ipa->mem_size - size) { 249 dev_err(dev, "header table region out of range\n"); 250 dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n", 251 offset, size, ipa->mem_size); 252 253 return false; 254 } 255 256 return true; 257 } 258 259 /* Indicate whether an offset can be used with a register_write command */ 260 static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa, 261 const char *name, u32 offset) 262 { 263 struct ipa_cmd_register_write *payload; 264 struct device *dev = &ipa->pdev->dev; 265 u32 offset_max; 266 u32 bit_count; 267 268 /* The maximum offset in a register_write immediate command depends 269 * on the version of IPA. A 16 bit offset is always supported, 270 * but starting with IPA v4.0 some additional high-order bits are 271 * allowed. 272 */ 273 bit_count = BITS_PER_BYTE * sizeof(payload->offset); 274 if (ipa->version >= IPA_VERSION_4_0) 275 bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); 276 BUILD_BUG_ON(bit_count > 32); 277 offset_max = ~0U >> (32 - bit_count); 278 279 /* Make sure the offset can be represented by the field(s) 280 * that holds it. Also make sure the offset is not outside 281 * the overall IPA memory range. 282 */ 283 if (offset > offset_max || ipa->mem_offset > offset_max - offset) { 284 dev_err(dev, "%s offset too large 0x%04x + 0x%04x > 0x%04x)\n", 285 name, ipa->mem_offset, offset, offset_max); 286 return false; 287 } 288 289 return true; 290 } 291 292 /* Check whether offsets passed to register_write are valid */ 293 static bool ipa_cmd_register_write_valid(struct ipa *ipa) 294 { 295 const char *name; 296 u32 offset; 297 298 /* If hashed tables are supported, ensure the hash flush register 299 * offset will fit in a register write IPA immediate command. 300 */ 301 if (ipa_table_hash_support(ipa)) { 302 offset = ipa_reg_filt_rout_hash_flush_offset(ipa->version); 303 name = "filter/route hash flush"; 304 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 305 return false; 306 } 307 308 /* Each endpoint can have a status endpoint associated with it, 309 * and this is recorded in an endpoint register. If the modem 310 * crashes, we reset the status endpoint for all modem endpoints 311 * using a register write IPA immediate command. Make sure the 312 * worst case (highest endpoint number) offset of that endpoint 313 * fits in the register write command field(s) that must hold it. 314 */ 315 offset = IPA_REG_ENDP_STATUS_N_OFFSET(IPA_ENDPOINT_COUNT - 1); 316 name = "maximal endpoint status"; 317 if (!ipa_cmd_register_write_offset_valid(ipa, name, offset)) 318 return false; 319 320 return true; 321 } 322 323 bool ipa_cmd_data_valid(struct ipa *ipa) 324 { 325 if (!ipa_cmd_header_valid(ipa)) 326 return false; 327 328 if (!ipa_cmd_register_write_valid(ipa)) 329 return false; 330 331 return true; 332 } 333 334 #endif /* IPA_VALIDATE */ 335 336 int ipa_cmd_pool_init(struct gsi_channel *channel, u32 tre_max) 337 { 338 struct gsi_trans_info *trans_info = &channel->trans_info; 339 struct device *dev = channel->gsi->dev; 340 int ret; 341 342 /* This is as good a place as any to validate build constants */ 343 ipa_cmd_validate_build(); 344 345 /* Even though command payloads are allocated one at a time, 346 * a single transaction can require up to tlv_count of them, 347 * so we treat them as if that many can be allocated at once. 348 */ 349 ret = gsi_trans_pool_init_dma(dev, &trans_info->cmd_pool, 350 sizeof(union ipa_cmd_payload), 351 tre_max, channel->tlv_count); 352 if (ret) 353 return ret; 354 355 /* Each TRE needs a command info structure */ 356 ret = gsi_trans_pool_init(&trans_info->info_pool, 357 sizeof(struct ipa_cmd_info), 358 tre_max, channel->tlv_count); 359 if (ret) 360 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); 361 362 return ret; 363 } 364 365 void ipa_cmd_pool_exit(struct gsi_channel *channel) 366 { 367 struct gsi_trans_info *trans_info = &channel->trans_info; 368 struct device *dev = channel->gsi->dev; 369 370 gsi_trans_pool_exit(&trans_info->info_pool); 371 gsi_trans_pool_exit_dma(dev, &trans_info->cmd_pool); 372 } 373 374 static union ipa_cmd_payload * 375 ipa_cmd_payload_alloc(struct ipa *ipa, dma_addr_t *addr) 376 { 377 struct gsi_trans_info *trans_info; 378 struct ipa_endpoint *endpoint; 379 380 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 381 trans_info = &ipa->gsi.channel[endpoint->channel_id].trans_info; 382 383 return gsi_trans_pool_alloc_dma(&trans_info->cmd_pool, addr); 384 } 385 386 /* If hash_size is 0, hash_offset and hash_addr ignored. */ 387 void ipa_cmd_table_init_add(struct gsi_trans *trans, 388 enum ipa_cmd_opcode opcode, u16 size, u32 offset, 389 dma_addr_t addr, u16 hash_size, u32 hash_offset, 390 dma_addr_t hash_addr) 391 { 392 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 393 enum dma_data_direction direction = DMA_TO_DEVICE; 394 struct ipa_cmd_hw_ip_fltrt_init *payload; 395 union ipa_cmd_payload *cmd_payload; 396 dma_addr_t payload_addr; 397 u64 val; 398 399 /* Record the non-hash table offset and size */ 400 offset += ipa->mem_offset; 401 val = u64_encode_bits(offset, IP_FLTRT_FLAGS_NHASH_ADDR_FMASK); 402 val |= u64_encode_bits(size, IP_FLTRT_FLAGS_NHASH_SIZE_FMASK); 403 404 /* The hash table offset and address are zero if its size is 0 */ 405 if (hash_size) { 406 /* Record the hash table offset and size */ 407 hash_offset += ipa->mem_offset; 408 val |= u64_encode_bits(hash_offset, 409 IP_FLTRT_FLAGS_HASH_ADDR_FMASK); 410 val |= u64_encode_bits(hash_size, 411 IP_FLTRT_FLAGS_HASH_SIZE_FMASK); 412 } 413 414 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 415 payload = &cmd_payload->table_init; 416 417 /* Fill in all offsets and sizes and the non-hash table address */ 418 if (hash_size) 419 payload->hash_rules_addr = cpu_to_le64(hash_addr); 420 payload->flags = cpu_to_le64(val); 421 payload->nhash_rules_addr = cpu_to_le64(addr); 422 423 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 424 direction, opcode); 425 } 426 427 /* Initialize header space in IPA-local memory */ 428 void ipa_cmd_hdr_init_local_add(struct gsi_trans *trans, u32 offset, u16 size, 429 dma_addr_t addr) 430 { 431 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 432 enum ipa_cmd_opcode opcode = IPA_CMD_HDR_INIT_LOCAL; 433 enum dma_data_direction direction = DMA_TO_DEVICE; 434 struct ipa_cmd_hw_hdr_init_local *payload; 435 union ipa_cmd_payload *cmd_payload; 436 dma_addr_t payload_addr; 437 u32 flags; 438 439 offset += ipa->mem_offset; 440 441 /* With this command we tell the IPA where in its local memory the 442 * header tables reside. The content of the buffer provided is 443 * also written via DMA into that space. The IPA hardware owns 444 * the table, but the AP must initialize it. 445 */ 446 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 447 payload = &cmd_payload->hdr_init_local; 448 449 payload->hdr_table_addr = cpu_to_le64(addr); 450 flags = u32_encode_bits(size, HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK); 451 flags |= u32_encode_bits(offset, HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK); 452 payload->flags = cpu_to_le32(flags); 453 454 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 455 direction, opcode); 456 } 457 458 void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value, 459 u32 mask, bool clear_full) 460 { 461 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 462 struct ipa_cmd_register_write *payload; 463 union ipa_cmd_payload *cmd_payload; 464 u32 opcode = IPA_CMD_REGISTER_WRITE; 465 dma_addr_t payload_addr; 466 u32 clear_option; 467 u32 options; 468 u16 flags; 469 470 /* pipeline_clear_src_grp is not used */ 471 clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps; 472 473 /* IPA v4.0+ represents the pipeline clear options in the opcode. It 474 * also supports a larger offset by encoding additional high-order 475 * bits in the payload flags field. 476 */ 477 if (ipa->version >= IPA_VERSION_4_0) { 478 u16 offset_high; 479 u32 val; 480 481 /* Opcode encodes pipeline clear options */ 482 /* SKIP_CLEAR is always 0 (don't skip pipeline clear) */ 483 val = u16_encode_bits(clear_option, 484 REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK); 485 opcode |= val; 486 487 /* Extract the high 4 bits from the offset */ 488 offset_high = (u16)u32_get_bits(offset, GENMASK(19, 16)); 489 offset &= (1 << 16) - 1; 490 491 /* Extract the top 4 bits and encode it into the flags field */ 492 flags = u16_encode_bits(offset_high, 493 REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK); 494 options = 0; /* reserved */ 495 496 } else { 497 flags = 0; /* SKIP_CLEAR flag is always 0 */ 498 options = u16_encode_bits(clear_option, 499 REGISTER_WRITE_CLEAR_OPTIONS_FMASK); 500 } 501 502 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 503 payload = &cmd_payload->register_write; 504 505 payload->flags = cpu_to_le16(flags); 506 payload->offset = cpu_to_le16((u16)offset); 507 payload->value = cpu_to_le32(value); 508 payload->value_mask = cpu_to_le32(mask); 509 payload->clear_options = cpu_to_le32(options); 510 511 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 512 DMA_NONE, opcode); 513 } 514 515 /* Skip IP packet processing on the next data transfer on a TX channel */ 516 static void ipa_cmd_ip_packet_init_add(struct gsi_trans *trans, u8 endpoint_id) 517 { 518 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 519 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_INIT; 520 enum dma_data_direction direction = DMA_TO_DEVICE; 521 struct ipa_cmd_ip_packet_init *payload; 522 union ipa_cmd_payload *cmd_payload; 523 dma_addr_t payload_addr; 524 525 /* assert(endpoint_id < 526 field_max(IPA_PACKET_INIT_DEST_ENDPOINT_FMASK)); */ 527 528 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 529 payload = &cmd_payload->ip_packet_init; 530 531 payload->dest_endpoint = u8_encode_bits(endpoint_id, 532 IPA_PACKET_INIT_DEST_ENDPOINT_FMASK); 533 534 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 535 direction, opcode); 536 } 537 538 /* Use a DMA command to read or write a block of IPA-resident memory */ 539 void ipa_cmd_dma_shared_mem_add(struct gsi_trans *trans, u32 offset, u16 size, 540 dma_addr_t addr, bool toward_ipa) 541 { 542 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 543 enum ipa_cmd_opcode opcode = IPA_CMD_DMA_SHARED_MEM; 544 struct ipa_cmd_hw_dma_mem_mem *payload; 545 union ipa_cmd_payload *cmd_payload; 546 enum dma_data_direction direction; 547 dma_addr_t payload_addr; 548 u16 flags; 549 550 /* size and offset must fit in 16 bit fields */ 551 /* assert(size > 0 && size <= U16_MAX); */ 552 /* assert(offset <= U16_MAX && ipa->mem_offset <= U16_MAX - offset); */ 553 554 offset += ipa->mem_offset; 555 556 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 557 payload = &cmd_payload->dma_shared_mem; 558 559 /* payload->clear_after_read was reserved prior to IPA v4.0. It's 560 * never needed for current code, so it's 0 regardless of version. 561 */ 562 payload->size = cpu_to_le16(size); 563 payload->local_addr = cpu_to_le16(offset); 564 /* payload->flags: 565 * direction: 0 = write to IPA, 1 read from IPA 566 * Starting at v4.0 these are reserved; either way, all zero: 567 * pipeline clear: 0 = wait for pipeline clear (don't skip) 568 * clear_options: 0 = pipeline_clear_hps 569 * Instead, for v4.0+ these are encoded in the opcode. But again 570 * since both values are 0 we won't bother OR'ing them in. 571 */ 572 flags = toward_ipa ? 0 : DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK; 573 payload->flags = cpu_to_le16(flags); 574 payload->system_addr = cpu_to_le64(addr); 575 576 direction = toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 577 578 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 579 direction, opcode); 580 } 581 582 static void ipa_cmd_ip_tag_status_add(struct gsi_trans *trans) 583 { 584 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 585 enum ipa_cmd_opcode opcode = IPA_CMD_IP_PACKET_TAG_STATUS; 586 enum dma_data_direction direction = DMA_TO_DEVICE; 587 struct ipa_cmd_ip_packet_tag_status *payload; 588 union ipa_cmd_payload *cmd_payload; 589 dma_addr_t payload_addr; 590 591 /* assert(tag <= field_max(IP_PACKET_TAG_STATUS_TAG_FMASK)); */ 592 593 cmd_payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 594 payload = &cmd_payload->ip_packet_tag_status; 595 596 payload->tag = le64_encode_bits(0, IP_PACKET_TAG_STATUS_TAG_FMASK); 597 598 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 599 direction, opcode); 600 } 601 602 /* Issue a small command TX data transfer */ 603 static void ipa_cmd_transfer_add(struct gsi_trans *trans) 604 { 605 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 606 enum dma_data_direction direction = DMA_TO_DEVICE; 607 enum ipa_cmd_opcode opcode = IPA_CMD_NONE; 608 union ipa_cmd_payload *payload; 609 dma_addr_t payload_addr; 610 611 /* Just transfer a zero-filled payload structure */ 612 payload = ipa_cmd_payload_alloc(ipa, &payload_addr); 613 614 gsi_trans_cmd_add(trans, payload, sizeof(*payload), payload_addr, 615 direction, opcode); 616 } 617 618 /* Add immediate commands to a transaction to clear the hardware pipeline */ 619 void ipa_cmd_pipeline_clear_add(struct gsi_trans *trans) 620 { 621 struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); 622 struct ipa_endpoint *endpoint; 623 624 /* This will complete when the transfer is received */ 625 reinit_completion(&ipa->completion); 626 627 /* Issue a no-op register write command (mask 0 means no write) */ 628 ipa_cmd_register_write_add(trans, 0, 0, 0, true); 629 630 /* Send a data packet through the IPA pipeline. The packet_init 631 * command says to send the next packet directly to the exception 632 * endpoint without any other IPA processing. The tag_status 633 * command requests that status be generated on completion of 634 * that transfer, and that it will be tagged with a value. 635 * Finally, the transfer command sends a small packet of data 636 * (instead of a command) using the command endpoint. 637 */ 638 endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 639 ipa_cmd_ip_packet_init_add(trans, endpoint->endpoint_id); 640 ipa_cmd_ip_tag_status_add(trans); 641 ipa_cmd_transfer_add(trans); 642 } 643 644 /* Returns the number of commands required to clear the pipeline */ 645 u32 ipa_cmd_pipeline_clear_count(void) 646 { 647 return 4; 648 } 649 650 void ipa_cmd_pipeline_clear_wait(struct ipa *ipa) 651 { 652 wait_for_completion(&ipa->completion); 653 } 654 655 void ipa_cmd_pipeline_clear(struct ipa *ipa) 656 { 657 u32 count = ipa_cmd_pipeline_clear_count(); 658 struct gsi_trans *trans; 659 660 trans = ipa_cmd_trans_alloc(ipa, count); 661 if (trans) { 662 ipa_cmd_pipeline_clear_add(trans); 663 gsi_trans_commit_wait(trans); 664 ipa_cmd_pipeline_clear_wait(ipa); 665 } else { 666 dev_err(&ipa->pdev->dev, 667 "error allocating %u entry tag transaction\n", count); 668 } 669 } 670 671 static struct ipa_cmd_info * 672 ipa_cmd_info_alloc(struct ipa_endpoint *endpoint, u32 tre_count) 673 { 674 struct gsi_channel *channel; 675 676 channel = &endpoint->ipa->gsi.channel[endpoint->channel_id]; 677 678 return gsi_trans_pool_alloc(&channel->trans_info.info_pool, tre_count); 679 } 680 681 /* Allocate a transaction for the command TX endpoint */ 682 struct gsi_trans *ipa_cmd_trans_alloc(struct ipa *ipa, u32 tre_count) 683 { 684 struct ipa_endpoint *endpoint; 685 struct gsi_trans *trans; 686 687 endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 688 689 trans = gsi_channel_trans_alloc(&ipa->gsi, endpoint->channel_id, 690 tre_count, DMA_NONE); 691 if (trans) 692 trans->info = ipa_cmd_info_alloc(endpoint, tre_count); 693 694 return trans; 695 } 696