19dd441e4SAlex Elder // SPDX-License-Identifier: GPL-2.0 29dd441e4SAlex Elder 39dd441e4SAlex Elder /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 49dd441e4SAlex Elder * Copyright (C) 2019-2020 Linaro Ltd. 59dd441e4SAlex Elder */ 69dd441e4SAlex Elder 79dd441e4SAlex Elder #include <linux/types.h> 89dd441e4SAlex Elder #include <linux/bits.h> 99dd441e4SAlex Elder #include <linux/bitfield.h> 109dd441e4SAlex Elder #include <linux/refcount.h> 119dd441e4SAlex Elder #include <linux/scatterlist.h> 129dd441e4SAlex Elder #include <linux/dma-direction.h> 139dd441e4SAlex Elder 149dd441e4SAlex Elder #include "gsi.h" 159dd441e4SAlex Elder #include "gsi_private.h" 169dd441e4SAlex Elder #include "gsi_trans.h" 179dd441e4SAlex Elder #include "ipa_gsi.h" 189dd441e4SAlex Elder #include "ipa_data.h" 199dd441e4SAlex Elder #include "ipa_cmd.h" 209dd441e4SAlex Elder 219dd441e4SAlex Elder /** 229dd441e4SAlex Elder * DOC: GSI Transactions 239dd441e4SAlex Elder * 249dd441e4SAlex Elder * A GSI transaction abstracts the behavior of a GSI channel by representing 259dd441e4SAlex Elder * everything about a related group of IPA commands in a single structure. 269dd441e4SAlex Elder * (A "command" in this sense is either a data transfer or an IPA immediate 279dd441e4SAlex Elder * command.) Most details of interaction with the GSI hardware are managed 289dd441e4SAlex Elder * by the GSI transaction core, allowing users to simply describe commands 299dd441e4SAlex Elder * to be performed. When a transaction has completed a callback function 309dd441e4SAlex Elder * (dependent on the type of endpoint associated with the channel) allows 319dd441e4SAlex Elder * cleanup of resources associated with the transaction. 329dd441e4SAlex Elder * 339dd441e4SAlex Elder * To perform a command (or set of them), a user of the GSI transaction 349dd441e4SAlex Elder * interface allocates a transaction, indicating the number of TREs required 359dd441e4SAlex Elder * (one per command). If sufficient TREs are available, they are reserved 369dd441e4SAlex Elder * for use in the transaction and the allocation succeeds. This way 379dd441e4SAlex Elder * exhaustion of the available TREs in a channel ring is detected 389dd441e4SAlex Elder * as early as possible. All resources required to complete a transaction 399dd441e4SAlex Elder * are allocated at transaction allocation time. 409dd441e4SAlex Elder * 419dd441e4SAlex Elder * Commands performed as part of a transaction are represented in an array 429dd441e4SAlex Elder * of Linux scatterlist structures. This array is allocated with the 439dd441e4SAlex Elder * transaction, and its entries are initialized using standard scatterlist 449dd441e4SAlex Elder * functions (such as sg_set_buf() or skb_to_sgvec()). 459dd441e4SAlex Elder * 469dd441e4SAlex Elder * Once a transaction's scatterlist structures have been initialized, the 479dd441e4SAlex Elder * transaction is committed. The caller is responsible for mapping buffers 489dd441e4SAlex Elder * for DMA if necessary, and this should be done *before* allocating 499dd441e4SAlex Elder * the transaction. Between a successful allocation and commit of a 509dd441e4SAlex Elder * transaction no errors should occur. 519dd441e4SAlex Elder * 529dd441e4SAlex Elder * Committing transfers ownership of the entire transaction to the GSI 539dd441e4SAlex Elder * transaction core. The GSI transaction code formats the content of 549dd441e4SAlex Elder * the scatterlist array into the channel ring buffer and informs the 559dd441e4SAlex Elder * hardware that new TREs are available to process. 569dd441e4SAlex Elder * 579dd441e4SAlex Elder * The last TRE in each transaction is marked to interrupt the AP when the 589dd441e4SAlex Elder * GSI hardware has completed it. Because transfers described by TREs are 599dd441e4SAlex Elder * performed strictly in order, signaling the completion of just the last 609dd441e4SAlex Elder * TRE in the transaction is sufficient to indicate the full transaction 619dd441e4SAlex Elder * is complete. 629dd441e4SAlex Elder * 639dd441e4SAlex Elder * When a transaction is complete, ipa_gsi_trans_complete() is called by the 649dd441e4SAlex Elder * GSI code into the IPA layer, allowing it to perform any final cleanup 659dd441e4SAlex Elder * required before the transaction is freed. 669dd441e4SAlex Elder */ 679dd441e4SAlex Elder 689dd441e4SAlex Elder /* Hardware values representing a transfer element type */ 699dd441e4SAlex Elder enum gsi_tre_type { 709dd441e4SAlex Elder GSI_RE_XFER = 0x2, 719dd441e4SAlex Elder GSI_RE_IMMD_CMD = 0x3, 729dd441e4SAlex Elder }; 739dd441e4SAlex Elder 749dd441e4SAlex Elder /* An entry in a channel ring */ 759dd441e4SAlex Elder struct gsi_tre { 769dd441e4SAlex Elder __le64 addr; /* DMA address */ 779dd441e4SAlex Elder __le16 len_opcode; /* length in bytes or enum IPA_CMD_* */ 789dd441e4SAlex Elder __le16 reserved; 799dd441e4SAlex Elder __le32 flags; /* TRE_FLAGS_* */ 809dd441e4SAlex Elder }; 819dd441e4SAlex Elder 829dd441e4SAlex Elder /* gsi_tre->flags mask values (in CPU byte order) */ 839dd441e4SAlex Elder #define TRE_FLAGS_CHAIN_FMASK GENMASK(0, 0) 849dd441e4SAlex Elder #define TRE_FLAGS_IEOT_FMASK GENMASK(9, 9) 859dd441e4SAlex Elder #define TRE_FLAGS_BEI_FMASK GENMASK(10, 10) 869dd441e4SAlex Elder #define TRE_FLAGS_TYPE_FMASK GENMASK(23, 16) 879dd441e4SAlex Elder 889dd441e4SAlex Elder int gsi_trans_pool_init(struct gsi_trans_pool *pool, size_t size, u32 count, 899dd441e4SAlex Elder u32 max_alloc) 909dd441e4SAlex Elder { 919dd441e4SAlex Elder void *virt; 929dd441e4SAlex Elder 939dd441e4SAlex Elder #ifdef IPA_VALIDATE 94*7ad3bd52SAlex Elder if (!size) 959dd441e4SAlex Elder return -EINVAL; 969dd441e4SAlex Elder if (count < max_alloc) 979dd441e4SAlex Elder return -EINVAL; 989dd441e4SAlex Elder if (!max_alloc) 999dd441e4SAlex Elder return -EINVAL; 1009dd441e4SAlex Elder #endif /* IPA_VALIDATE */ 1019dd441e4SAlex Elder 1029dd441e4SAlex Elder /* By allocating a few extra entries in our pool (one less 1039dd441e4SAlex Elder * than the maximum number that will be requested in a 1049dd441e4SAlex Elder * single allocation), we can always satisfy requests without 1059dd441e4SAlex Elder * ever worrying about straddling the end of the pool array. 1069dd441e4SAlex Elder * If there aren't enough entries starting at the free index, 1079dd441e4SAlex Elder * we just allocate free entries from the beginning of the pool. 1089dd441e4SAlex Elder */ 1099dd441e4SAlex Elder virt = kcalloc(count + max_alloc - 1, size, GFP_KERNEL); 1109dd441e4SAlex Elder if (!virt) 1119dd441e4SAlex Elder return -ENOMEM; 1129dd441e4SAlex Elder 1139dd441e4SAlex Elder pool->base = virt; 1149dd441e4SAlex Elder /* If the allocator gave us any extra memory, use it */ 1159dd441e4SAlex Elder pool->count = ksize(pool->base) / size; 1169dd441e4SAlex Elder pool->free = 0; 1179dd441e4SAlex Elder pool->max_alloc = max_alloc; 1189dd441e4SAlex Elder pool->size = size; 1199dd441e4SAlex Elder pool->addr = 0; /* Only used for DMA pools */ 1209dd441e4SAlex Elder 1219dd441e4SAlex Elder return 0; 1229dd441e4SAlex Elder } 1239dd441e4SAlex Elder 1249dd441e4SAlex Elder void gsi_trans_pool_exit(struct gsi_trans_pool *pool) 1259dd441e4SAlex Elder { 1269dd441e4SAlex Elder kfree(pool->base); 1279dd441e4SAlex Elder memset(pool, 0, sizeof(*pool)); 1289dd441e4SAlex Elder } 1299dd441e4SAlex Elder 1309dd441e4SAlex Elder /* Allocate the requested number of (zeroed) entries from the pool */ 1319dd441e4SAlex Elder /* Home-grown DMA pool. This way we can preallocate and use the tre_count 1329dd441e4SAlex Elder * to guarantee allocations will succeed. Even though we specify max_alloc 1339dd441e4SAlex Elder * (and it can be more than one), we only allow allocation of a single 1349dd441e4SAlex Elder * element from a DMA pool. 1359dd441e4SAlex Elder */ 1369dd441e4SAlex Elder int gsi_trans_pool_init_dma(struct device *dev, struct gsi_trans_pool *pool, 1379dd441e4SAlex Elder size_t size, u32 count, u32 max_alloc) 1389dd441e4SAlex Elder { 1399dd441e4SAlex Elder size_t total_size; 1409dd441e4SAlex Elder dma_addr_t addr; 1419dd441e4SAlex Elder void *virt; 1429dd441e4SAlex Elder 1439dd441e4SAlex Elder #ifdef IPA_VALIDATE 144*7ad3bd52SAlex Elder if (!size) 1459dd441e4SAlex Elder return -EINVAL; 1469dd441e4SAlex Elder if (count < max_alloc) 1479dd441e4SAlex Elder return -EINVAL; 1489dd441e4SAlex Elder if (!max_alloc) 1499dd441e4SAlex Elder return -EINVAL; 1509dd441e4SAlex Elder #endif /* IPA_VALIDATE */ 1519dd441e4SAlex Elder 1529dd441e4SAlex Elder /* Don't let allocations cross a power-of-two boundary */ 1539dd441e4SAlex Elder size = __roundup_pow_of_two(size); 1549dd441e4SAlex Elder total_size = (count + max_alloc - 1) * size; 1559dd441e4SAlex Elder 15619aaf72cSAlex Elder /* The allocator will give us a power-of-2 number of pages 15719aaf72cSAlex Elder * sufficient to satisfy our request. Round up our requested 15819aaf72cSAlex Elder * size to avoid any unused space in the allocation. This way 15919aaf72cSAlex Elder * gsi_trans_pool_exit_dma() can assume the total allocated 1601130b252SAlex Elder * size is exactly (count * size). 1619dd441e4SAlex Elder */ 1629dd441e4SAlex Elder total_size = get_order(total_size) << PAGE_SHIFT; 1639dd441e4SAlex Elder 1649dd441e4SAlex Elder virt = dma_alloc_coherent(dev, total_size, &addr, GFP_KERNEL); 1659dd441e4SAlex Elder if (!virt) 1669dd441e4SAlex Elder return -ENOMEM; 1679dd441e4SAlex Elder 1689dd441e4SAlex Elder pool->base = virt; 1699dd441e4SAlex Elder pool->count = total_size / size; 1709dd441e4SAlex Elder pool->free = 0; 1719dd441e4SAlex Elder pool->size = size; 1729dd441e4SAlex Elder pool->max_alloc = max_alloc; 1739dd441e4SAlex Elder pool->addr = addr; 1749dd441e4SAlex Elder 1759dd441e4SAlex Elder return 0; 1769dd441e4SAlex Elder } 1779dd441e4SAlex Elder 1789dd441e4SAlex Elder void gsi_trans_pool_exit_dma(struct device *dev, struct gsi_trans_pool *pool) 1799dd441e4SAlex Elder { 1801130b252SAlex Elder size_t total_size = pool->count * pool->size; 1811130b252SAlex Elder 1821130b252SAlex Elder dma_free_coherent(dev, total_size, pool->base, pool->addr); 1839dd441e4SAlex Elder memset(pool, 0, sizeof(*pool)); 1849dd441e4SAlex Elder } 1859dd441e4SAlex Elder 1869dd441e4SAlex Elder /* Return the byte offset of the next free entry in the pool */ 1879dd441e4SAlex Elder static u32 gsi_trans_pool_alloc_common(struct gsi_trans_pool *pool, u32 count) 1889dd441e4SAlex Elder { 1899dd441e4SAlex Elder u32 offset; 1909dd441e4SAlex Elder 1919dd441e4SAlex Elder /* assert(count > 0); */ 1929dd441e4SAlex Elder /* assert(count <= pool->max_alloc); */ 1939dd441e4SAlex Elder 1949dd441e4SAlex Elder /* Allocate from beginning if wrap would occur */ 1959dd441e4SAlex Elder if (count > pool->count - pool->free) 1969dd441e4SAlex Elder pool->free = 0; 1979dd441e4SAlex Elder 1989dd441e4SAlex Elder offset = pool->free * pool->size; 1999dd441e4SAlex Elder pool->free += count; 2009dd441e4SAlex Elder memset(pool->base + offset, 0, count * pool->size); 2019dd441e4SAlex Elder 2029dd441e4SAlex Elder return offset; 2039dd441e4SAlex Elder } 2049dd441e4SAlex Elder 2059dd441e4SAlex Elder /* Allocate a contiguous block of zeroed entries from a pool */ 2069dd441e4SAlex Elder void *gsi_trans_pool_alloc(struct gsi_trans_pool *pool, u32 count) 2079dd441e4SAlex Elder { 2089dd441e4SAlex Elder return pool->base + gsi_trans_pool_alloc_common(pool, count); 2099dd441e4SAlex Elder } 2109dd441e4SAlex Elder 2119dd441e4SAlex Elder /* Allocate a single zeroed entry from a DMA pool */ 2129dd441e4SAlex Elder void *gsi_trans_pool_alloc_dma(struct gsi_trans_pool *pool, dma_addr_t *addr) 2139dd441e4SAlex Elder { 2149dd441e4SAlex Elder u32 offset = gsi_trans_pool_alloc_common(pool, 1); 2159dd441e4SAlex Elder 2169dd441e4SAlex Elder *addr = pool->addr + offset; 2179dd441e4SAlex Elder 2189dd441e4SAlex Elder return pool->base + offset; 2199dd441e4SAlex Elder } 2209dd441e4SAlex Elder 2219dd441e4SAlex Elder /* Return the pool element that immediately follows the one given. 2229dd441e4SAlex Elder * This only works done if elements are allocated one at a time. 2239dd441e4SAlex Elder */ 2249dd441e4SAlex Elder void *gsi_trans_pool_next(struct gsi_trans_pool *pool, void *element) 2259dd441e4SAlex Elder { 2269dd441e4SAlex Elder void *end = pool->base + pool->count * pool->size; 2279dd441e4SAlex Elder 2289dd441e4SAlex Elder /* assert(element >= pool->base); */ 2299dd441e4SAlex Elder /* assert(element < end); */ 2309dd441e4SAlex Elder /* assert(pool->max_alloc == 1); */ 2319dd441e4SAlex Elder element += pool->size; 2329dd441e4SAlex Elder 2339dd441e4SAlex Elder return element < end ? element : pool->base; 2349dd441e4SAlex Elder } 2359dd441e4SAlex Elder 2369dd441e4SAlex Elder /* Map a given ring entry index to the transaction associated with it */ 2379dd441e4SAlex Elder static void gsi_channel_trans_map(struct gsi_channel *channel, u32 index, 2389dd441e4SAlex Elder struct gsi_trans *trans) 2399dd441e4SAlex Elder { 2409dd441e4SAlex Elder /* Note: index *must* be used modulo the ring count here */ 2419dd441e4SAlex Elder channel->trans_info.map[index % channel->tre_ring.count] = trans; 2429dd441e4SAlex Elder } 2439dd441e4SAlex Elder 2449dd441e4SAlex Elder /* Return the transaction mapped to a given ring entry */ 2459dd441e4SAlex Elder struct gsi_trans * 2469dd441e4SAlex Elder gsi_channel_trans_mapped(struct gsi_channel *channel, u32 index) 2479dd441e4SAlex Elder { 2489dd441e4SAlex Elder /* Note: index *must* be used modulo the ring count here */ 2499dd441e4SAlex Elder return channel->trans_info.map[index % channel->tre_ring.count]; 2509dd441e4SAlex Elder } 2519dd441e4SAlex Elder 2529dd441e4SAlex Elder /* Return the oldest completed transaction for a channel (or null) */ 2539dd441e4SAlex Elder struct gsi_trans *gsi_channel_trans_complete(struct gsi_channel *channel) 2549dd441e4SAlex Elder { 2559dd441e4SAlex Elder return list_first_entry_or_null(&channel->trans_info.complete, 2569dd441e4SAlex Elder struct gsi_trans, links); 2579dd441e4SAlex Elder } 2589dd441e4SAlex Elder 2599dd441e4SAlex Elder /* Move a transaction from the allocated list to the pending list */ 2609dd441e4SAlex Elder static void gsi_trans_move_pending(struct gsi_trans *trans) 2619dd441e4SAlex Elder { 2629dd441e4SAlex Elder struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; 2639dd441e4SAlex Elder struct gsi_trans_info *trans_info = &channel->trans_info; 2649dd441e4SAlex Elder 2659dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 2669dd441e4SAlex Elder 2679dd441e4SAlex Elder list_move_tail(&trans->links, &trans_info->pending); 2689dd441e4SAlex Elder 2699dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 2709dd441e4SAlex Elder } 2719dd441e4SAlex Elder 2729dd441e4SAlex Elder /* Move a transaction and all of its predecessors from the pending list 2739dd441e4SAlex Elder * to the completed list. 2749dd441e4SAlex Elder */ 2759dd441e4SAlex Elder void gsi_trans_move_complete(struct gsi_trans *trans) 2769dd441e4SAlex Elder { 2779dd441e4SAlex Elder struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; 2789dd441e4SAlex Elder struct gsi_trans_info *trans_info = &channel->trans_info; 2799dd441e4SAlex Elder struct list_head list; 2809dd441e4SAlex Elder 2819dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 2829dd441e4SAlex Elder 2839dd441e4SAlex Elder /* Move this transaction and all predecessors to completed list */ 2849dd441e4SAlex Elder list_cut_position(&list, &trans_info->pending, &trans->links); 2859dd441e4SAlex Elder list_splice_tail(&list, &trans_info->complete); 2869dd441e4SAlex Elder 2879dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 2889dd441e4SAlex Elder } 2899dd441e4SAlex Elder 2909dd441e4SAlex Elder /* Move a transaction from the completed list to the polled list */ 2919dd441e4SAlex Elder void gsi_trans_move_polled(struct gsi_trans *trans) 2929dd441e4SAlex Elder { 2939dd441e4SAlex Elder struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; 2949dd441e4SAlex Elder struct gsi_trans_info *trans_info = &channel->trans_info; 2959dd441e4SAlex Elder 2969dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 2979dd441e4SAlex Elder 2989dd441e4SAlex Elder list_move_tail(&trans->links, &trans_info->polled); 2999dd441e4SAlex Elder 3009dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 3019dd441e4SAlex Elder } 3029dd441e4SAlex Elder 3039dd441e4SAlex Elder /* Reserve some number of TREs on a channel. Returns true if successful */ 3049dd441e4SAlex Elder static bool 3059dd441e4SAlex Elder gsi_trans_tre_reserve(struct gsi_trans_info *trans_info, u32 tre_count) 3069dd441e4SAlex Elder { 3079dd441e4SAlex Elder int avail = atomic_read(&trans_info->tre_avail); 3089dd441e4SAlex Elder int new; 3099dd441e4SAlex Elder 3109dd441e4SAlex Elder do { 3119dd441e4SAlex Elder new = avail - (int)tre_count; 3129dd441e4SAlex Elder if (unlikely(new < 0)) 3139dd441e4SAlex Elder return false; 3149dd441e4SAlex Elder } while (!atomic_try_cmpxchg(&trans_info->tre_avail, &avail, new)); 3159dd441e4SAlex Elder 3169dd441e4SAlex Elder return true; 3179dd441e4SAlex Elder } 3189dd441e4SAlex Elder 3199dd441e4SAlex Elder /* Release previously-reserved TRE entries to a channel */ 3209dd441e4SAlex Elder static void 3219dd441e4SAlex Elder gsi_trans_tre_release(struct gsi_trans_info *trans_info, u32 tre_count) 3229dd441e4SAlex Elder { 3239dd441e4SAlex Elder atomic_add(tre_count, &trans_info->tre_avail); 3249dd441e4SAlex Elder } 3259dd441e4SAlex Elder 3269dd441e4SAlex Elder /* Allocate a GSI transaction on a channel */ 3279dd441e4SAlex Elder struct gsi_trans *gsi_channel_trans_alloc(struct gsi *gsi, u32 channel_id, 3289dd441e4SAlex Elder u32 tre_count, 3299dd441e4SAlex Elder enum dma_data_direction direction) 3309dd441e4SAlex Elder { 3319dd441e4SAlex Elder struct gsi_channel *channel = &gsi->channel[channel_id]; 3329dd441e4SAlex Elder struct gsi_trans_info *trans_info; 3339dd441e4SAlex Elder struct gsi_trans *trans; 3349dd441e4SAlex Elder 3359dd441e4SAlex Elder /* assert(tre_count <= gsi_channel_trans_tre_max(gsi, channel_id)); */ 3369dd441e4SAlex Elder 3379dd441e4SAlex Elder trans_info = &channel->trans_info; 3389dd441e4SAlex Elder 3399dd441e4SAlex Elder /* We reserve the TREs now, but consume them at commit time. 3409dd441e4SAlex Elder * If there aren't enough available, we're done. 3419dd441e4SAlex Elder */ 3429dd441e4SAlex Elder if (!gsi_trans_tre_reserve(trans_info, tre_count)) 3439dd441e4SAlex Elder return NULL; 3449dd441e4SAlex Elder 3459dd441e4SAlex Elder /* Allocate and initialize non-zero fields in the the transaction */ 3469dd441e4SAlex Elder trans = gsi_trans_pool_alloc(&trans_info->pool, 1); 3479dd441e4SAlex Elder trans->gsi = gsi; 3489dd441e4SAlex Elder trans->channel_id = channel_id; 3499dd441e4SAlex Elder trans->tre_count = tre_count; 3509dd441e4SAlex Elder init_completion(&trans->completion); 3519dd441e4SAlex Elder 3529dd441e4SAlex Elder /* Allocate the scatterlist and (if requested) info entries. */ 3539dd441e4SAlex Elder trans->sgl = gsi_trans_pool_alloc(&trans_info->sg_pool, tre_count); 3549dd441e4SAlex Elder sg_init_marker(trans->sgl, tre_count); 3559dd441e4SAlex Elder 3569dd441e4SAlex Elder trans->direction = direction; 3579dd441e4SAlex Elder 3589dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 3599dd441e4SAlex Elder 3609dd441e4SAlex Elder list_add_tail(&trans->links, &trans_info->alloc); 3619dd441e4SAlex Elder 3629dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 3639dd441e4SAlex Elder 3649dd441e4SAlex Elder refcount_set(&trans->refcount, 1); 3659dd441e4SAlex Elder 3669dd441e4SAlex Elder return trans; 3679dd441e4SAlex Elder } 3689dd441e4SAlex Elder 369064c9c32SAlex Elder /* Free a previously-allocated transaction */ 3709dd441e4SAlex Elder void gsi_trans_free(struct gsi_trans *trans) 3719dd441e4SAlex Elder { 372064c9c32SAlex Elder refcount_t *refcount = &trans->refcount; 3739dd441e4SAlex Elder struct gsi_trans_info *trans_info; 374064c9c32SAlex Elder bool last; 3759dd441e4SAlex Elder 376064c9c32SAlex Elder /* We must hold the lock to release the last reference */ 377064c9c32SAlex Elder if (refcount_dec_not_one(refcount)) 3789dd441e4SAlex Elder return; 3799dd441e4SAlex Elder 3809dd441e4SAlex Elder trans_info = &trans->gsi->channel[trans->channel_id].trans_info; 3819dd441e4SAlex Elder 3829dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 3839dd441e4SAlex Elder 384064c9c32SAlex Elder /* Reference might have been added before we got the lock */ 385064c9c32SAlex Elder last = refcount_dec_and_test(refcount); 386064c9c32SAlex Elder if (last) 3879dd441e4SAlex Elder list_del(&trans->links); 3889dd441e4SAlex Elder 3899dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 3909dd441e4SAlex Elder 391064c9c32SAlex Elder if (!last) 392064c9c32SAlex Elder return; 393064c9c32SAlex Elder 3949dd441e4SAlex Elder ipa_gsi_trans_release(trans); 3959dd441e4SAlex Elder 3969dd441e4SAlex Elder /* Releasing the reserved TREs implicitly frees the sgl[] and 3979dd441e4SAlex Elder * (if present) info[] arrays, plus the transaction itself. 3989dd441e4SAlex Elder */ 3999dd441e4SAlex Elder gsi_trans_tre_release(trans_info, trans->tre_count); 4009dd441e4SAlex Elder } 4019dd441e4SAlex Elder 4029dd441e4SAlex Elder /* Add an immediate command to a transaction */ 4039dd441e4SAlex Elder void gsi_trans_cmd_add(struct gsi_trans *trans, void *buf, u32 size, 4049dd441e4SAlex Elder dma_addr_t addr, enum dma_data_direction direction, 4059dd441e4SAlex Elder enum ipa_cmd_opcode opcode) 4069dd441e4SAlex Elder { 4079dd441e4SAlex Elder struct ipa_cmd_info *info; 4089dd441e4SAlex Elder u32 which = trans->used++; 4099dd441e4SAlex Elder struct scatterlist *sg; 4109dd441e4SAlex Elder 4119dd441e4SAlex Elder /* assert(which < trans->tre_count); */ 4129dd441e4SAlex Elder 413df833050SAlex Elder /* Commands are quite different from data transfer requests. 414df833050SAlex Elder * Their payloads come from a pool whose memory is allocated 415df833050SAlex Elder * using dma_alloc_coherent(). We therefore do *not* map them 416df833050SAlex Elder * for DMA (unlike what we do for pages and skbs). 417df833050SAlex Elder * 418df833050SAlex Elder * When a transaction completes, the SGL is normally unmapped. 419df833050SAlex Elder * A command transaction has direction DMA_NONE, which tells 420df833050SAlex Elder * gsi_trans_complete() to skip the unmapping step. 421df833050SAlex Elder * 422df833050SAlex Elder * The only things we use directly in a command scatter/gather 423df833050SAlex Elder * entry are the DMA address and length. We still need the SG 424df833050SAlex Elder * table flags to be maintained though, so assign a NULL page 425df833050SAlex Elder * pointer for that purpose. 4269dd441e4SAlex Elder */ 4279dd441e4SAlex Elder sg = &trans->sgl[which]; 428df833050SAlex Elder sg_assign_page(sg, NULL); 4299dd441e4SAlex Elder sg_dma_address(sg) = addr; 430df833050SAlex Elder sg_dma_len(sg) = size; 4319dd441e4SAlex Elder 4329dd441e4SAlex Elder info = &trans->info[which]; 4339dd441e4SAlex Elder info->opcode = opcode; 4349dd441e4SAlex Elder info->direction = direction; 4359dd441e4SAlex Elder } 4369dd441e4SAlex Elder 4379dd441e4SAlex Elder /* Add a page transfer to a transaction. It will fill the only TRE. */ 4389dd441e4SAlex Elder int gsi_trans_page_add(struct gsi_trans *trans, struct page *page, u32 size, 4399dd441e4SAlex Elder u32 offset) 4409dd441e4SAlex Elder { 4419dd441e4SAlex Elder struct scatterlist *sg = &trans->sgl[0]; 4429dd441e4SAlex Elder int ret; 4439dd441e4SAlex Elder 4449dd441e4SAlex Elder /* assert(trans->tre_count == 1); */ 4459dd441e4SAlex Elder /* assert(!trans->used); */ 4469dd441e4SAlex Elder 4479dd441e4SAlex Elder sg_set_page(sg, page, size, offset); 4489dd441e4SAlex Elder ret = dma_map_sg(trans->gsi->dev, sg, 1, trans->direction); 4499dd441e4SAlex Elder if (!ret) 4509dd441e4SAlex Elder return -ENOMEM; 4519dd441e4SAlex Elder 4529dd441e4SAlex Elder trans->used++; /* Transaction now owns the (DMA mapped) page */ 4539dd441e4SAlex Elder 4549dd441e4SAlex Elder return 0; 4559dd441e4SAlex Elder } 4569dd441e4SAlex Elder 4579dd441e4SAlex Elder /* Add an SKB transfer to a transaction. No other TREs will be used. */ 4589dd441e4SAlex Elder int gsi_trans_skb_add(struct gsi_trans *trans, struct sk_buff *skb) 4599dd441e4SAlex Elder { 4609dd441e4SAlex Elder struct scatterlist *sg = &trans->sgl[0]; 4619dd441e4SAlex Elder u32 used; 4629dd441e4SAlex Elder int ret; 4639dd441e4SAlex Elder 4649dd441e4SAlex Elder /* assert(trans->tre_count == 1); */ 4659dd441e4SAlex Elder /* assert(!trans->used); */ 4669dd441e4SAlex Elder 4679dd441e4SAlex Elder /* skb->len will not be 0 (checked early) */ 4689dd441e4SAlex Elder ret = skb_to_sgvec(skb, sg, 0, skb->len); 4699dd441e4SAlex Elder if (ret < 0) 4709dd441e4SAlex Elder return ret; 4719dd441e4SAlex Elder used = ret; 4729dd441e4SAlex Elder 4739dd441e4SAlex Elder ret = dma_map_sg(trans->gsi->dev, sg, used, trans->direction); 4749dd441e4SAlex Elder if (!ret) 4759dd441e4SAlex Elder return -ENOMEM; 4769dd441e4SAlex Elder 4779dd441e4SAlex Elder trans->used += used; /* Transaction now owns the (DMA mapped) skb */ 4789dd441e4SAlex Elder 4799dd441e4SAlex Elder return 0; 4809dd441e4SAlex Elder } 4819dd441e4SAlex Elder 4829dd441e4SAlex Elder /* Compute the length/opcode value to use for a TRE */ 4839dd441e4SAlex Elder static __le16 gsi_tre_len_opcode(enum ipa_cmd_opcode opcode, u32 len) 4849dd441e4SAlex Elder { 4859dd441e4SAlex Elder return opcode == IPA_CMD_NONE ? cpu_to_le16((u16)len) 4869dd441e4SAlex Elder : cpu_to_le16((u16)opcode); 4879dd441e4SAlex Elder } 4889dd441e4SAlex Elder 4899dd441e4SAlex Elder /* Compute the flags value to use for a given TRE */ 4909dd441e4SAlex Elder static __le32 gsi_tre_flags(bool last_tre, bool bei, enum ipa_cmd_opcode opcode) 4919dd441e4SAlex Elder { 4929dd441e4SAlex Elder enum gsi_tre_type tre_type; 4939dd441e4SAlex Elder u32 tre_flags; 4949dd441e4SAlex Elder 4959dd441e4SAlex Elder tre_type = opcode == IPA_CMD_NONE ? GSI_RE_XFER : GSI_RE_IMMD_CMD; 4969dd441e4SAlex Elder tre_flags = u32_encode_bits(tre_type, TRE_FLAGS_TYPE_FMASK); 4979dd441e4SAlex Elder 4989dd441e4SAlex Elder /* Last TRE contains interrupt flags */ 4999dd441e4SAlex Elder if (last_tre) { 5009dd441e4SAlex Elder /* All transactions end in a transfer completion interrupt */ 5019dd441e4SAlex Elder tre_flags |= TRE_FLAGS_IEOT_FMASK; 5029dd441e4SAlex Elder /* Don't interrupt when outbound commands are acknowledged */ 5039dd441e4SAlex Elder if (bei) 5049dd441e4SAlex Elder tre_flags |= TRE_FLAGS_BEI_FMASK; 5059dd441e4SAlex Elder } else { /* All others indicate there's more to come */ 5069dd441e4SAlex Elder tre_flags |= TRE_FLAGS_CHAIN_FMASK; 5079dd441e4SAlex Elder } 5089dd441e4SAlex Elder 5099dd441e4SAlex Elder return cpu_to_le32(tre_flags); 5109dd441e4SAlex Elder } 5119dd441e4SAlex Elder 5129dd441e4SAlex Elder static void gsi_trans_tre_fill(struct gsi_tre *dest_tre, dma_addr_t addr, 5139dd441e4SAlex Elder u32 len, bool last_tre, bool bei, 5149dd441e4SAlex Elder enum ipa_cmd_opcode opcode) 5159dd441e4SAlex Elder { 5169dd441e4SAlex Elder struct gsi_tre tre; 5179dd441e4SAlex Elder 5189dd441e4SAlex Elder tre.addr = cpu_to_le64(addr); 5199dd441e4SAlex Elder tre.len_opcode = gsi_tre_len_opcode(opcode, len); 5209dd441e4SAlex Elder tre.reserved = 0; 5219dd441e4SAlex Elder tre.flags = gsi_tre_flags(last_tre, bei, opcode); 5229dd441e4SAlex Elder 5239dd441e4SAlex Elder /* ARM64 can write 16 bytes as a unit with a single instruction. 5249dd441e4SAlex Elder * Doing the assignment this way is an attempt to make that happen. 5259dd441e4SAlex Elder */ 5269dd441e4SAlex Elder *dest_tre = tre; 5279dd441e4SAlex Elder } 5289dd441e4SAlex Elder 5299dd441e4SAlex Elder /** 5309dd441e4SAlex Elder * __gsi_trans_commit() - Common GSI transaction commit code 5319dd441e4SAlex Elder * @trans: Transaction to commit 5329dd441e4SAlex Elder * @ring_db: Whether to tell the hardware about these queued transfers 5339dd441e4SAlex Elder * 5349dd441e4SAlex Elder * Formats channel ring TRE entries based on the content of the scatterlist. 5359dd441e4SAlex Elder * Maps a transaction pointer to the last ring entry used for the transaction, 5369dd441e4SAlex Elder * so it can be recovered when it completes. Moves the transaction to the 5379dd441e4SAlex Elder * pending list. Finally, updates the channel ring pointer and optionally 5389dd441e4SAlex Elder * rings the doorbell. 5399dd441e4SAlex Elder */ 5409dd441e4SAlex Elder static void __gsi_trans_commit(struct gsi_trans *trans, bool ring_db) 5419dd441e4SAlex Elder { 5429dd441e4SAlex Elder struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; 5439dd441e4SAlex Elder struct gsi_ring *ring = &channel->tre_ring; 5449dd441e4SAlex Elder enum ipa_cmd_opcode opcode = IPA_CMD_NONE; 5459dd441e4SAlex Elder bool bei = channel->toward_ipa; 5469dd441e4SAlex Elder struct ipa_cmd_info *info; 5479dd441e4SAlex Elder struct gsi_tre *dest_tre; 5489dd441e4SAlex Elder struct scatterlist *sg; 5499dd441e4SAlex Elder u32 byte_count = 0; 5509dd441e4SAlex Elder u32 avail; 5519dd441e4SAlex Elder u32 i; 5529dd441e4SAlex Elder 5539dd441e4SAlex Elder /* assert(trans->used > 0); */ 5549dd441e4SAlex Elder 5559dd441e4SAlex Elder /* Consume the entries. If we cross the end of the ring while 5569dd441e4SAlex Elder * filling them we'll switch to the beginning to finish. 5579dd441e4SAlex Elder * If there is no info array we're doing a simple data 5589dd441e4SAlex Elder * transfer request, whose opcode is IPA_CMD_NONE. 5599dd441e4SAlex Elder */ 5609dd441e4SAlex Elder info = trans->info ? &trans->info[0] : NULL; 5619dd441e4SAlex Elder avail = ring->count - ring->index % ring->count; 5629dd441e4SAlex Elder dest_tre = gsi_ring_virt(ring, ring->index); 5639dd441e4SAlex Elder for_each_sg(trans->sgl, sg, trans->used, i) { 5649dd441e4SAlex Elder bool last_tre = i == trans->used - 1; 5659dd441e4SAlex Elder dma_addr_t addr = sg_dma_address(sg); 5669dd441e4SAlex Elder u32 len = sg_dma_len(sg); 5679dd441e4SAlex Elder 5689dd441e4SAlex Elder byte_count += len; 5699dd441e4SAlex Elder if (!avail--) 5709dd441e4SAlex Elder dest_tre = gsi_ring_virt(ring, 0); 5719dd441e4SAlex Elder if (info) 5729dd441e4SAlex Elder opcode = info++->opcode; 5739dd441e4SAlex Elder 5749dd441e4SAlex Elder gsi_trans_tre_fill(dest_tre, addr, len, last_tre, bei, opcode); 5759dd441e4SAlex Elder dest_tre++; 5769dd441e4SAlex Elder } 5779dd441e4SAlex Elder ring->index += trans->used; 5789dd441e4SAlex Elder 5799dd441e4SAlex Elder if (channel->toward_ipa) { 5809dd441e4SAlex Elder /* We record TX bytes when they are sent */ 5819dd441e4SAlex Elder trans->len = byte_count; 5829dd441e4SAlex Elder trans->trans_count = channel->trans_count; 5839dd441e4SAlex Elder trans->byte_count = channel->byte_count; 5849dd441e4SAlex Elder channel->trans_count++; 5859dd441e4SAlex Elder channel->byte_count += byte_count; 5869dd441e4SAlex Elder } 5879dd441e4SAlex Elder 5889dd441e4SAlex Elder /* Associate the last TRE with the transaction */ 5899dd441e4SAlex Elder gsi_channel_trans_map(channel, ring->index - 1, trans); 5909dd441e4SAlex Elder 5919dd441e4SAlex Elder gsi_trans_move_pending(trans); 5929dd441e4SAlex Elder 5939dd441e4SAlex Elder /* Ring doorbell if requested, or if all TREs are allocated */ 5949dd441e4SAlex Elder if (ring_db || !atomic_read(&channel->trans_info.tre_avail)) { 5959dd441e4SAlex Elder /* Report what we're handing off to hardware for TX channels */ 5969dd441e4SAlex Elder if (channel->toward_ipa) 5979dd441e4SAlex Elder gsi_channel_tx_queued(channel); 5989dd441e4SAlex Elder gsi_channel_doorbell(channel); 5999dd441e4SAlex Elder } 6009dd441e4SAlex Elder } 6019dd441e4SAlex Elder 6029dd441e4SAlex Elder /* Commit a GSI transaction */ 6039dd441e4SAlex Elder void gsi_trans_commit(struct gsi_trans *trans, bool ring_db) 6049dd441e4SAlex Elder { 6059dd441e4SAlex Elder if (trans->used) 6069dd441e4SAlex Elder __gsi_trans_commit(trans, ring_db); 6079dd441e4SAlex Elder else 6089dd441e4SAlex Elder gsi_trans_free(trans); 6099dd441e4SAlex Elder } 6109dd441e4SAlex Elder 6119dd441e4SAlex Elder /* Commit a GSI transaction and wait for it to complete */ 6129dd441e4SAlex Elder void gsi_trans_commit_wait(struct gsi_trans *trans) 6139dd441e4SAlex Elder { 6149dd441e4SAlex Elder if (!trans->used) 6159dd441e4SAlex Elder goto out_trans_free; 6169dd441e4SAlex Elder 6179dd441e4SAlex Elder refcount_inc(&trans->refcount); 6189dd441e4SAlex Elder 6199dd441e4SAlex Elder __gsi_trans_commit(trans, true); 6209dd441e4SAlex Elder 6219dd441e4SAlex Elder wait_for_completion(&trans->completion); 6229dd441e4SAlex Elder 6239dd441e4SAlex Elder out_trans_free: 6249dd441e4SAlex Elder gsi_trans_free(trans); 6259dd441e4SAlex Elder } 6269dd441e4SAlex Elder 6279dd441e4SAlex Elder /* Commit a GSI transaction and wait for it to complete, with timeout */ 6289dd441e4SAlex Elder int gsi_trans_commit_wait_timeout(struct gsi_trans *trans, 6299dd441e4SAlex Elder unsigned long timeout) 6309dd441e4SAlex Elder { 6319dd441e4SAlex Elder unsigned long timeout_jiffies = msecs_to_jiffies(timeout); 6329dd441e4SAlex Elder unsigned long remaining = 1; /* In case of empty transaction */ 6339dd441e4SAlex Elder 6349dd441e4SAlex Elder if (!trans->used) 6359dd441e4SAlex Elder goto out_trans_free; 6369dd441e4SAlex Elder 6379dd441e4SAlex Elder refcount_inc(&trans->refcount); 6389dd441e4SAlex Elder 6399dd441e4SAlex Elder __gsi_trans_commit(trans, true); 6409dd441e4SAlex Elder 6419dd441e4SAlex Elder remaining = wait_for_completion_timeout(&trans->completion, 6429dd441e4SAlex Elder timeout_jiffies); 6439dd441e4SAlex Elder out_trans_free: 6449dd441e4SAlex Elder gsi_trans_free(trans); 6459dd441e4SAlex Elder 6469dd441e4SAlex Elder return remaining ? 0 : -ETIMEDOUT; 6479dd441e4SAlex Elder } 6489dd441e4SAlex Elder 6499dd441e4SAlex Elder /* Process the completion of a transaction; called while polling */ 6509dd441e4SAlex Elder void gsi_trans_complete(struct gsi_trans *trans) 6519dd441e4SAlex Elder { 6529dd441e4SAlex Elder /* If the entire SGL was mapped when added, unmap it now */ 6539dd441e4SAlex Elder if (trans->direction != DMA_NONE) 6549dd441e4SAlex Elder dma_unmap_sg(trans->gsi->dev, trans->sgl, trans->used, 6559dd441e4SAlex Elder trans->direction); 6569dd441e4SAlex Elder 6579dd441e4SAlex Elder ipa_gsi_trans_complete(trans); 6589dd441e4SAlex Elder 6599dd441e4SAlex Elder complete(&trans->completion); 6609dd441e4SAlex Elder 6619dd441e4SAlex Elder gsi_trans_free(trans); 6629dd441e4SAlex Elder } 6639dd441e4SAlex Elder 6649dd441e4SAlex Elder /* Cancel a channel's pending transactions */ 6659dd441e4SAlex Elder void gsi_channel_trans_cancel_pending(struct gsi_channel *channel) 6669dd441e4SAlex Elder { 6679dd441e4SAlex Elder struct gsi_trans_info *trans_info = &channel->trans_info; 6689dd441e4SAlex Elder struct gsi_trans *trans; 6699dd441e4SAlex Elder bool cancelled; 6709dd441e4SAlex Elder 6719dd441e4SAlex Elder /* channel->gsi->mutex is held by caller */ 6729dd441e4SAlex Elder spin_lock_bh(&trans_info->spinlock); 6739dd441e4SAlex Elder 6749dd441e4SAlex Elder cancelled = !list_empty(&trans_info->pending); 6759dd441e4SAlex Elder list_for_each_entry(trans, &trans_info->pending, links) 6769dd441e4SAlex Elder trans->cancelled = true; 6779dd441e4SAlex Elder 6789dd441e4SAlex Elder list_splice_tail_init(&trans_info->pending, &trans_info->complete); 6799dd441e4SAlex Elder 6809dd441e4SAlex Elder spin_unlock_bh(&trans_info->spinlock); 6819dd441e4SAlex Elder 6829dd441e4SAlex Elder /* Schedule NAPI polling to complete the cancelled transactions */ 6839dd441e4SAlex Elder if (cancelled) 6849dd441e4SAlex Elder napi_schedule(&channel->napi); 6859dd441e4SAlex Elder } 6869dd441e4SAlex Elder 6879dd441e4SAlex Elder /* Issue a command to read a single byte from a channel */ 6889dd441e4SAlex Elder int gsi_trans_read_byte(struct gsi *gsi, u32 channel_id, dma_addr_t addr) 6899dd441e4SAlex Elder { 6909dd441e4SAlex Elder struct gsi_channel *channel = &gsi->channel[channel_id]; 6919dd441e4SAlex Elder struct gsi_ring *ring = &channel->tre_ring; 6929dd441e4SAlex Elder struct gsi_trans_info *trans_info; 6939dd441e4SAlex Elder struct gsi_tre *dest_tre; 6949dd441e4SAlex Elder 6959dd441e4SAlex Elder trans_info = &channel->trans_info; 6969dd441e4SAlex Elder 6979dd441e4SAlex Elder /* First reserve the TRE, if possible */ 6989dd441e4SAlex Elder if (!gsi_trans_tre_reserve(trans_info, 1)) 6999dd441e4SAlex Elder return -EBUSY; 7009dd441e4SAlex Elder 7019dd441e4SAlex Elder /* Now fill the the reserved TRE and tell the hardware */ 7029dd441e4SAlex Elder 7039dd441e4SAlex Elder dest_tre = gsi_ring_virt(ring, ring->index); 7049dd441e4SAlex Elder gsi_trans_tre_fill(dest_tre, addr, 1, true, false, IPA_CMD_NONE); 7059dd441e4SAlex Elder 7069dd441e4SAlex Elder ring->index++; 7079dd441e4SAlex Elder gsi_channel_doorbell(channel); 7089dd441e4SAlex Elder 7099dd441e4SAlex Elder return 0; 7109dd441e4SAlex Elder } 7119dd441e4SAlex Elder 7129dd441e4SAlex Elder /* Mark a gsi_trans_read_byte() request done */ 7139dd441e4SAlex Elder void gsi_trans_read_byte_done(struct gsi *gsi, u32 channel_id) 7149dd441e4SAlex Elder { 7159dd441e4SAlex Elder struct gsi_channel *channel = &gsi->channel[channel_id]; 7169dd441e4SAlex Elder 7179dd441e4SAlex Elder gsi_trans_tre_release(&channel->trans_info, 1); 7189dd441e4SAlex Elder } 7199dd441e4SAlex Elder 7209dd441e4SAlex Elder /* Initialize a channel's GSI transaction info */ 7219dd441e4SAlex Elder int gsi_channel_trans_init(struct gsi *gsi, u32 channel_id) 7229dd441e4SAlex Elder { 7239dd441e4SAlex Elder struct gsi_channel *channel = &gsi->channel[channel_id]; 7249dd441e4SAlex Elder struct gsi_trans_info *trans_info; 7259dd441e4SAlex Elder u32 tre_max; 7269dd441e4SAlex Elder int ret; 7279dd441e4SAlex Elder 7289dd441e4SAlex Elder /* Ensure the size of a channel element is what's expected */ 7299dd441e4SAlex Elder BUILD_BUG_ON(sizeof(struct gsi_tre) != GSI_RING_ELEMENT_SIZE); 7309dd441e4SAlex Elder 7319dd441e4SAlex Elder /* The map array is used to determine what transaction is associated 7329dd441e4SAlex Elder * with a TRE that the hardware reports has completed. We need one 7339dd441e4SAlex Elder * map entry per TRE. 7349dd441e4SAlex Elder */ 7359dd441e4SAlex Elder trans_info = &channel->trans_info; 7369dd441e4SAlex Elder trans_info->map = kcalloc(channel->tre_count, sizeof(*trans_info->map), 7379dd441e4SAlex Elder GFP_KERNEL); 7389dd441e4SAlex Elder if (!trans_info->map) 7399dd441e4SAlex Elder return -ENOMEM; 7409dd441e4SAlex Elder 7419dd441e4SAlex Elder /* We can't use more TREs than there are available in the ring. 7429dd441e4SAlex Elder * This limits the number of transactions that can be oustanding. 7439dd441e4SAlex Elder * Worst case is one TRE per transaction (but we actually limit 7449dd441e4SAlex Elder * it to something a little less than that). We allocate resources 7459dd441e4SAlex Elder * for transactions (including transaction structures) based on 7469dd441e4SAlex Elder * this maximum number. 7479dd441e4SAlex Elder */ 7489dd441e4SAlex Elder tre_max = gsi_channel_tre_max(channel->gsi, channel_id); 7499dd441e4SAlex Elder 7509dd441e4SAlex Elder /* Transactions are allocated one at a time. */ 7519dd441e4SAlex Elder ret = gsi_trans_pool_init(&trans_info->pool, sizeof(struct gsi_trans), 7529dd441e4SAlex Elder tre_max, 1); 7539dd441e4SAlex Elder if (ret) 7549dd441e4SAlex Elder goto err_kfree; 7559dd441e4SAlex Elder 7569dd441e4SAlex Elder /* A transaction uses a scatterlist array to represent the data 7579dd441e4SAlex Elder * transfers implemented by the transaction. Each scatterlist 7589dd441e4SAlex Elder * element is used to fill a single TRE when the transaction is 7599dd441e4SAlex Elder * committed. So we need as many scatterlist elements as the 7609dd441e4SAlex Elder * maximum number of TREs that can be outstanding. 7619dd441e4SAlex Elder * 7629dd441e4SAlex Elder * All TREs in a transaction must fit within the channel's TLV FIFO. 7639dd441e4SAlex Elder * A transaction on a channel can allocate as many TREs as that but 7649dd441e4SAlex Elder * no more. 7659dd441e4SAlex Elder */ 7669dd441e4SAlex Elder ret = gsi_trans_pool_init(&trans_info->sg_pool, 7679dd441e4SAlex Elder sizeof(struct scatterlist), 7689dd441e4SAlex Elder tre_max, channel->tlv_count); 7699dd441e4SAlex Elder if (ret) 7709dd441e4SAlex Elder goto err_trans_pool_exit; 7719dd441e4SAlex Elder 7729dd441e4SAlex Elder /* Finally, the tre_avail field is what ultimately limits the number 7739dd441e4SAlex Elder * of outstanding transactions and their resources. A transaction 7749dd441e4SAlex Elder * allocation succeeds only if the TREs available are sufficient for 7759dd441e4SAlex Elder * what the transaction might need. Transaction resource pools are 7769dd441e4SAlex Elder * sized based on the maximum number of outstanding TREs, so there 7779dd441e4SAlex Elder * will always be resources available if there are TREs available. 7789dd441e4SAlex Elder */ 7799dd441e4SAlex Elder atomic_set(&trans_info->tre_avail, tre_max); 7809dd441e4SAlex Elder 7819dd441e4SAlex Elder spin_lock_init(&trans_info->spinlock); 7829dd441e4SAlex Elder INIT_LIST_HEAD(&trans_info->alloc); 7839dd441e4SAlex Elder INIT_LIST_HEAD(&trans_info->pending); 7849dd441e4SAlex Elder INIT_LIST_HEAD(&trans_info->complete); 7859dd441e4SAlex Elder INIT_LIST_HEAD(&trans_info->polled); 7869dd441e4SAlex Elder 7879dd441e4SAlex Elder return 0; 7889dd441e4SAlex Elder 7899dd441e4SAlex Elder err_trans_pool_exit: 7909dd441e4SAlex Elder gsi_trans_pool_exit(&trans_info->pool); 7919dd441e4SAlex Elder err_kfree: 7929dd441e4SAlex Elder kfree(trans_info->map); 7939dd441e4SAlex Elder 7949dd441e4SAlex Elder dev_err(gsi->dev, "error %d initializing channel %u transactions\n", 7959dd441e4SAlex Elder ret, channel_id); 7969dd441e4SAlex Elder 7979dd441e4SAlex Elder return ret; 7989dd441e4SAlex Elder } 7999dd441e4SAlex Elder 8009dd441e4SAlex Elder /* Inverse of gsi_channel_trans_init() */ 8019dd441e4SAlex Elder void gsi_channel_trans_exit(struct gsi_channel *channel) 8029dd441e4SAlex Elder { 8039dd441e4SAlex Elder struct gsi_trans_info *trans_info = &channel->trans_info; 8049dd441e4SAlex Elder 8059dd441e4SAlex Elder gsi_trans_pool_exit(&trans_info->sg_pool); 8069dd441e4SAlex Elder gsi_trans_pool_exit(&trans_info->pool); 8079dd441e4SAlex Elder kfree(trans_info->map); 8089dd441e4SAlex Elder } 809