1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 42 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 43 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 44 (0x0000c018 + 0x1000 * (ee)) 45 46 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 47 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 48 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 49 (0x0000c01c + 0x1000 * (ee)) 50 51 #define GSI_INTER_EE_SRC_CH_IRQ_CLR_OFFSET \ 52 GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 53 #define GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(ee) \ 54 (0x0000c028 + 0x1000 * (ee)) 55 56 #define GSI_INTER_EE_SRC_EV_CH_IRQ_CLR_OFFSET \ 57 GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 58 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 59 (0x0000c02c + 0x1000 * (ee)) 60 61 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 62 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 63 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 64 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 65 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 66 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 67 #define EE_FMASK GENMASK(7, 4) 68 #define CHID_FMASK GENMASK(12, 8) 69 /* The next field is present for GSI v2.0 and above */ 70 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 71 #define ERINDEX_FMASK GENMASK(18, 14) 72 #define CHSTATE_FMASK GENMASK(23, 20) 73 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 74 75 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 76 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 77 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 78 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 79 #define R_LENGTH_FMASK GENMASK(15, 0) 80 81 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 82 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 83 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 84 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 85 86 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 87 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 88 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 89 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 90 91 #define GSI_CH_C_QOS_OFFSET(ch) \ 92 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 93 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 94 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 95 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 96 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 97 #define USE_DB_ENG_FMASK GENMASK(9, 9) 98 /* The next field is present for GSI v2.0 and above */ 99 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 100 101 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 102 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 103 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 104 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 105 106 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 107 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 108 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 109 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 110 111 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 112 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 113 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 114 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 115 116 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 117 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 118 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 119 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 120 121 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 122 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 123 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 124 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 125 #define EV_CHTYPE_FMASK GENMASK(3, 0) 126 #define EV_EE_FMASK GENMASK(7, 4) 127 #define EV_EVCHID_FMASK GENMASK(15, 8) 128 #define EV_INTYPE_FMASK GENMASK(16, 16) 129 #define EV_CHSTATE_FMASK GENMASK(23, 20) 130 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 131 132 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 133 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 134 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 135 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 136 #define EV_R_LENGTH_FMASK GENMASK(15, 0) 137 138 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 139 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 140 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 141 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 142 143 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 144 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 145 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 146 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 147 148 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 149 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 150 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 151 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 152 153 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 154 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 155 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 156 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 157 #define MODT_FMASK GENMASK(15, 0) 158 #define MODC_FMASK GENMASK(23, 16) 159 #define MOD_CNT_FMASK GENMASK(31, 24) 160 161 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 162 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 163 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 164 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 165 166 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 167 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 168 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 169 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 170 171 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 172 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 173 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 174 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 175 176 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 177 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 178 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 179 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 180 181 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 182 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 183 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 184 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 185 186 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 187 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 188 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 189 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 190 191 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 192 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 193 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 194 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 195 196 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 197 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 198 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 199 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 200 201 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 202 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 203 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 204 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 205 206 #define GSI_GSI_STATUS_OFFSET \ 207 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 208 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 209 (0x0001f000 + 0x4000 * (ee)) 210 #define ENABLED_FMASK GENMASK(0, 0) 211 212 #define GSI_CH_CMD_OFFSET \ 213 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 214 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 215 (0x0001f008 + 0x4000 * (ee)) 216 #define CH_CHID_FMASK GENMASK(7, 0) 217 #define CH_OPCODE_FMASK GENMASK(31, 24) 218 219 #define GSI_EV_CH_CMD_OFFSET \ 220 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 221 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 222 (0x0001f010 + 0x4000 * (ee)) 223 #define EV_CHID_FMASK GENMASK(7, 0) 224 #define EV_OPCODE_FMASK GENMASK(31, 24) 225 226 #define GSI_GENERIC_CMD_OFFSET \ 227 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 228 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 229 (0x0001f018 + 0x4000 * (ee)) 230 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 231 #define GENERIC_CHID_FMASK GENMASK(9, 5) 232 #define GENERIC_EE_FMASK GENMASK(13, 10) 233 234 #define GSI_GSI_HW_PARAM_2_OFFSET \ 235 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 236 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 237 (0x0001f040 + 0x4000 * (ee)) 238 #define IRAM_SIZE_FMASK GENMASK(2, 0) 239 #define IRAM_SIZE_ONE_KB_FVAL 0 240 #define IRAM_SIZE_TWO_KB_FVAL 1 241 /* The next two values are available for GSI v2.0 and above */ 242 #define IRAM_SIZE_TWO_N_HALF_KB_FVAL 2 243 #define IRAM_SIZE_THREE_KB_FVAL 3 244 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 245 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 246 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 247 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 248 /* Fields below are present for GSI v2.0 and above */ 249 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 250 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 251 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 252 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 253 /* Fields below are present for GSI v2.2 and above */ 254 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 255 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 256 257 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 258 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 259 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 260 (0x0001f080 + 0x4000 * (ee)) 261 #define CH_CTRL_FMASK GENMASK(0, 0) 262 #define EV_CTRL_FMASK GENMASK(1, 1) 263 #define GLOB_EE_FMASK GENMASK(2, 2) 264 #define IEOB_FMASK GENMASK(3, 3) 265 #define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) 266 #define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) 267 #define GENERAL_FMASK GENMASK(6, 6) 268 269 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 270 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 271 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 272 (0x0001f088 + 0x4000 * (ee)) 273 #define MSK_CH_CTRL_FMASK GENMASK(0, 0) 274 #define MSK_EV_CTRL_FMASK GENMASK(1, 1) 275 #define MSK_GLOB_EE_FMASK GENMASK(2, 2) 276 #define MSK_IEOB_FMASK GENMASK(3, 3) 277 #define MSK_INTER_EE_CH_CTRL_FMASK GENMASK(4, 4) 278 #define MSK_INTER_EE_EV_CTRL_FMASK GENMASK(5, 5) 279 #define MSK_GENERAL_FMASK GENMASK(6, 6) 280 #define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0) 281 282 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 283 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 284 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 285 (0x0001f090 + 0x4000 * (ee)) 286 287 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 288 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 289 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 290 (0x0001f094 + 0x4000 * (ee)) 291 292 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 293 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 294 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 295 (0x0001f098 + 0x4000 * (ee)) 296 297 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 298 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 299 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 300 (0x0001f09c + 0x4000 * (ee)) 301 302 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 303 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 304 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 305 (0x0001f0a0 + 0x4000 * (ee)) 306 307 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 308 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 309 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 310 (0x0001f0a4 + 0x4000 * (ee)) 311 312 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 313 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 314 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 315 (0x0001f0b0 + 0x4000 * (ee)) 316 317 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 318 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 319 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 320 (0x0001f0b8 + 0x4000 * (ee)) 321 322 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 323 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 324 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 325 (0x0001f0c0 + 0x4000 * (ee)) 326 327 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 328 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 329 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 330 (0x0001f100 + 0x4000 * (ee)) 331 #define ERROR_INT_FMASK GENMASK(0, 0) 332 #define GP_INT1_FMASK GENMASK(1, 1) 333 #define GP_INT2_FMASK GENMASK(2, 2) 334 #define GP_INT3_FMASK GENMASK(3, 3) 335 336 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 337 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 338 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 339 (0x0001f108 + 0x4000 * (ee)) 340 #define EN_ERROR_INT_FMASK GENMASK(0, 0) 341 #define EN_GP_INT1_FMASK GENMASK(1, 1) 342 #define EN_GP_INT2_FMASK GENMASK(2, 2) 343 #define EN_GP_INT3_FMASK GENMASK(3, 3) 344 #define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0) 345 346 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 347 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 348 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 349 (0x0001f110 + 0x4000 * (ee)) 350 #define CLR_ERROR_INT_FMASK GENMASK(0, 0) 351 #define CLR_GP_INT1_FMASK GENMASK(1, 1) 352 #define CLR_GP_INT2_FMASK GENMASK(2, 2) 353 #define CLR_GP_INT3_FMASK GENMASK(3, 3) 354 355 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 356 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 357 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 358 (0x0001f118 + 0x4000 * (ee)) 359 #define BREAK_POINT_FMASK GENMASK(0, 0) 360 #define BUS_ERROR_FMASK GENMASK(1, 1) 361 #define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) 362 #define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) 363 364 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 365 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 366 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 367 (0x0001f120 + 0x4000 * (ee)) 368 #define EN_BREAK_POINT_FMASK GENMASK(0, 0) 369 #define EN_BUS_ERROR_FMASK GENMASK(1, 1) 370 #define EN_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) 371 #define EN_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) 372 #define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0) 373 374 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 375 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 376 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 377 (0x0001f128 + 0x4000 * (ee)) 378 #define CLR_BREAK_POINT_FMASK GENMASK(0, 0) 379 #define CLR_BUS_ERROR_FMASK GENMASK(1, 1) 380 #define CLR_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2) 381 #define CLR_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3) 382 383 #define GSI_CNTXT_INTSET_OFFSET \ 384 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 385 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 386 (0x0001f180 + 0x4000 * (ee)) 387 #define INTYPE_FMASK GENMASK(0, 0) 388 389 #define GSI_ERROR_LOG_OFFSET \ 390 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 391 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 392 (0x0001f200 + 0x4000 * (ee)) 393 #define ERR_ARG3_FMASK GENMASK(3, 0) 394 #define ERR_ARG2_FMASK GENMASK(7, 4) 395 #define ERR_ARG1_FMASK GENMASK(11, 8) 396 #define ERR_CODE_FMASK GENMASK(15, 12) 397 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 398 #define ERR_TYPE_FMASK GENMASK(27, 24) 399 #define ERR_EE_FMASK GENMASK(31, 28) 400 401 #define GSI_ERROR_LOG_CLR_OFFSET \ 402 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 403 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 404 (0x0001f210 + 0x4000 * (ee)) 405 406 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 407 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 408 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 409 (0x0001f400 + 0x4000 * (ee)) 410 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 411 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 412 #define GENERIC_EE_SUCCESS_FVAL 1 413 #define GENERIC_EE_INCORRECT_DIRECTION_FVAL 3 414 #define GENERIC_EE_INCORRECT_CHANNEL_FVAL 5 415 #define GENERIC_EE_NO_RESOURCES_FVAL 7 416 #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ 417 #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) 418 419 #endif /* _GSI_REG_H_ */ 420