1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2022 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* GSI EE registers as a group are shifted downward by a fixed constant amount 42 * for IPA versions 4.5 and beyond. This applies to all GSI registers we use 43 * *except* the ones that disable inter-EE interrupts for channels and event 44 * channels. 45 * 46 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to 47 * the mapped range is held in gsi->virt_raw. The inter-EE interrupt 48 * registers are accessed using that pointer. 49 * 50 * Most registers are accessed using gsi->virt, which is a copy of the "raw" 51 * pointer, adjusted downward by the fixed amount. 52 */ 53 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ 54 55 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ 56 57 #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ 58 (0x0000c020 + 0x1000 * GSI_EE_AP) 59 60 #define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \ 61 (0x0000c024 + 0x1000 * GSI_EE_AP) 62 63 /* All other register offsets are relative to gsi->virt */ 64 65 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 66 (0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 67 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 68 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 69 #define EE_FMASK GENMASK(7, 4) 70 #define CHID_FMASK GENMASK(12, 8) 71 /* The next field is present for IPA v4.5 and above */ 72 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 73 #define ERINDEX_FMASK GENMASK(18, 14) 74 #define CHSTATE_FMASK GENMASK(23, 20) 75 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 76 77 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 78 enum gsi_channel_type { 79 GSI_CHANNEL_TYPE_MHI = 0x0, 80 GSI_CHANNEL_TYPE_XHCI = 0x1, 81 GSI_CHANNEL_TYPE_GPI = 0x2, 82 GSI_CHANNEL_TYPE_XDCI = 0x3, 83 GSI_CHANNEL_TYPE_WDI2 = 0x4, 84 GSI_CHANNEL_TYPE_GCI = 0x5, 85 GSI_CHANNEL_TYPE_WDI3 = 0x6, 86 GSI_CHANNEL_TYPE_MHIP = 0x7, 87 GSI_CHANNEL_TYPE_AQC = 0x8, 88 GSI_CHANNEL_TYPE_11AD = 0x9, 89 }; 90 91 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 92 (0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 93 94 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 95 (0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 96 97 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 98 (0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 99 100 #define GSI_CH_C_QOS_OFFSET(ch) \ 101 (0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 102 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 103 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 104 #define USE_DB_ENG_FMASK GENMASK(9, 9) 105 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 106 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 107 /* The next two fields are present for IPA v4.5 and above */ 108 #define PREFETCH_MODE_FMASK GENMASK(13, 10) 109 #define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16) 110 /* The next field is present for IPA v4.9 and above */ 111 #define DB_IN_BYTES GENMASK(24, 24) 112 113 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 114 enum gsi_prefetch_mode { 115 GSI_USE_PREFETCH_BUFS = 0x0, 116 GSI_ESCAPE_BUF_ONLY = 0x1, 117 GSI_SMART_PREFETCH = 0x2, 118 GSI_FREE_PREFETCH = 0x3, 119 }; 120 121 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 122 (0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 123 124 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 125 (0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 126 127 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 128 (0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 129 130 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 131 (0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch)) 132 133 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 134 (0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 135 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 136 #define EV_CHTYPE_FMASK GENMASK(3, 0) 137 #define EV_EE_FMASK GENMASK(7, 4) 138 #define EV_EVCHID_FMASK GENMASK(15, 8) 139 #define EV_INTYPE_FMASK GENMASK(16, 16) 140 #define EV_CHSTATE_FMASK GENMASK(23, 20) 141 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 142 143 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 144 (0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 145 146 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 147 (0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 148 149 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 150 (0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 151 152 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 153 (0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 154 155 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 156 (0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 157 #define MODT_FMASK GENMASK(15, 0) 158 #define MODC_FMASK GENMASK(23, 16) 159 #define MOD_CNT_FMASK GENMASK(31, 24) 160 161 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 162 (0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 163 164 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 165 (0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 166 167 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 168 (0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 169 170 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 171 (0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 172 173 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 174 (0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 175 176 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 177 (0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 178 179 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 180 (0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev)) 181 182 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 183 (0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch)) 184 185 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 186 (0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev)) 187 188 #define GSI_GSI_STATUS_OFFSET \ 189 (0x0001f000 + 0x4000 * GSI_EE_AP) 190 #define ENABLED_FMASK GENMASK(0, 0) 191 192 #define GSI_CH_CMD_OFFSET \ 193 (0x0001f008 + 0x4000 * GSI_EE_AP) 194 #define CH_CHID_FMASK GENMASK(7, 0) 195 #define CH_OPCODE_FMASK GENMASK(31, 24) 196 197 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 198 enum gsi_ch_cmd_opcode { 199 GSI_CH_ALLOCATE = 0x0, 200 GSI_CH_START = 0x1, 201 GSI_CH_STOP = 0x2, 202 GSI_CH_RESET = 0x9, 203 GSI_CH_DE_ALLOC = 0xa, 204 GSI_CH_DB_STOP = 0xb, 205 }; 206 207 #define GSI_EV_CH_CMD_OFFSET \ 208 (0x0001f010 + 0x4000 * GSI_EE_AP) 209 #define EV_CHID_FMASK GENMASK(7, 0) 210 #define EV_OPCODE_FMASK GENMASK(31, 24) 211 212 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 213 enum gsi_evt_cmd_opcode { 214 GSI_EVT_ALLOCATE = 0x0, 215 GSI_EVT_RESET = 0x9, 216 GSI_EVT_DE_ALLOC = 0xa, 217 }; 218 219 #define GSI_GENERIC_CMD_OFFSET \ 220 (0x0001f018 + 0x4000 * GSI_EE_AP) 221 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 222 #define GENERIC_CHID_FMASK GENMASK(9, 5) 223 #define GENERIC_EE_FMASK GENMASK(13, 10) 224 #define GENERIC_PARAMS_FMASK GENMASK(31, 24) /* IPA v4.11+ */ 225 226 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 227 enum gsi_generic_cmd_opcode { 228 GSI_GENERIC_HALT_CHANNEL = 0x1, 229 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 230 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */ 231 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */ 232 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */ 233 }; 234 235 /* The next register is present for IPA v3.5.1 and above */ 236 #define GSI_GSI_HW_PARAM_2_OFFSET \ 237 (0x0001f040 + 0x4000 * GSI_EE_AP) 238 #define IRAM_SIZE_FMASK GENMASK(2, 0) 239 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 240 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 241 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 242 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 243 /* Fields below are present for IPA v4.0 and above */ 244 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 245 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 246 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 247 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 248 /* Fields below are present for IPA v4.2 and above */ 249 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 250 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 251 252 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 253 enum gsi_iram_size { 254 IRAM_SIZE_ONE_KB = 0x0, 255 IRAM_SIZE_TWO_KB = 0x1, 256 /* The next two values are available for IPA v4.0 and above */ 257 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 258 IRAM_SIZE_THREE_KB = 0x3, 259 /* The next two values are available for IPA v4.5 and above */ 260 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 261 IRAM_SIZE_FOUR_KB = 0x5, 262 }; 263 264 /* IRQ condition for each type is cleared by writing type-specific register */ 265 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 266 (0x0001f080 + 0x4000 * GSI_EE_AP) 267 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 268 (0x0001f088 + 0x4000 * GSI_EE_AP) 269 270 /** 271 * enum gsi_irq_type_id: GSI IRQ types 272 * @GSI_CH_CTRL: Channel allocation, deallocation, etc. 273 * @GSI_EV_CTRL: Event ring allocation, deallocation, etc. 274 * @GSI_GLOB_EE: Global/general event 275 * @GSI_IEOB: Transfer (TRE) completion 276 * @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused) 277 * @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused) 278 * @GSI_GENERAL: General hardware event (bus error, etc.) 279 */ 280 enum gsi_irq_type_id { 281 GSI_CH_CTRL = BIT(0), 282 GSI_EV_CTRL = BIT(1), 283 GSI_GLOB_EE = BIT(2), 284 GSI_IEOB = BIT(3), 285 GSI_INTER_EE_CH_CTRL = BIT(4), 286 GSI_INTER_EE_EV_CTRL = BIT(5), 287 GSI_GENERAL = BIT(6), 288 /* IRQ types 7-31 (and their bit values) are reserved */ 289 }; 290 291 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 292 (0x0001f090 + 0x4000 * GSI_EE_AP) 293 294 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 295 (0x0001f094 + 0x4000 * GSI_EE_AP) 296 297 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 298 (0x0001f098 + 0x4000 * GSI_EE_AP) 299 300 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 301 (0x0001f09c + 0x4000 * GSI_EE_AP) 302 303 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 304 (0x0001f0a0 + 0x4000 * GSI_EE_AP) 305 306 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 307 (0x0001f0a4 + 0x4000 * GSI_EE_AP) 308 309 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 310 (0x0001f0b0 + 0x4000 * GSI_EE_AP) 311 312 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 313 (0x0001f0b8 + 0x4000 * GSI_EE_AP) 314 315 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 316 (0x0001f0c0 + 0x4000 * GSI_EE_AP) 317 318 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 319 (0x0001f100 + 0x4000 * GSI_EE_AP) 320 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 321 (0x0001f108 + 0x4000 * GSI_EE_AP) 322 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 323 (0x0001f110 + 0x4000 * GSI_EE_AP) 324 325 /** enum gsi_global_irq_id: Global GSI interrupt events */ 326 enum gsi_global_irq_id { 327 ERROR_INT = BIT(0), 328 GP_INT1 = BIT(1), 329 GP_INT2 = BIT(2), 330 GP_INT3 = BIT(3), 331 /* Global IRQ types 4-31 (and their bit values) are reserved */ 332 }; 333 334 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 335 (0x0001f118 + 0x4000 * GSI_EE_AP) 336 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 337 (0x0001f120 + 0x4000 * GSI_EE_AP) 338 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 339 (0x0001f128 + 0x4000 * GSI_EE_AP) 340 341 /** enum gsi_general_irq_id: GSI general IRQ conditions */ 342 enum gsi_general_irq_id { 343 BREAK_POINT = BIT(0), 344 BUS_ERROR = BIT(1), 345 CMD_FIFO_OVRFLOW = BIT(2), 346 MCS_STACK_OVRFLOW = BIT(3), 347 /* General IRQ types 4-31 (and their bit values) are reserved */ 348 }; 349 350 #define GSI_CNTXT_INTSET_OFFSET \ 351 (0x0001f180 + 0x4000 * GSI_EE_AP) 352 #define INTYPE_FMASK GENMASK(0, 0) 353 354 #define GSI_ERROR_LOG_OFFSET \ 355 (0x0001f200 + 0x4000 * GSI_EE_AP) 356 357 #define ERR_ARG3_FMASK GENMASK(3, 0) 358 #define ERR_ARG2_FMASK GENMASK(7, 4) 359 #define ERR_ARG1_FMASK GENMASK(11, 8) 360 #define ERR_CODE_FMASK GENMASK(15, 12) 361 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 362 #define ERR_TYPE_FMASK GENMASK(27, 24) 363 #define ERR_EE_FMASK GENMASK(31, 28) 364 365 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 366 enum gsi_err_code { 367 GSI_INVALID_TRE = 0x1, 368 GSI_OUT_OF_BUFFERS = 0x2, 369 GSI_OUT_OF_RESOURCES = 0x3, 370 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 371 GSI_EVT_RING_EMPTY = 0x5, 372 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 373 /* 7 is not assigned */ 374 GSI_HWO_1 = 0x8, 375 }; 376 377 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 378 enum gsi_err_type { 379 GSI_ERR_TYPE_GLOB = 0x1, 380 GSI_ERR_TYPE_CHAN = 0x2, 381 GSI_ERR_TYPE_EVT = 0x3, 382 }; 383 384 #define GSI_ERROR_LOG_CLR_OFFSET \ 385 (0x0001f210 + 0x4000 * GSI_EE_AP) 386 387 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 388 (0x0001f400 + 0x4000 * GSI_EE_AP) 389 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 390 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 391 392 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 393 enum gsi_generic_ee_result { 394 GENERIC_EE_SUCCESS = 0x1, 395 GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2, 396 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 397 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 398 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 399 GENERIC_EE_RETRY = 0x6, 400 GENERIC_EE_NO_RESOURCES = 0x7, 401 }; 402 403 #endif /* _GSI_REG_H_ */ 404