1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* GSI EE registers as a group are shifted downward by a fixed 42 * constant amount for IPA versions 4.5 and beyond. This applies 43 * to all GSI registers we use *except* the ones that disable 44 * inter-EE interrupts for channels and event channels. 45 * 46 * We handle this by adjusting the pointer to the mapped GSI memory 47 * region downward. Then in the one place we use them (gsi_irq_setup()) 48 * we undo that adjustment for the inter-EE interrupt registers. 49 */ 50 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ 51 52 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 53 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 54 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 55 (0x0000c018 + 0x1000 * (ee)) 56 57 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 58 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 59 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 60 (0x0000c01c + 0x1000 * (ee)) 61 62 #define GSI_INTER_EE_SRC_CH_IRQ_CLR_OFFSET \ 63 GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 64 #define GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(ee) \ 65 (0x0000c028 + 0x1000 * (ee)) 66 67 #define GSI_INTER_EE_SRC_EV_CH_IRQ_CLR_OFFSET \ 68 GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 69 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 70 (0x0000c02c + 0x1000 * (ee)) 71 72 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 73 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 74 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 75 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 76 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 77 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 78 #define EE_FMASK GENMASK(7, 4) 79 #define CHID_FMASK GENMASK(12, 8) 80 /* The next field is present for IPA v4.5 and above */ 81 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 82 #define ERINDEX_FMASK GENMASK(18, 14) 83 #define CHSTATE_FMASK GENMASK(23, 20) 84 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 85 86 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 87 enum gsi_channel_type { 88 GSI_CHANNEL_TYPE_MHI = 0x0, 89 GSI_CHANNEL_TYPE_XHCI = 0x1, 90 GSI_CHANNEL_TYPE_GPI = 0x2, 91 GSI_CHANNEL_TYPE_XDCI = 0x3, 92 }; 93 94 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 95 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 96 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 97 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 98 #define R_LENGTH_FMASK GENMASK(15, 0) 99 100 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 101 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 102 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 103 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 104 105 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 106 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 107 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 108 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 109 110 #define GSI_CH_C_QOS_OFFSET(ch) \ 111 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 112 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 113 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 114 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 115 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 116 #define USE_DB_ENG_FMASK GENMASK(9, 9) 117 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 118 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 119 /* The next two fields are present for IPA v4.5 and above */ 120 #define PREFETCH_MODE_FMASK GENMASK(13, 10) 121 #define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16) 122 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 123 enum gsi_prefetch_mode { 124 GSI_USE_PREFETCH_BUFS = 0x0, 125 GSI_ESCAPE_BUF_ONLY = 0x1, 126 GSI_SMART_PREFETCH = 0x2, 127 GSI_FREE_PREFETCH = 0x3, 128 }; 129 130 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 131 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 132 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 133 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 134 135 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 136 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 137 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 138 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 139 140 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 141 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 142 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 143 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 144 145 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 146 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 147 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 148 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 149 150 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 151 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 152 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 153 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 154 #define EV_CHTYPE_FMASK GENMASK(3, 0) 155 #define EV_EE_FMASK GENMASK(7, 4) 156 #define EV_EVCHID_FMASK GENMASK(15, 8) 157 #define EV_INTYPE_FMASK GENMASK(16, 16) 158 #define EV_CHSTATE_FMASK GENMASK(23, 20) 159 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 160 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 161 162 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 163 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 164 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 165 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 166 #define EV_R_LENGTH_FMASK GENMASK(15, 0) 167 168 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 169 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 170 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 171 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 172 173 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 174 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 175 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 176 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 177 178 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 179 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 180 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 181 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 182 183 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 184 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 185 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 186 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 187 #define MODT_FMASK GENMASK(15, 0) 188 #define MODC_FMASK GENMASK(23, 16) 189 #define MOD_CNT_FMASK GENMASK(31, 24) 190 191 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 192 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 193 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 194 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 195 196 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 197 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 198 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 199 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 200 201 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 202 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 203 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 204 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 205 206 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 207 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 208 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 209 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 210 211 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 212 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 213 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 214 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 215 216 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 217 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 218 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 219 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 220 221 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 222 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 223 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 224 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 225 226 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 227 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 228 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 229 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 230 231 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 232 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 233 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 234 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 235 236 #define GSI_GSI_STATUS_OFFSET \ 237 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 238 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 239 (0x0001f000 + 0x4000 * (ee)) 240 #define ENABLED_FMASK GENMASK(0, 0) 241 242 #define GSI_CH_CMD_OFFSET \ 243 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 244 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 245 (0x0001f008 + 0x4000 * (ee)) 246 #define CH_CHID_FMASK GENMASK(7, 0) 247 #define CH_OPCODE_FMASK GENMASK(31, 24) 248 249 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 250 enum gsi_ch_cmd_opcode { 251 GSI_CH_ALLOCATE = 0x0, 252 GSI_CH_START = 0x1, 253 GSI_CH_STOP = 0x2, 254 GSI_CH_RESET = 0x9, 255 GSI_CH_DE_ALLOC = 0xa, 256 }; 257 258 #define GSI_EV_CH_CMD_OFFSET \ 259 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 260 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 261 (0x0001f010 + 0x4000 * (ee)) 262 #define EV_CHID_FMASK GENMASK(7, 0) 263 #define EV_OPCODE_FMASK GENMASK(31, 24) 264 265 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 266 enum gsi_evt_cmd_opcode { 267 GSI_EVT_ALLOCATE = 0x0, 268 GSI_EVT_RESET = 0x9, 269 GSI_EVT_DE_ALLOC = 0xa, 270 }; 271 272 #define GSI_GENERIC_CMD_OFFSET \ 273 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 274 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 275 (0x0001f018 + 0x4000 * (ee)) 276 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 277 #define GENERIC_CHID_FMASK GENMASK(9, 5) 278 #define GENERIC_EE_FMASK GENMASK(13, 10) 279 280 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 281 enum gsi_generic_cmd_opcode { 282 GSI_GENERIC_HALT_CHANNEL = 0x1, 283 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 284 }; 285 286 #define GSI_GSI_HW_PARAM_2_OFFSET \ 287 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 288 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 289 (0x0001f040 + 0x4000 * (ee)) 290 #define IRAM_SIZE_FMASK GENMASK(2, 0) 291 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 292 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 293 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 294 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 295 /* Fields below are present for IPA v4.0 and above */ 296 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 297 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 298 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 299 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 300 /* Fields below are present for IPA v4.2 and above */ 301 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 302 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 303 304 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 305 enum gsi_iram_size { 306 IRAM_SIZE_ONE_KB = 0x0, 307 IRAM_SIZE_TWO_KB = 0x1, 308 /* The next two values are available for IPA v4.0 and above */ 309 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 310 IRAM_SIZE_THREE_KB = 0x3, 311 /* The next two values are available for IPA v4.5 and above */ 312 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 313 IRAM_SIZE_FOUR_KB = 0x5, 314 }; 315 316 /* IRQ condition for each type is cleared by writing type-specific register */ 317 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 318 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 319 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 320 (0x0001f080 + 0x4000 * (ee)) 321 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 322 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 323 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 324 (0x0001f088 + 0x4000 * (ee)) 325 326 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ 327 enum gsi_irq_type_id { 328 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ 329 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ 330 GSI_GLOB_EE = 0x2, /* global/general event */ 331 GSI_IEOB = 0x3, /* TRE completion */ 332 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ 333 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ 334 GSI_GENERAL = 0x6, /* general-purpose event */ 335 }; 336 337 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 338 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 339 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 340 (0x0001f090 + 0x4000 * (ee)) 341 342 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 343 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 344 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 345 (0x0001f094 + 0x4000 * (ee)) 346 347 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 348 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 349 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 350 (0x0001f098 + 0x4000 * (ee)) 351 352 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 353 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 354 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 355 (0x0001f09c + 0x4000 * (ee)) 356 357 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 358 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 359 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 360 (0x0001f0a0 + 0x4000 * (ee)) 361 362 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 363 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 364 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 365 (0x0001f0a4 + 0x4000 * (ee)) 366 367 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 368 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 369 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 370 (0x0001f0b0 + 0x4000 * (ee)) 371 372 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 373 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 374 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 375 (0x0001f0b8 + 0x4000 * (ee)) 376 377 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 378 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 379 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 380 (0x0001f0c0 + 0x4000 * (ee)) 381 382 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 383 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 384 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 385 (0x0001f100 + 0x4000 * (ee)) 386 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 387 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 388 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 389 (0x0001f108 + 0x4000 * (ee)) 390 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 391 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 392 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 393 (0x0001f110 + 0x4000 * (ee)) 394 /* Values here are bit positions in the GLOB_IRQ_* registers */ 395 enum gsi_global_irq_id { 396 ERROR_INT = 0x0, 397 GP_INT1 = 0x1, 398 GP_INT2 = 0x2, 399 GP_INT3 = 0x3, 400 }; 401 402 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 403 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 404 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 405 (0x0001f118 + 0x4000 * (ee)) 406 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 407 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 408 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 409 (0x0001f120 + 0x4000 * (ee)) 410 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 411 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 412 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 413 (0x0001f128 + 0x4000 * (ee)) 414 /* Values here are bit positions in the (general) GSI_IRQ_* registers */ 415 enum gsi_general_id { 416 BREAK_POINT = 0x0, 417 BUS_ERROR = 0x1, 418 CMD_FIFO_OVRFLOW = 0x2, 419 MCS_STACK_OVRFLOW = 0x3, 420 }; 421 422 #define GSI_CNTXT_INTSET_OFFSET \ 423 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 424 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 425 (0x0001f180 + 0x4000 * (ee)) 426 #define INTYPE_FMASK GENMASK(0, 0) 427 428 #define GSI_ERROR_LOG_OFFSET \ 429 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 430 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 431 (0x0001f200 + 0x4000 * (ee)) 432 #define ERR_ARG3_FMASK GENMASK(3, 0) 433 #define ERR_ARG2_FMASK GENMASK(7, 4) 434 #define ERR_ARG1_FMASK GENMASK(11, 8) 435 #define ERR_CODE_FMASK GENMASK(15, 12) 436 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 437 #define ERR_TYPE_FMASK GENMASK(27, 24) 438 #define ERR_EE_FMASK GENMASK(31, 28) 439 440 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 441 enum gsi_err_code { 442 GSI_INVALID_TRE = 0x1, 443 GSI_OUT_OF_BUFFERS = 0x2, 444 GSI_OUT_OF_RESOURCES = 0x3, 445 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 446 GSI_EVT_RING_EMPTY = 0x5, 447 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 448 /* 7 is not assigned */ 449 GSI_HWO_1 = 0x8, 450 }; 451 452 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 453 enum gsi_err_type { 454 GSI_ERR_TYPE_GLOB = 0x1, 455 GSI_ERR_TYPE_CHAN = 0x2, 456 GSI_ERR_TYPE_EVT = 0x3, 457 }; 458 459 #define GSI_ERROR_LOG_CLR_OFFSET \ 460 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 461 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 462 (0x0001f210 + 0x4000 * (ee)) 463 464 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 465 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 466 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 467 (0x0001f400 + 0x4000 * (ee)) 468 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 469 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 470 471 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 472 enum gsi_generic_ee_result { 473 GENERIC_EE_SUCCESS = 0x1, 474 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, 475 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 476 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 477 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 478 GENERIC_EE_RETRY = 0x6, 479 GENERIC_EE_NO_RESOURCES = 0x7, 480 }; 481 482 #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ 483 #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) 484 485 #endif /* _GSI_REG_H_ */ 486