1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 42 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 43 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 44 (0x0000c018 + 0x1000 * (ee)) 45 46 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 47 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 48 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 49 (0x0000c01c + 0x1000 * (ee)) 50 51 #define GSI_INTER_EE_SRC_CH_IRQ_CLR_OFFSET \ 52 GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 53 #define GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(ee) \ 54 (0x0000c028 + 0x1000 * (ee)) 55 56 #define GSI_INTER_EE_SRC_EV_CH_IRQ_CLR_OFFSET \ 57 GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 58 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 59 (0x0000c02c + 0x1000 * (ee)) 60 61 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 62 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 63 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 64 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 65 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 66 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 67 #define EE_FMASK GENMASK(7, 4) 68 #define CHID_FMASK GENMASK(12, 8) 69 /* The next field is present for IPA v4.5 and above */ 70 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 71 #define ERINDEX_FMASK GENMASK(18, 14) 72 #define CHSTATE_FMASK GENMASK(23, 20) 73 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 74 75 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 76 enum gsi_channel_type { 77 GSI_CHANNEL_TYPE_MHI = 0x0, 78 GSI_CHANNEL_TYPE_XHCI = 0x1, 79 GSI_CHANNEL_TYPE_GPI = 0x2, 80 GSI_CHANNEL_TYPE_XDCI = 0x3, 81 }; 82 83 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 84 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 85 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 86 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 87 #define R_LENGTH_FMASK GENMASK(15, 0) 88 89 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 90 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 91 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 92 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 93 94 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 95 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 96 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 97 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 98 99 #define GSI_CH_C_QOS_OFFSET(ch) \ 100 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 101 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 102 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 103 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 104 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 105 #define USE_DB_ENG_FMASK GENMASK(9, 9) 106 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 107 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 108 109 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 110 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 111 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 112 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 113 114 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 115 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 116 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 117 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 118 119 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 120 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 121 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 122 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 123 124 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 125 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 126 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 127 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 128 129 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 130 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 131 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 132 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 133 #define EV_CHTYPE_FMASK GENMASK(3, 0) 134 #define EV_EE_FMASK GENMASK(7, 4) 135 #define EV_EVCHID_FMASK GENMASK(15, 8) 136 #define EV_INTYPE_FMASK GENMASK(16, 16) 137 #define EV_CHSTATE_FMASK GENMASK(23, 20) 138 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 139 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 140 141 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 142 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 143 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 144 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 145 #define EV_R_LENGTH_FMASK GENMASK(15, 0) 146 147 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 148 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 149 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 150 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 151 152 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 153 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 154 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 155 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 156 157 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 158 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 159 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 160 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 161 162 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 163 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 164 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 165 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 166 #define MODT_FMASK GENMASK(15, 0) 167 #define MODC_FMASK GENMASK(23, 16) 168 #define MOD_CNT_FMASK GENMASK(31, 24) 169 170 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 171 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 172 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 173 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 174 175 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 176 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 177 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 178 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 179 180 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 181 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 182 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 183 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 184 185 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 186 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 187 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 188 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 189 190 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 191 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 192 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 193 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 194 195 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 196 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 197 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 198 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 199 200 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 201 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 202 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 203 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 204 205 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 206 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 207 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 208 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 209 210 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 211 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 212 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 213 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 214 215 #define GSI_GSI_STATUS_OFFSET \ 216 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 217 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 218 (0x0001f000 + 0x4000 * (ee)) 219 #define ENABLED_FMASK GENMASK(0, 0) 220 221 #define GSI_CH_CMD_OFFSET \ 222 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 223 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 224 (0x0001f008 + 0x4000 * (ee)) 225 #define CH_CHID_FMASK GENMASK(7, 0) 226 #define CH_OPCODE_FMASK GENMASK(31, 24) 227 228 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 229 enum gsi_ch_cmd_opcode { 230 GSI_CH_ALLOCATE = 0x0, 231 GSI_CH_START = 0x1, 232 GSI_CH_STOP = 0x2, 233 GSI_CH_RESET = 0x9, 234 GSI_CH_DE_ALLOC = 0xa, 235 }; 236 237 #define GSI_EV_CH_CMD_OFFSET \ 238 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 239 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 240 (0x0001f010 + 0x4000 * (ee)) 241 #define EV_CHID_FMASK GENMASK(7, 0) 242 #define EV_OPCODE_FMASK GENMASK(31, 24) 243 244 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 245 enum gsi_evt_cmd_opcode { 246 GSI_EVT_ALLOCATE = 0x0, 247 GSI_EVT_RESET = 0x9, 248 GSI_EVT_DE_ALLOC = 0xa, 249 }; 250 251 #define GSI_GENERIC_CMD_OFFSET \ 252 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 253 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 254 (0x0001f018 + 0x4000 * (ee)) 255 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 256 #define GENERIC_CHID_FMASK GENMASK(9, 5) 257 #define GENERIC_EE_FMASK GENMASK(13, 10) 258 259 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 260 enum gsi_generic_cmd_opcode { 261 GSI_GENERIC_HALT_CHANNEL = 0x1, 262 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 263 }; 264 265 #define GSI_GSI_HW_PARAM_2_OFFSET \ 266 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 267 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 268 (0x0001f040 + 0x4000 * (ee)) 269 #define IRAM_SIZE_FMASK GENMASK(2, 0) 270 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 271 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 272 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 273 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 274 /* Fields below are present for IPA v4.0 and above */ 275 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 276 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 277 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 278 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 279 /* Fields below are present for IPA v4.2 and above */ 280 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 281 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 282 283 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 284 enum gsi_iram_size { 285 IRAM_SIZE_ONE_KB = 0x0, 286 IRAM_SIZE_TWO_KB = 0x1, 287 /* The next two values are available for IPA v4.0 and above */ 288 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 289 IRAM_SIZE_THREE_KB = 0x3, 290 }; 291 292 /* IRQ condition for each type is cleared by writing type-specific register */ 293 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 294 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 295 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 296 (0x0001f080 + 0x4000 * (ee)) 297 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 298 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 299 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 300 (0x0001f088 + 0x4000 * (ee)) 301 302 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ 303 enum gsi_irq_type_id { 304 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ 305 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ 306 GSI_GLOB_EE = 0x2, /* global/general event */ 307 GSI_IEOB = 0x3, /* TRE completion */ 308 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ 309 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ 310 GSI_GENERAL = 0x6, /* general-purpose event */ 311 }; 312 313 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 314 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 315 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 316 (0x0001f090 + 0x4000 * (ee)) 317 318 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 319 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 320 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 321 (0x0001f094 + 0x4000 * (ee)) 322 323 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 324 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 325 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 326 (0x0001f098 + 0x4000 * (ee)) 327 328 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 329 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 330 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 331 (0x0001f09c + 0x4000 * (ee)) 332 333 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 334 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 335 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 336 (0x0001f0a0 + 0x4000 * (ee)) 337 338 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 339 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 340 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 341 (0x0001f0a4 + 0x4000 * (ee)) 342 343 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 344 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 345 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 346 (0x0001f0b0 + 0x4000 * (ee)) 347 348 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 349 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 350 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 351 (0x0001f0b8 + 0x4000 * (ee)) 352 353 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 354 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 355 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 356 (0x0001f0c0 + 0x4000 * (ee)) 357 358 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 359 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 360 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 361 (0x0001f100 + 0x4000 * (ee)) 362 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 363 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 364 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 365 (0x0001f108 + 0x4000 * (ee)) 366 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 367 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 368 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 369 (0x0001f110 + 0x4000 * (ee)) 370 /* Values here are bit positions in the GLOB_IRQ_* registers */ 371 enum gsi_global_irq_id { 372 ERROR_INT = 0x0, 373 GP_INT1 = 0x1, 374 GP_INT2 = 0x2, 375 GP_INT3 = 0x3, 376 }; 377 378 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 379 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 380 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 381 (0x0001f118 + 0x4000 * (ee)) 382 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 383 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 384 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 385 (0x0001f120 + 0x4000 * (ee)) 386 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 387 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 388 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 389 (0x0001f128 + 0x4000 * (ee)) 390 /* Values here are bit positions in the (general) GSI_IRQ_* registers */ 391 enum gsi_general_id { 392 BREAK_POINT = 0x0, 393 BUS_ERROR = 0x1, 394 CMD_FIFO_OVRFLOW = 0x2, 395 MCS_STACK_OVRFLOW = 0x3, 396 }; 397 398 #define GSI_CNTXT_INTSET_OFFSET \ 399 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 400 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 401 (0x0001f180 + 0x4000 * (ee)) 402 #define INTYPE_FMASK GENMASK(0, 0) 403 404 #define GSI_ERROR_LOG_OFFSET \ 405 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 406 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 407 (0x0001f200 + 0x4000 * (ee)) 408 #define ERR_ARG3_FMASK GENMASK(3, 0) 409 #define ERR_ARG2_FMASK GENMASK(7, 4) 410 #define ERR_ARG1_FMASK GENMASK(11, 8) 411 #define ERR_CODE_FMASK GENMASK(15, 12) 412 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 413 #define ERR_TYPE_FMASK GENMASK(27, 24) 414 #define ERR_EE_FMASK GENMASK(31, 28) 415 416 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 417 enum gsi_err_code { 418 GSI_INVALID_TRE = 0x1, 419 GSI_OUT_OF_BUFFERS = 0x2, 420 GSI_OUT_OF_RESOURCES = 0x3, 421 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 422 GSI_EVT_RING_EMPTY = 0x5, 423 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 424 /* 7 is not assigned */ 425 GSI_HWO_1 = 0x8, 426 }; 427 428 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 429 enum gsi_err_type { 430 GSI_ERR_TYPE_GLOB = 0x1, 431 GSI_ERR_TYPE_CHAN = 0x2, 432 GSI_ERR_TYPE_EVT = 0x3, 433 }; 434 435 #define GSI_ERROR_LOG_CLR_OFFSET \ 436 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 437 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 438 (0x0001f210 + 0x4000 * (ee)) 439 440 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 441 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 442 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 443 (0x0001f400 + 0x4000 * (ee)) 444 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 445 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 446 447 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 448 enum gsi_generic_ee_result { 449 GENERIC_EE_SUCCESS = 0x1, 450 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, 451 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 452 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 453 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 454 GENERIC_EE_RETRY = 0x6, 455 GENERIC_EE_NO_RESOURCES = 0x7, 456 }; 457 458 #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ 459 #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) 460 461 #endif /* _GSI_REG_H_ */ 462