1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/mutex.h> 11 #include <linux/completion.h> 12 #include <linux/io.h> 13 #include <linux/bug.h> 14 #include <linux/interrupt.h> 15 #include <linux/platform_device.h> 16 #include <linux/netdevice.h> 17 18 #include "gsi.h" 19 #include "gsi_reg.h" 20 #include "gsi_private.h" 21 #include "gsi_trans.h" 22 #include "ipa_gsi.h" 23 #include "ipa_data.h" 24 25 /** 26 * DOC: The IPA Generic Software Interface 27 * 28 * The generic software interface (GSI) is an integral component of the IPA, 29 * providing a well-defined communication layer between the AP subsystem 30 * and the IPA core. The modem uses the GSI layer as well. 31 * 32 * -------- --------- 33 * | | | | 34 * | AP +<---. .----+ Modem | 35 * | +--. | | .->+ | 36 * | | | | | | | | 37 * -------- | | | | --------- 38 * v | v | 39 * --+-+---+-+-- 40 * | GSI | 41 * |-----------| 42 * | | 43 * | IPA | 44 * | | 45 * ------------- 46 * 47 * In the above diagram, the AP and Modem represent "execution environments" 48 * (EEs), which are independent operating environments that use the IPA for 49 * data transfer. 50 * 51 * Each EE uses a set of unidirectional GSI "channels," which allow transfer 52 * of data to or from the IPA. A channel is implemented as a ring buffer, 53 * with a DRAM-resident array of "transfer elements" (TREs) available to 54 * describe transfers to or from other EEs through the IPA. A transfer 55 * element can also contain an immediate command, requesting the IPA perform 56 * actions other than data transfer. 57 * 58 * Each TRE refers to a block of data--also located DRAM. After writing one 59 * or more TREs to a channel, the writer (either the IPA or an EE) writes a 60 * doorbell register to inform the receiving side how many elements have 61 * been written. 62 * 63 * Each channel has a GSI "event ring" associated with it. An event ring 64 * is implemented very much like a channel ring, but is always directed from 65 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel 66 * events by adding an entry to the event ring associated with the channel. 67 * The GSI then writes its doorbell for the event ring, causing the target 68 * EE to be interrupted. Each entry in an event ring contains a pointer 69 * to the channel TRE whose completion the event represents. 70 * 71 * Each TRE in a channel ring has a set of flags. One flag indicates whether 72 * the completion of the transfer operation generates an entry (and possibly 73 * an interrupt) in the channel's event ring. Other flags allow transfer 74 * elements to be chained together, forming a single logical transaction. 75 * TRE flags are used to control whether and when interrupts are generated 76 * to signal completion of channel transfers. 77 * 78 * Elements in channel and event rings are completed (or consumed) strictly 79 * in order. Completion of one entry implies the completion of all preceding 80 * entries. A single completion interrupt can therefore communicate the 81 * completion of many transfers. 82 * 83 * Note that all GSI registers are little-endian, which is the assumed 84 * endianness of I/O space accesses. The accessor functions perform byte 85 * swapping if needed (i.e., for a big endian CPU). 86 */ 87 88 /* Delay period for interrupt moderation (in 32KHz IPA internal timer ticks) */ 89 #define GSI_EVT_RING_INT_MODT (32 * 1) /* 1ms under 32KHz clock */ 90 91 #define GSI_CMD_TIMEOUT 5 /* seconds */ 92 93 #define GSI_CHANNEL_STOP_RX_RETRIES 10 94 95 #define GSI_MHI_EVENT_ID_START 10 /* 1st reserved event id */ 96 #define GSI_MHI_EVENT_ID_END 16 /* Last reserved event id */ 97 98 #define GSI_ISR_MAX_ITER 50 /* Detect interrupt storms */ 99 100 /* An entry in an event ring */ 101 struct gsi_event { 102 __le64 xfer_ptr; 103 __le16 len; 104 u8 reserved1; 105 u8 code; 106 __le16 reserved2; 107 u8 type; 108 u8 chid; 109 }; 110 111 /* Hardware values from the error log register error code field */ 112 enum gsi_err_code { 113 GSI_INVALID_TRE_ERR = 0x1, 114 GSI_OUT_OF_BUFFERS_ERR = 0x2, 115 GSI_OUT_OF_RESOURCES_ERR = 0x3, 116 GSI_UNSUPPORTED_INTER_EE_OP_ERR = 0x4, 117 GSI_EVT_RING_EMPTY_ERR = 0x5, 118 GSI_NON_ALLOCATED_EVT_ACCESS_ERR = 0x6, 119 GSI_HWO_1_ERR = 0x8, 120 }; 121 122 /* Hardware values from the error log register error type field */ 123 enum gsi_err_type { 124 GSI_ERR_TYPE_GLOB = 0x1, 125 GSI_ERR_TYPE_CHAN = 0x2, 126 GSI_ERR_TYPE_EVT = 0x3, 127 }; 128 129 /* Hardware values used when programming an event ring */ 130 enum gsi_evt_chtype { 131 GSI_EVT_CHTYPE_MHI_EV = 0x0, 132 GSI_EVT_CHTYPE_XHCI_EV = 0x1, 133 GSI_EVT_CHTYPE_GPI_EV = 0x2, 134 GSI_EVT_CHTYPE_XDCI_EV = 0x3, 135 }; 136 137 /* Hardware values used when programming a channel */ 138 enum gsi_channel_protocol { 139 GSI_CHANNEL_PROTOCOL_MHI = 0x0, 140 GSI_CHANNEL_PROTOCOL_XHCI = 0x1, 141 GSI_CHANNEL_PROTOCOL_GPI = 0x2, 142 GSI_CHANNEL_PROTOCOL_XDCI = 0x3, 143 }; 144 145 /* Hardware values representing an event ring immediate command opcode */ 146 enum gsi_evt_cmd_opcode { 147 GSI_EVT_ALLOCATE = 0x0, 148 GSI_EVT_RESET = 0x9, 149 GSI_EVT_DE_ALLOC = 0xa, 150 }; 151 152 /* Hardware values representing a generic immediate command opcode */ 153 enum gsi_generic_cmd_opcode { 154 GSI_GENERIC_HALT_CHANNEL = 0x1, 155 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 156 }; 157 158 /* Hardware values representing a channel immediate command opcode */ 159 enum gsi_ch_cmd_opcode { 160 GSI_CH_ALLOCATE = 0x0, 161 GSI_CH_START = 0x1, 162 GSI_CH_STOP = 0x2, 163 GSI_CH_RESET = 0x9, 164 GSI_CH_DE_ALLOC = 0xa, 165 }; 166 167 /** gsi_channel_scratch_gpi - GPI protocol scratch register 168 * @max_outstanding_tre: 169 * Defines the maximum number of TREs allowed in a single transaction 170 * on a channel (in bytes). This determines the amount of prefetch 171 * performed by the hardware. We configure this to equal the size of 172 * the TLV FIFO for the channel. 173 * @outstanding_threshold: 174 * Defines the threshold (in bytes) determining when the sequencer 175 * should update the channel doorbell. We configure this to equal 176 * the size of two TREs. 177 */ 178 struct gsi_channel_scratch_gpi { 179 u64 reserved1; 180 u16 reserved2; 181 u16 max_outstanding_tre; 182 u16 reserved3; 183 u16 outstanding_threshold; 184 }; 185 186 /** gsi_channel_scratch - channel scratch configuration area 187 * 188 * The exact interpretation of this register is protocol-specific. 189 * We only use GPI channels; see struct gsi_channel_scratch_gpi, above. 190 */ 191 union gsi_channel_scratch { 192 struct gsi_channel_scratch_gpi gpi; 193 struct { 194 u32 word1; 195 u32 word2; 196 u32 word3; 197 u32 word4; 198 } data; 199 }; 200 201 /* Check things that can be validated at build time. */ 202 static void gsi_validate_build(void) 203 { 204 /* This is used as a divisor */ 205 BUILD_BUG_ON(!GSI_RING_ELEMENT_SIZE); 206 207 /* Code assumes the size of channel and event ring element are 208 * the same (and fixed). Make sure the size of an event ring 209 * element is what's expected. 210 */ 211 BUILD_BUG_ON(sizeof(struct gsi_event) != GSI_RING_ELEMENT_SIZE); 212 213 /* Hardware requires a 2^n ring size. We ensure the number of 214 * elements in an event ring is a power of 2 elsewhere; this 215 * ensure the elements themselves meet the requirement. 216 */ 217 BUILD_BUG_ON(!is_power_of_2(GSI_RING_ELEMENT_SIZE)); 218 219 /* The channel element size must fit in this field */ 220 BUILD_BUG_ON(GSI_RING_ELEMENT_SIZE > field_max(ELEMENT_SIZE_FMASK)); 221 222 /* The event ring element size must fit in this field */ 223 BUILD_BUG_ON(GSI_RING_ELEMENT_SIZE > field_max(EV_ELEMENT_SIZE_FMASK)); 224 } 225 226 /* Return the channel id associated with a given channel */ 227 static u32 gsi_channel_id(struct gsi_channel *channel) 228 { 229 return channel - &channel->gsi->channel[0]; 230 } 231 232 static void gsi_irq_ieob_enable(struct gsi *gsi, u32 evt_ring_id) 233 { 234 u32 val; 235 236 gsi->event_enable_bitmap |= BIT(evt_ring_id); 237 val = gsi->event_enable_bitmap; 238 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); 239 } 240 241 static void gsi_irq_ieob_disable(struct gsi *gsi, u32 evt_ring_id) 242 { 243 u32 val; 244 245 gsi->event_enable_bitmap &= ~BIT(evt_ring_id); 246 val = gsi->event_enable_bitmap; 247 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); 248 } 249 250 /* Enable all GSI_interrupt types */ 251 static void gsi_irq_enable(struct gsi *gsi) 252 { 253 u32 val; 254 255 /* We don't use inter-EE channel or event interrupts */ 256 val = GSI_CNTXT_TYPE_IRQ_MSK_ALL; 257 val &= ~MSK_INTER_EE_CH_CTRL_FMASK; 258 val &= ~MSK_INTER_EE_EV_CTRL_FMASK; 259 iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); 260 261 val = GENMASK(gsi->channel_count - 1, 0); 262 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); 263 264 val = GENMASK(gsi->evt_ring_count - 1, 0); 265 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); 266 267 /* Each IEOB interrupt is enabled (later) as needed by channels */ 268 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); 269 270 val = GSI_CNTXT_GLOB_IRQ_ALL; 271 iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); 272 273 /* Never enable GSI_BREAK_POINT */ 274 val = GSI_CNTXT_GSI_IRQ_ALL & ~EN_BREAK_POINT_FMASK; 275 iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); 276 } 277 278 /* Disable all GSI_interrupt types */ 279 static void gsi_irq_disable(struct gsi *gsi) 280 { 281 iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); 282 iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); 283 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); 284 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); 285 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); 286 iowrite32(0, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); 287 } 288 289 /* Return the virtual address associated with a ring index */ 290 void *gsi_ring_virt(struct gsi_ring *ring, u32 index) 291 { 292 /* Note: index *must* be used modulo the ring count here */ 293 return ring->virt + (index % ring->count) * GSI_RING_ELEMENT_SIZE; 294 } 295 296 /* Return the 32-bit DMA address associated with a ring index */ 297 static u32 gsi_ring_addr(struct gsi_ring *ring, u32 index) 298 { 299 return (ring->addr & GENMASK(31, 0)) + index * GSI_RING_ELEMENT_SIZE; 300 } 301 302 /* Return the ring index of a 32-bit ring offset */ 303 static u32 gsi_ring_index(struct gsi_ring *ring, u32 offset) 304 { 305 return (offset - gsi_ring_addr(ring, 0)) / GSI_RING_ELEMENT_SIZE; 306 } 307 308 /* Issue a GSI command by writing a value to a register, then wait for 309 * completion to be signaled. Returns true if the command completes 310 * or false if it times out. 311 */ 312 static bool 313 gsi_command(struct gsi *gsi, u32 reg, u32 val, struct completion *completion) 314 { 315 reinit_completion(completion); 316 317 iowrite32(val, gsi->virt + reg); 318 319 return !!wait_for_completion_timeout(completion, GSI_CMD_TIMEOUT * HZ); 320 } 321 322 /* Return the hardware's notion of the current state of an event ring */ 323 static enum gsi_evt_ring_state 324 gsi_evt_ring_state(struct gsi *gsi, u32 evt_ring_id) 325 { 326 u32 val; 327 328 val = ioread32(gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); 329 330 return u32_get_bits(val, EV_CHSTATE_FMASK); 331 } 332 333 /* Issue an event ring command and wait for it to complete */ 334 static int evt_ring_command(struct gsi *gsi, u32 evt_ring_id, 335 enum gsi_evt_cmd_opcode opcode) 336 { 337 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 338 struct completion *completion = &evt_ring->completion; 339 u32 val; 340 341 val = u32_encode_bits(evt_ring_id, EV_CHID_FMASK); 342 val |= u32_encode_bits(opcode, EV_OPCODE_FMASK); 343 344 if (gsi_command(gsi, GSI_EV_CH_CMD_OFFSET, val, completion)) 345 return 0; /* Success! */ 346 347 dev_err(gsi->dev, "GSI command %u to event ring %u timed out " 348 "(state is %u)\n", opcode, evt_ring_id, evt_ring->state); 349 350 return -ETIMEDOUT; 351 } 352 353 /* Allocate an event ring in NOT_ALLOCATED state */ 354 static int gsi_evt_ring_alloc_command(struct gsi *gsi, u32 evt_ring_id) 355 { 356 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 357 int ret; 358 359 /* Get initial event ring state */ 360 evt_ring->state = gsi_evt_ring_state(gsi, evt_ring_id); 361 362 if (evt_ring->state != GSI_EVT_RING_STATE_NOT_ALLOCATED) 363 return -EINVAL; 364 365 ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_ALLOCATE); 366 if (!ret && evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) { 367 dev_err(gsi->dev, "bad event ring state (%u) after alloc\n", 368 evt_ring->state); 369 ret = -EIO; 370 } 371 372 return ret; 373 } 374 375 /* Reset a GSI event ring in ALLOCATED or ERROR state. */ 376 static void gsi_evt_ring_reset_command(struct gsi *gsi, u32 evt_ring_id) 377 { 378 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 379 enum gsi_evt_ring_state state = evt_ring->state; 380 int ret; 381 382 if (state != GSI_EVT_RING_STATE_ALLOCATED && 383 state != GSI_EVT_RING_STATE_ERROR) { 384 dev_err(gsi->dev, "bad event ring state (%u) before reset\n", 385 evt_ring->state); 386 return; 387 } 388 389 ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_RESET); 390 if (!ret && evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) 391 dev_err(gsi->dev, "bad event ring state (%u) after reset\n", 392 evt_ring->state); 393 } 394 395 /* Issue a hardware de-allocation request for an allocated event ring */ 396 static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id) 397 { 398 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 399 int ret; 400 401 if (evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) { 402 dev_err(gsi->dev, "bad event ring state (%u) before dealloc\n", 403 evt_ring->state); 404 return; 405 } 406 407 ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_DE_ALLOC); 408 if (!ret && evt_ring->state != GSI_EVT_RING_STATE_NOT_ALLOCATED) 409 dev_err(gsi->dev, "bad event ring state (%u) after dealloc\n", 410 evt_ring->state); 411 } 412 413 /* Fetch the current state of a channel from hardware */ 414 static enum gsi_channel_state gsi_channel_state(struct gsi_channel *channel) 415 { 416 u32 channel_id = gsi_channel_id(channel); 417 void *virt = channel->gsi->virt; 418 u32 val; 419 420 val = ioread32(virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id)); 421 422 return u32_get_bits(val, CHSTATE_FMASK); 423 } 424 425 /* Issue a channel command and wait for it to complete */ 426 static int 427 gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode) 428 { 429 struct completion *completion = &channel->completion; 430 u32 channel_id = gsi_channel_id(channel); 431 struct gsi *gsi = channel->gsi; 432 u32 val; 433 434 val = u32_encode_bits(channel_id, CH_CHID_FMASK); 435 val |= u32_encode_bits(opcode, CH_OPCODE_FMASK); 436 437 if (gsi_command(gsi, GSI_CH_CMD_OFFSET, val, completion)) 438 return 0; /* Success! */ 439 440 dev_err(gsi->dev, 441 "GSI command %u to channel %u timed out (state is %u)\n", 442 opcode, channel_id, gsi_channel_state(channel)); 443 444 return -ETIMEDOUT; 445 } 446 447 /* Allocate GSI channel in NOT_ALLOCATED state */ 448 static int gsi_channel_alloc_command(struct gsi *gsi, u32 channel_id) 449 { 450 struct gsi_channel *channel = &gsi->channel[channel_id]; 451 enum gsi_channel_state state; 452 int ret; 453 454 /* Get initial channel state */ 455 state = gsi_channel_state(channel); 456 if (state != GSI_CHANNEL_STATE_NOT_ALLOCATED) 457 return -EINVAL; 458 459 ret = gsi_channel_command(channel, GSI_CH_ALLOCATE); 460 461 /* Channel state will normally have been updated */ 462 state = gsi_channel_state(channel); 463 if (!ret && state != GSI_CHANNEL_STATE_ALLOCATED) { 464 dev_err(gsi->dev, "bad channel state (%u) after alloc\n", 465 state); 466 ret = -EIO; 467 } 468 469 return ret; 470 } 471 472 /* Start an ALLOCATED channel */ 473 static int gsi_channel_start_command(struct gsi_channel *channel) 474 { 475 enum gsi_channel_state state; 476 int ret; 477 478 state = gsi_channel_state(channel); 479 if (state != GSI_CHANNEL_STATE_ALLOCATED && 480 state != GSI_CHANNEL_STATE_STOPPED) 481 return -EINVAL; 482 483 ret = gsi_channel_command(channel, GSI_CH_START); 484 485 /* Channel state will normally have been updated */ 486 state = gsi_channel_state(channel); 487 if (!ret && state != GSI_CHANNEL_STATE_STARTED) { 488 dev_err(channel->gsi->dev, 489 "bad channel state (%u) after start\n", state); 490 ret = -EIO; 491 } 492 493 return ret; 494 } 495 496 /* Stop a GSI channel in STARTED state */ 497 static int gsi_channel_stop_command(struct gsi_channel *channel) 498 { 499 enum gsi_channel_state state; 500 int ret; 501 502 state = gsi_channel_state(channel); 503 504 /* Channel could have entered STOPPED state since last call 505 * if it timed out. If so, we're done. 506 */ 507 if (state == GSI_CHANNEL_STATE_STOPPED) 508 return 0; 509 510 if (state != GSI_CHANNEL_STATE_STARTED && 511 state != GSI_CHANNEL_STATE_STOP_IN_PROC) 512 return -EINVAL; 513 514 ret = gsi_channel_command(channel, GSI_CH_STOP); 515 516 /* Channel state will normally have been updated */ 517 state = gsi_channel_state(channel); 518 if (ret || state == GSI_CHANNEL_STATE_STOPPED) 519 return ret; 520 521 /* We may have to try again if stop is in progress */ 522 if (state == GSI_CHANNEL_STATE_STOP_IN_PROC) 523 return -EAGAIN; 524 525 dev_err(channel->gsi->dev, 526 "bad channel state (%u) after stop\n", state); 527 528 return -EIO; 529 } 530 531 /* Reset a GSI channel in ALLOCATED or ERROR state. */ 532 static void gsi_channel_reset_command(struct gsi_channel *channel) 533 { 534 enum gsi_channel_state state; 535 int ret; 536 537 msleep(1); /* A short delay is required before a RESET command */ 538 539 state = gsi_channel_state(channel); 540 if (state != GSI_CHANNEL_STATE_STOPPED && 541 state != GSI_CHANNEL_STATE_ERROR) { 542 dev_err(channel->gsi->dev, 543 "bad channel state (%u) before reset\n", state); 544 return; 545 } 546 547 ret = gsi_channel_command(channel, GSI_CH_RESET); 548 549 /* Channel state will normally have been updated */ 550 state = gsi_channel_state(channel); 551 if (!ret && state != GSI_CHANNEL_STATE_ALLOCATED) 552 dev_err(channel->gsi->dev, 553 "bad channel state (%u) after reset\n", state); 554 } 555 556 /* Deallocate an ALLOCATED GSI channel */ 557 static void gsi_channel_de_alloc_command(struct gsi *gsi, u32 channel_id) 558 { 559 struct gsi_channel *channel = &gsi->channel[channel_id]; 560 enum gsi_channel_state state; 561 int ret; 562 563 state = gsi_channel_state(channel); 564 if (state != GSI_CHANNEL_STATE_ALLOCATED) { 565 dev_err(gsi->dev, 566 "bad channel state (%u) before dealloc\n", state); 567 return; 568 } 569 570 ret = gsi_channel_command(channel, GSI_CH_DE_ALLOC); 571 572 /* Channel state will normally have been updated */ 573 state = gsi_channel_state(channel); 574 if (!ret && state != GSI_CHANNEL_STATE_NOT_ALLOCATED) 575 dev_err(gsi->dev, 576 "bad channel state (%u) after dealloc\n", state); 577 } 578 579 /* Ring an event ring doorbell, reporting the last entry processed by the AP. 580 * The index argument (modulo the ring count) is the first unfilled entry, so 581 * we supply one less than that with the doorbell. Update the event ring 582 * index field with the value provided. 583 */ 584 static void gsi_evt_ring_doorbell(struct gsi *gsi, u32 evt_ring_id, u32 index) 585 { 586 struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring; 587 u32 val; 588 589 ring->index = index; /* Next unused entry */ 590 591 /* Note: index *must* be used modulo the ring count here */ 592 val = gsi_ring_addr(ring, (index - 1) % ring->count); 593 iowrite32(val, gsi->virt + GSI_EV_CH_E_DOORBELL_0_OFFSET(evt_ring_id)); 594 } 595 596 /* Program an event ring for use */ 597 static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id) 598 { 599 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 600 size_t size = evt_ring->ring.count * GSI_RING_ELEMENT_SIZE; 601 u32 val; 602 603 val = u32_encode_bits(GSI_EVT_CHTYPE_GPI_EV, EV_CHTYPE_FMASK); 604 val |= EV_INTYPE_FMASK; 605 val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, EV_ELEMENT_SIZE_FMASK); 606 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); 607 608 val = u32_encode_bits(size, EV_R_LENGTH_FMASK); 609 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id)); 610 611 /* The context 2 and 3 registers store the low-order and 612 * high-order 32 bits of the address of the event ring, 613 * respectively. 614 */ 615 val = evt_ring->ring.addr & GENMASK(31, 0); 616 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id)); 617 618 val = evt_ring->ring.addr >> 32; 619 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id)); 620 621 /* Enable interrupt moderation by setting the moderation delay */ 622 val = u32_encode_bits(GSI_EVT_RING_INT_MODT, MODT_FMASK); 623 val |= u32_encode_bits(1, MODC_FMASK); /* comes from channel */ 624 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_8_OFFSET(evt_ring_id)); 625 626 /* No MSI write data, and MSI address high and low address is 0 */ 627 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_9_OFFSET(evt_ring_id)); 628 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_10_OFFSET(evt_ring_id)); 629 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_11_OFFSET(evt_ring_id)); 630 631 /* We don't need to get event read pointer updates */ 632 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_12_OFFSET(evt_ring_id)); 633 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_13_OFFSET(evt_ring_id)); 634 635 /* Finally, tell the hardware we've completed event 0 (arbitrary) */ 636 gsi_evt_ring_doorbell(gsi, evt_ring_id, 0); 637 } 638 639 /* Return the last (most recent) transaction completed on a channel. */ 640 static struct gsi_trans *gsi_channel_trans_last(struct gsi_channel *channel) 641 { 642 struct gsi_trans_info *trans_info = &channel->trans_info; 643 struct gsi_trans *trans; 644 645 spin_lock_bh(&trans_info->spinlock); 646 647 if (!list_empty(&trans_info->complete)) 648 trans = list_last_entry(&trans_info->complete, 649 struct gsi_trans, links); 650 else if (!list_empty(&trans_info->polled)) 651 trans = list_last_entry(&trans_info->polled, 652 struct gsi_trans, links); 653 else 654 trans = NULL; 655 656 /* Caller will wait for this, so take a reference */ 657 if (trans) 658 refcount_inc(&trans->refcount); 659 660 spin_unlock_bh(&trans_info->spinlock); 661 662 return trans; 663 } 664 665 /* Wait for transaction activity on a channel to complete */ 666 static void gsi_channel_trans_quiesce(struct gsi_channel *channel) 667 { 668 struct gsi_trans *trans; 669 670 /* Get the last transaction, and wait for it to complete */ 671 trans = gsi_channel_trans_last(channel); 672 if (trans) { 673 wait_for_completion(&trans->completion); 674 gsi_trans_free(trans); 675 } 676 } 677 678 /* Stop channel activity. Transactions may not be allocated until thawed. */ 679 static void gsi_channel_freeze(struct gsi_channel *channel) 680 { 681 gsi_channel_trans_quiesce(channel); 682 683 napi_disable(&channel->napi); 684 685 gsi_irq_ieob_disable(channel->gsi, channel->evt_ring_id); 686 } 687 688 /* Allow transactions to be used on the channel again. */ 689 static void gsi_channel_thaw(struct gsi_channel *channel) 690 { 691 gsi_irq_ieob_enable(channel->gsi, channel->evt_ring_id); 692 693 napi_enable(&channel->napi); 694 } 695 696 /* Program a channel for use */ 697 static void gsi_channel_program(struct gsi_channel *channel, bool doorbell) 698 { 699 size_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE; 700 u32 channel_id = gsi_channel_id(channel); 701 union gsi_channel_scratch scr = { }; 702 struct gsi_channel_scratch_gpi *gpi; 703 struct gsi *gsi = channel->gsi; 704 u32 wrr_weight = 0; 705 u32 val; 706 707 /* Arbitrarily pick TRE 0 as the first channel element to use */ 708 channel->tre_ring.index = 0; 709 710 /* We program all channels to use GPI protocol */ 711 val = u32_encode_bits(GSI_CHANNEL_PROTOCOL_GPI, CHTYPE_PROTOCOL_FMASK); 712 if (channel->toward_ipa) 713 val |= CHTYPE_DIR_FMASK; 714 val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK); 715 val |= u32_encode_bits(GSI_RING_ELEMENT_SIZE, ELEMENT_SIZE_FMASK); 716 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id)); 717 718 val = u32_encode_bits(size, R_LENGTH_FMASK); 719 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id)); 720 721 /* The context 2 and 3 registers store the low-order and 722 * high-order 32 bits of the address of the channel ring, 723 * respectively. 724 */ 725 val = channel->tre_ring.addr & GENMASK(31, 0); 726 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id)); 727 728 val = channel->tre_ring.addr >> 32; 729 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id)); 730 731 /* Command channel gets low weighted round-robin priority */ 732 if (channel->command) 733 wrr_weight = field_max(WRR_WEIGHT_FMASK); 734 val = u32_encode_bits(wrr_weight, WRR_WEIGHT_FMASK); 735 736 /* Max prefetch is 1 segment (do not set MAX_PREFETCH_FMASK) */ 737 738 /* Enable the doorbell engine if requested */ 739 if (doorbell) 740 val |= USE_DB_ENG_FMASK; 741 742 if (!channel->use_prefetch) 743 val |= USE_ESCAPE_BUF_ONLY_FMASK; 744 745 iowrite32(val, gsi->virt + GSI_CH_C_QOS_OFFSET(channel_id)); 746 747 /* Now update the scratch registers for GPI protocol */ 748 gpi = &scr.gpi; 749 gpi->max_outstanding_tre = gsi_channel_trans_tre_max(gsi, channel_id) * 750 GSI_RING_ELEMENT_SIZE; 751 gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE; 752 753 val = scr.data.word1; 754 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_0_OFFSET(channel_id)); 755 756 val = scr.data.word2; 757 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_1_OFFSET(channel_id)); 758 759 val = scr.data.word3; 760 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_2_OFFSET(channel_id)); 761 762 /* We must preserve the upper 16 bits of the last scratch register. 763 * The next sequence assumes those bits remain unchanged between the 764 * read and the write. 765 */ 766 val = ioread32(gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); 767 val = (scr.data.word4 & GENMASK(31, 16)) | (val & GENMASK(15, 0)); 768 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); 769 770 /* All done! */ 771 } 772 773 static void gsi_channel_deprogram(struct gsi_channel *channel) 774 { 775 /* Nothing to do */ 776 } 777 778 /* Start an allocated GSI channel */ 779 int gsi_channel_start(struct gsi *gsi, u32 channel_id) 780 { 781 struct gsi_channel *channel = &gsi->channel[channel_id]; 782 int ret; 783 784 mutex_lock(&gsi->mutex); 785 786 ret = gsi_channel_start_command(channel); 787 788 mutex_unlock(&gsi->mutex); 789 790 gsi_channel_thaw(channel); 791 792 return ret; 793 } 794 795 /* Stop a started channel */ 796 int gsi_channel_stop(struct gsi *gsi, u32 channel_id) 797 { 798 struct gsi_channel *channel = &gsi->channel[channel_id]; 799 u32 retries; 800 int ret; 801 802 gsi_channel_freeze(channel); 803 804 /* RX channels might require a little time to enter STOPPED state */ 805 retries = channel->toward_ipa ? 0 : GSI_CHANNEL_STOP_RX_RETRIES; 806 807 mutex_lock(&gsi->mutex); 808 809 do { 810 ret = gsi_channel_stop_command(channel); 811 if (ret != -EAGAIN) 812 break; 813 msleep(1); 814 } while (retries--); 815 816 mutex_unlock(&gsi->mutex); 817 818 /* Thaw the channel if we need to retry (or on error) */ 819 if (ret) 820 gsi_channel_thaw(channel); 821 822 return ret; 823 } 824 825 /* Reset and reconfigure a channel (possibly leaving doorbell disabled) */ 826 void gsi_channel_reset(struct gsi *gsi, u32 channel_id, bool legacy) 827 { 828 struct gsi_channel *channel = &gsi->channel[channel_id]; 829 830 mutex_lock(&gsi->mutex); 831 832 gsi_channel_reset_command(channel); 833 /* Due to a hardware quirk we may need to reset RX channels twice. */ 834 if (legacy && !channel->toward_ipa) 835 gsi_channel_reset_command(channel); 836 837 gsi_channel_program(channel, legacy); 838 gsi_channel_trans_cancel_pending(channel); 839 840 mutex_unlock(&gsi->mutex); 841 } 842 843 /* Stop a STARTED channel for suspend (using stop if requested) */ 844 int gsi_channel_suspend(struct gsi *gsi, u32 channel_id, bool stop) 845 { 846 struct gsi_channel *channel = &gsi->channel[channel_id]; 847 848 if (stop) 849 return gsi_channel_stop(gsi, channel_id); 850 851 gsi_channel_freeze(channel); 852 853 return 0; 854 } 855 856 /* Resume a suspended channel (starting will be requested if STOPPED) */ 857 int gsi_channel_resume(struct gsi *gsi, u32 channel_id, bool start) 858 { 859 struct gsi_channel *channel = &gsi->channel[channel_id]; 860 861 if (start) 862 return gsi_channel_start(gsi, channel_id); 863 864 gsi_channel_thaw(channel); 865 866 return 0; 867 } 868 869 /** 870 * gsi_channel_tx_queued() - Report queued TX transfers for a channel 871 * @channel: Channel for which to report 872 * 873 * Report to the network stack the number of bytes and transactions that 874 * have been queued to hardware since last call. This and the next function 875 * supply information used by the network stack for throttling. 876 * 877 * For each channel we track the number of transactions used and bytes of 878 * data those transactions represent. We also track what those values are 879 * each time this function is called. Subtracting the two tells us 880 * the number of bytes and transactions that have been added between 881 * successive calls. 882 * 883 * Calling this each time we ring the channel doorbell allows us to 884 * provide accurate information to the network stack about how much 885 * work we've given the hardware at any point in time. 886 */ 887 void gsi_channel_tx_queued(struct gsi_channel *channel) 888 { 889 u32 trans_count; 890 u32 byte_count; 891 892 byte_count = channel->byte_count - channel->queued_byte_count; 893 trans_count = channel->trans_count - channel->queued_trans_count; 894 channel->queued_byte_count = channel->byte_count; 895 channel->queued_trans_count = channel->trans_count; 896 897 ipa_gsi_channel_tx_queued(channel->gsi, gsi_channel_id(channel), 898 trans_count, byte_count); 899 } 900 901 /** 902 * gsi_channel_tx_update() - Report completed TX transfers 903 * @channel: Channel that has completed transmitting packets 904 * @trans: Last transation known to be complete 905 * 906 * Compute the number of transactions and bytes that have been transferred 907 * over a TX channel since the given transaction was committed. Report this 908 * information to the network stack. 909 * 910 * At the time a transaction is committed, we record its channel's 911 * committed transaction and byte counts *in the transaction*. 912 * Completions are signaled by the hardware with an interrupt, and 913 * we can determine the latest completed transaction at that time. 914 * 915 * The difference between the byte/transaction count recorded in 916 * the transaction and the count last time we recorded a completion 917 * tells us exactly how much data has been transferred between 918 * completions. 919 * 920 * Calling this each time we learn of a newly-completed transaction 921 * allows us to provide accurate information to the network stack 922 * about how much work has been completed by the hardware at a given 923 * point in time. 924 */ 925 static void 926 gsi_channel_tx_update(struct gsi_channel *channel, struct gsi_trans *trans) 927 { 928 u64 byte_count = trans->byte_count + trans->len; 929 u64 trans_count = trans->trans_count + 1; 930 931 byte_count -= channel->compl_byte_count; 932 channel->compl_byte_count += byte_count; 933 trans_count -= channel->compl_trans_count; 934 channel->compl_trans_count += trans_count; 935 936 ipa_gsi_channel_tx_completed(channel->gsi, gsi_channel_id(channel), 937 trans_count, byte_count); 938 } 939 940 /* Channel control interrupt handler */ 941 static void gsi_isr_chan_ctrl(struct gsi *gsi) 942 { 943 u32 channel_mask; 944 945 channel_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_CH_IRQ_OFFSET); 946 iowrite32(channel_mask, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET); 947 948 while (channel_mask) { 949 u32 channel_id = __ffs(channel_mask); 950 struct gsi_channel *channel; 951 952 channel_mask ^= BIT(channel_id); 953 954 channel = &gsi->channel[channel_id]; 955 956 complete(&channel->completion); 957 } 958 } 959 960 /* Event ring control interrupt handler */ 961 static void gsi_isr_evt_ctrl(struct gsi *gsi) 962 { 963 u32 event_mask; 964 965 event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET); 966 iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET); 967 968 while (event_mask) { 969 u32 evt_ring_id = __ffs(event_mask); 970 struct gsi_evt_ring *evt_ring; 971 972 event_mask ^= BIT(evt_ring_id); 973 974 evt_ring = &gsi->evt_ring[evt_ring_id]; 975 evt_ring->state = gsi_evt_ring_state(gsi, evt_ring_id); 976 977 complete(&evt_ring->completion); 978 } 979 } 980 981 /* Global channel error interrupt handler */ 982 static void 983 gsi_isr_glob_chan_err(struct gsi *gsi, u32 err_ee, u32 channel_id, u32 code) 984 { 985 if (code == GSI_OUT_OF_RESOURCES_ERR) { 986 dev_err(gsi->dev, "channel %u out of resources\n", channel_id); 987 complete(&gsi->channel[channel_id].completion); 988 return; 989 } 990 991 /* Report, but otherwise ignore all other error codes */ 992 dev_err(gsi->dev, "channel %u global error ee 0x%08x code 0x%08x\n", 993 channel_id, err_ee, code); 994 } 995 996 /* Global event error interrupt handler */ 997 static void 998 gsi_isr_glob_evt_err(struct gsi *gsi, u32 err_ee, u32 evt_ring_id, u32 code) 999 { 1000 if (code == GSI_OUT_OF_RESOURCES_ERR) { 1001 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; 1002 u32 channel_id = gsi_channel_id(evt_ring->channel); 1003 1004 complete(&evt_ring->completion); 1005 dev_err(gsi->dev, "evt_ring for channel %u out of resources\n", 1006 channel_id); 1007 return; 1008 } 1009 1010 /* Report, but otherwise ignore all other error codes */ 1011 dev_err(gsi->dev, "event ring %u global error ee %u code 0x%08x\n", 1012 evt_ring_id, err_ee, code); 1013 } 1014 1015 /* Global error interrupt handler */ 1016 static void gsi_isr_glob_err(struct gsi *gsi) 1017 { 1018 enum gsi_err_type type; 1019 enum gsi_err_code code; 1020 u32 which; 1021 u32 val; 1022 u32 ee; 1023 1024 /* Get the logged error, then reinitialize the log */ 1025 val = ioread32(gsi->virt + GSI_ERROR_LOG_OFFSET); 1026 iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); 1027 iowrite32(~0, gsi->virt + GSI_ERROR_LOG_CLR_OFFSET); 1028 1029 ee = u32_get_bits(val, ERR_EE_FMASK); 1030 which = u32_get_bits(val, ERR_VIRT_IDX_FMASK); 1031 type = u32_get_bits(val, ERR_TYPE_FMASK); 1032 code = u32_get_bits(val, ERR_CODE_FMASK); 1033 1034 if (type == GSI_ERR_TYPE_CHAN) 1035 gsi_isr_glob_chan_err(gsi, ee, which, code); 1036 else if (type == GSI_ERR_TYPE_EVT) 1037 gsi_isr_glob_evt_err(gsi, ee, which, code); 1038 else /* type GSI_ERR_TYPE_GLOB should be fatal */ 1039 dev_err(gsi->dev, "unexpected global error 0x%08x\n", type); 1040 } 1041 1042 /* Generic EE interrupt handler */ 1043 static void gsi_isr_gp_int1(struct gsi *gsi) 1044 { 1045 u32 result; 1046 u32 val; 1047 1048 val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); 1049 result = u32_get_bits(val, GENERIC_EE_RESULT_FMASK); 1050 if (result != GENERIC_EE_SUCCESS_FVAL) 1051 dev_err(gsi->dev, "global INT1 generic result %u\n", result); 1052 1053 complete(&gsi->completion); 1054 } 1055 1056 /* Inter-EE interrupt handler */ 1057 static void gsi_isr_glob_ee(struct gsi *gsi) 1058 { 1059 u32 val; 1060 1061 val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET); 1062 1063 if (val & ERROR_INT_FMASK) 1064 gsi_isr_glob_err(gsi); 1065 1066 iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET); 1067 1068 val &= ~ERROR_INT_FMASK; 1069 1070 if (val & EN_GP_INT1_FMASK) { 1071 val ^= EN_GP_INT1_FMASK; 1072 gsi_isr_gp_int1(gsi); 1073 } 1074 1075 if (val) 1076 dev_err(gsi->dev, "unexpected global interrupt 0x%08x\n", val); 1077 } 1078 1079 /* I/O completion interrupt event */ 1080 static void gsi_isr_ieob(struct gsi *gsi) 1081 { 1082 u32 event_mask; 1083 1084 event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET); 1085 iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET); 1086 1087 while (event_mask) { 1088 u32 evt_ring_id = __ffs(event_mask); 1089 1090 event_mask ^= BIT(evt_ring_id); 1091 1092 gsi_irq_ieob_disable(gsi, evt_ring_id); 1093 napi_schedule(&gsi->evt_ring[evt_ring_id].channel->napi); 1094 } 1095 } 1096 1097 /* General event interrupts represent serious problems, so report them */ 1098 static void gsi_isr_general(struct gsi *gsi) 1099 { 1100 struct device *dev = gsi->dev; 1101 u32 val; 1102 1103 val = ioread32(gsi->virt + GSI_CNTXT_GSI_IRQ_STTS_OFFSET); 1104 iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_CLR_OFFSET); 1105 1106 if (val) 1107 dev_err(dev, "unexpected general interrupt 0x%08x\n", val); 1108 } 1109 1110 /** 1111 * gsi_isr() - Top level GSI interrupt service routine 1112 * @irq: Interrupt number (ignored) 1113 * @dev_id: GSI pointer supplied to request_irq() 1114 * 1115 * This is the main handler function registered for the GSI IRQ. Each type 1116 * of interrupt has a separate handler function that is called from here. 1117 */ 1118 static irqreturn_t gsi_isr(int irq, void *dev_id) 1119 { 1120 struct gsi *gsi = dev_id; 1121 u32 intr_mask; 1122 u32 cnt = 0; 1123 1124 while ((intr_mask = ioread32(gsi->virt + GSI_CNTXT_TYPE_IRQ_OFFSET))) { 1125 /* intr_mask contains bitmask of pending GSI interrupts */ 1126 do { 1127 u32 gsi_intr = BIT(__ffs(intr_mask)); 1128 1129 intr_mask ^= gsi_intr; 1130 1131 switch (gsi_intr) { 1132 case CH_CTRL_FMASK: 1133 gsi_isr_chan_ctrl(gsi); 1134 break; 1135 case EV_CTRL_FMASK: 1136 gsi_isr_evt_ctrl(gsi); 1137 break; 1138 case GLOB_EE_FMASK: 1139 gsi_isr_glob_ee(gsi); 1140 break; 1141 case IEOB_FMASK: 1142 gsi_isr_ieob(gsi); 1143 break; 1144 case GENERAL_FMASK: 1145 gsi_isr_general(gsi); 1146 break; 1147 default: 1148 dev_err(gsi->dev, 1149 "%s: unrecognized type 0x%08x\n", 1150 __func__, gsi_intr); 1151 break; 1152 } 1153 } while (intr_mask); 1154 1155 if (++cnt > GSI_ISR_MAX_ITER) { 1156 dev_err(gsi->dev, "interrupt flood\n"); 1157 break; 1158 } 1159 } 1160 1161 return IRQ_HANDLED; 1162 } 1163 1164 /* Return the transaction associated with a transfer completion event */ 1165 static struct gsi_trans *gsi_event_trans(struct gsi_channel *channel, 1166 struct gsi_event *event) 1167 { 1168 u32 tre_offset; 1169 u32 tre_index; 1170 1171 /* Event xfer_ptr records the TRE it's associated with */ 1172 tre_offset = le64_to_cpu(event->xfer_ptr) & GENMASK(31, 0); 1173 tre_index = gsi_ring_index(&channel->tre_ring, tre_offset); 1174 1175 return gsi_channel_trans_mapped(channel, tre_index); 1176 } 1177 1178 /** 1179 * gsi_evt_ring_rx_update() - Record lengths of received data 1180 * @evt_ring: Event ring associated with channel that received packets 1181 * @index: Event index in ring reported by hardware 1182 * 1183 * Events for RX channels contain the actual number of bytes received into 1184 * the buffer. Every event has a transaction associated with it, and here 1185 * we update transactions to record their actual received lengths. 1186 * 1187 * This function is called whenever we learn that the GSI hardware has filled 1188 * new events since the last time we checked. The ring's index field tells 1189 * the first entry in need of processing. The index provided is the 1190 * first *unfilled* event in the ring (following the last filled one). 1191 * 1192 * Events are sequential within the event ring, and transactions are 1193 * sequential within the transaction pool. 1194 * 1195 * Note that @index always refers to an element *within* the event ring. 1196 */ 1197 static void gsi_evt_ring_rx_update(struct gsi_evt_ring *evt_ring, u32 index) 1198 { 1199 struct gsi_channel *channel = evt_ring->channel; 1200 struct gsi_ring *ring = &evt_ring->ring; 1201 struct gsi_trans_info *trans_info; 1202 struct gsi_event *event_done; 1203 struct gsi_event *event; 1204 struct gsi_trans *trans; 1205 u32 byte_count = 0; 1206 u32 old_index; 1207 u32 event_avail; 1208 1209 trans_info = &channel->trans_info; 1210 1211 /* We'll start with the oldest un-processed event. RX channels 1212 * replenish receive buffers in single-TRE transactions, so we 1213 * can just map that event to its transaction. Transactions 1214 * associated with completion events are consecutive. 1215 */ 1216 old_index = ring->index; 1217 event = gsi_ring_virt(ring, old_index); 1218 trans = gsi_event_trans(channel, event); 1219 1220 /* Compute the number of events to process before we wrap, 1221 * and determine when we'll be done processing events. 1222 */ 1223 event_avail = ring->count - old_index % ring->count; 1224 event_done = gsi_ring_virt(ring, index); 1225 do { 1226 trans->len = __le16_to_cpu(event->len); 1227 byte_count += trans->len; 1228 1229 /* Move on to the next event and transaction */ 1230 if (--event_avail) 1231 event++; 1232 else 1233 event = gsi_ring_virt(ring, 0); 1234 trans = gsi_trans_pool_next(&trans_info->pool, trans); 1235 } while (event != event_done); 1236 1237 /* We record RX bytes when they are received */ 1238 channel->byte_count += byte_count; 1239 channel->trans_count++; 1240 } 1241 1242 /* Initialize a ring, including allocating DMA memory for its entries */ 1243 static int gsi_ring_alloc(struct gsi *gsi, struct gsi_ring *ring, u32 count) 1244 { 1245 size_t size = count * GSI_RING_ELEMENT_SIZE; 1246 struct device *dev = gsi->dev; 1247 dma_addr_t addr; 1248 1249 /* Hardware requires a 2^n ring size, with alignment equal to size */ 1250 ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL); 1251 if (ring->virt && addr % size) { 1252 dma_free_coherent(dev, size, ring->virt, ring->addr); 1253 dev_err(dev, "unable to alloc 0x%zx-aligned ring buffer\n", 1254 size); 1255 return -EINVAL; /* Not a good error value, but distinct */ 1256 } else if (!ring->virt) { 1257 return -ENOMEM; 1258 } 1259 ring->addr = addr; 1260 ring->count = count; 1261 1262 return 0; 1263 } 1264 1265 /* Free a previously-allocated ring */ 1266 static void gsi_ring_free(struct gsi *gsi, struct gsi_ring *ring) 1267 { 1268 size_t size = ring->count * GSI_RING_ELEMENT_SIZE; 1269 1270 dma_free_coherent(gsi->dev, size, ring->virt, ring->addr); 1271 } 1272 1273 /* Allocate an available event ring id */ 1274 static int gsi_evt_ring_id_alloc(struct gsi *gsi) 1275 { 1276 u32 evt_ring_id; 1277 1278 if (gsi->event_bitmap == ~0U) { 1279 dev_err(gsi->dev, "event rings exhausted\n"); 1280 return -ENOSPC; 1281 } 1282 1283 evt_ring_id = ffz(gsi->event_bitmap); 1284 gsi->event_bitmap |= BIT(evt_ring_id); 1285 1286 return (int)evt_ring_id; 1287 } 1288 1289 /* Free a previously-allocated event ring id */ 1290 static void gsi_evt_ring_id_free(struct gsi *gsi, u32 evt_ring_id) 1291 { 1292 gsi->event_bitmap &= ~BIT(evt_ring_id); 1293 } 1294 1295 /* Ring a channel doorbell, reporting the first un-filled entry */ 1296 void gsi_channel_doorbell(struct gsi_channel *channel) 1297 { 1298 struct gsi_ring *tre_ring = &channel->tre_ring; 1299 u32 channel_id = gsi_channel_id(channel); 1300 struct gsi *gsi = channel->gsi; 1301 u32 val; 1302 1303 /* Note: index *must* be used modulo the ring count here */ 1304 val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count); 1305 iowrite32(val, gsi->virt + GSI_CH_C_DOORBELL_0_OFFSET(channel_id)); 1306 } 1307 1308 /* Consult hardware, move any newly completed transactions to completed list */ 1309 static void gsi_channel_update(struct gsi_channel *channel) 1310 { 1311 u32 evt_ring_id = channel->evt_ring_id; 1312 struct gsi *gsi = channel->gsi; 1313 struct gsi_evt_ring *evt_ring; 1314 struct gsi_trans *trans; 1315 struct gsi_ring *ring; 1316 u32 offset; 1317 u32 index; 1318 1319 evt_ring = &gsi->evt_ring[evt_ring_id]; 1320 ring = &evt_ring->ring; 1321 1322 /* See if there's anything new to process; if not, we're done. Note 1323 * that index always refers to an entry *within* the event ring. 1324 */ 1325 offset = GSI_EV_CH_E_CNTXT_4_OFFSET(evt_ring_id); 1326 index = gsi_ring_index(ring, ioread32(gsi->virt + offset)); 1327 if (index == ring->index % ring->count) 1328 return; 1329 1330 /* Get the transaction for the latest completed event. Take a 1331 * reference to keep it from completing before we give the events 1332 * for this and previous transactions back to the hardware. 1333 */ 1334 trans = gsi_event_trans(channel, gsi_ring_virt(ring, index - 1)); 1335 refcount_inc(&trans->refcount); 1336 1337 /* For RX channels, update each completed transaction with the number 1338 * of bytes that were actually received. For TX channels, report 1339 * the number of transactions and bytes this completion represents 1340 * up the network stack. 1341 */ 1342 if (channel->toward_ipa) 1343 gsi_channel_tx_update(channel, trans); 1344 else 1345 gsi_evt_ring_rx_update(evt_ring, index); 1346 1347 gsi_trans_move_complete(trans); 1348 1349 /* Tell the hardware we've handled these events */ 1350 gsi_evt_ring_doorbell(channel->gsi, channel->evt_ring_id, index); 1351 1352 gsi_trans_free(trans); 1353 } 1354 1355 /** 1356 * gsi_channel_poll_one() - Return a single completed transaction on a channel 1357 * @channel: Channel to be polled 1358 * 1359 * @Return: Transaction pointer, or null if none are available 1360 * 1361 * This function returns the first entry on a channel's completed transaction 1362 * list. If that list is empty, the hardware is consulted to determine 1363 * whether any new transactions have completed. If so, they're moved to the 1364 * completed list and the new first entry is returned. If there are no more 1365 * completed transactions, a null pointer is returned. 1366 */ 1367 static struct gsi_trans *gsi_channel_poll_one(struct gsi_channel *channel) 1368 { 1369 struct gsi_trans *trans; 1370 1371 /* Get the first transaction from the completed list */ 1372 trans = gsi_channel_trans_complete(channel); 1373 if (!trans) { 1374 /* List is empty; see if there's more to do */ 1375 gsi_channel_update(channel); 1376 trans = gsi_channel_trans_complete(channel); 1377 } 1378 1379 if (trans) 1380 gsi_trans_move_polled(trans); 1381 1382 return trans; 1383 } 1384 1385 /** 1386 * gsi_channel_poll() - NAPI poll function for a channel 1387 * @napi: NAPI structure for the channel 1388 * @budget: Budget supplied by NAPI core 1389 1390 * @Return: Number of items polled (<= budget) 1391 * 1392 * Single transactions completed by hardware are polled until either 1393 * the budget is exhausted, or there are no more. Each transaction 1394 * polled is passed to gsi_trans_complete(), to perform remaining 1395 * completion processing and retire/free the transaction. 1396 */ 1397 static int gsi_channel_poll(struct napi_struct *napi, int budget) 1398 { 1399 struct gsi_channel *channel; 1400 int count = 0; 1401 1402 channel = container_of(napi, struct gsi_channel, napi); 1403 while (count < budget) { 1404 struct gsi_trans *trans; 1405 1406 count++; 1407 trans = gsi_channel_poll_one(channel); 1408 if (!trans) 1409 break; 1410 gsi_trans_complete(trans); 1411 } 1412 1413 if (count < budget) { 1414 napi_complete(&channel->napi); 1415 gsi_irq_ieob_enable(channel->gsi, channel->evt_ring_id); 1416 } 1417 1418 return count; 1419 } 1420 1421 /* The event bitmap represents which event ids are available for allocation. 1422 * Set bits are not available, clear bits can be used. This function 1423 * initializes the map so all events supported by the hardware are available, 1424 * then precludes any reserved events from being allocated. 1425 */ 1426 static u32 gsi_event_bitmap_init(u32 evt_ring_max) 1427 { 1428 u32 event_bitmap = GENMASK(BITS_PER_LONG - 1, evt_ring_max); 1429 1430 event_bitmap |= GENMASK(GSI_MHI_EVENT_ID_END, GSI_MHI_EVENT_ID_START); 1431 1432 return event_bitmap; 1433 } 1434 1435 /* Setup function for event rings */ 1436 static void gsi_evt_ring_setup(struct gsi *gsi) 1437 { 1438 /* Nothing to do */ 1439 } 1440 1441 /* Inverse of gsi_evt_ring_setup() */ 1442 static void gsi_evt_ring_teardown(struct gsi *gsi) 1443 { 1444 /* Nothing to do */ 1445 } 1446 1447 /* Setup function for a single channel */ 1448 static int gsi_channel_setup_one(struct gsi *gsi, u32 channel_id, 1449 bool legacy) 1450 { 1451 struct gsi_channel *channel = &gsi->channel[channel_id]; 1452 u32 evt_ring_id = channel->evt_ring_id; 1453 int ret; 1454 1455 if (!channel->gsi) 1456 return 0; /* Ignore uninitialized channels */ 1457 1458 ret = gsi_evt_ring_alloc_command(gsi, evt_ring_id); 1459 if (ret) 1460 return ret; 1461 1462 gsi_evt_ring_program(gsi, evt_ring_id); 1463 1464 ret = gsi_channel_alloc_command(gsi, channel_id); 1465 if (ret) 1466 goto err_evt_ring_de_alloc; 1467 1468 gsi_channel_program(channel, legacy); 1469 1470 if (channel->toward_ipa) 1471 netif_tx_napi_add(&gsi->dummy_dev, &channel->napi, 1472 gsi_channel_poll, NAPI_POLL_WEIGHT); 1473 else 1474 netif_napi_add(&gsi->dummy_dev, &channel->napi, 1475 gsi_channel_poll, NAPI_POLL_WEIGHT); 1476 1477 return 0; 1478 1479 err_evt_ring_de_alloc: 1480 /* We've done nothing with the event ring yet so don't reset */ 1481 gsi_evt_ring_de_alloc_command(gsi, evt_ring_id); 1482 1483 return ret; 1484 } 1485 1486 /* Inverse of gsi_channel_setup_one() */ 1487 static void gsi_channel_teardown_one(struct gsi *gsi, u32 channel_id) 1488 { 1489 struct gsi_channel *channel = &gsi->channel[channel_id]; 1490 u32 evt_ring_id = channel->evt_ring_id; 1491 1492 if (!channel->gsi) 1493 return; /* Ignore uninitialized channels */ 1494 1495 netif_napi_del(&channel->napi); 1496 1497 gsi_channel_deprogram(channel); 1498 gsi_channel_de_alloc_command(gsi, channel_id); 1499 gsi_evt_ring_reset_command(gsi, evt_ring_id); 1500 gsi_evt_ring_de_alloc_command(gsi, evt_ring_id); 1501 } 1502 1503 static int gsi_generic_command(struct gsi *gsi, u32 channel_id, 1504 enum gsi_generic_cmd_opcode opcode) 1505 { 1506 struct completion *completion = &gsi->completion; 1507 u32 val; 1508 1509 /* First zero the result code field */ 1510 val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); 1511 val &= ~GENERIC_EE_RESULT_FMASK; 1512 iowrite32(val, gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); 1513 1514 /* Now issue the command */ 1515 val = u32_encode_bits(opcode, GENERIC_OPCODE_FMASK); 1516 val |= u32_encode_bits(channel_id, GENERIC_CHID_FMASK); 1517 val |= u32_encode_bits(GSI_EE_MODEM, GENERIC_EE_FMASK); 1518 1519 if (gsi_command(gsi, GSI_GENERIC_CMD_OFFSET, val, completion)) 1520 return 0; /* Success! */ 1521 1522 dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n", 1523 opcode, channel_id); 1524 1525 return -ETIMEDOUT; 1526 } 1527 1528 static int gsi_modem_channel_alloc(struct gsi *gsi, u32 channel_id) 1529 { 1530 return gsi_generic_command(gsi, channel_id, 1531 GSI_GENERIC_ALLOCATE_CHANNEL); 1532 } 1533 1534 static void gsi_modem_channel_halt(struct gsi *gsi, u32 channel_id) 1535 { 1536 int ret; 1537 1538 ret = gsi_generic_command(gsi, channel_id, GSI_GENERIC_HALT_CHANNEL); 1539 if (ret) 1540 dev_err(gsi->dev, "error %d halting modem channel %u\n", 1541 ret, channel_id); 1542 } 1543 1544 /* Setup function for channels */ 1545 static int gsi_channel_setup(struct gsi *gsi, bool legacy) 1546 { 1547 u32 channel_id = 0; 1548 u32 mask; 1549 int ret; 1550 1551 gsi_evt_ring_setup(gsi); 1552 gsi_irq_enable(gsi); 1553 1554 mutex_lock(&gsi->mutex); 1555 1556 do { 1557 ret = gsi_channel_setup_one(gsi, channel_id, legacy); 1558 if (ret) 1559 goto err_unwind; 1560 } while (++channel_id < gsi->channel_count); 1561 1562 /* Make sure no channels were defined that hardware does not support */ 1563 while (channel_id < GSI_CHANNEL_COUNT_MAX) { 1564 struct gsi_channel *channel = &gsi->channel[channel_id++]; 1565 1566 if (!channel->gsi) 1567 continue; /* Ignore uninitialized channels */ 1568 1569 dev_err(gsi->dev, "channel %u not supported by hardware\n", 1570 channel_id - 1); 1571 channel_id = gsi->channel_count; 1572 goto err_unwind; 1573 } 1574 1575 /* Allocate modem channels if necessary */ 1576 mask = gsi->modem_channel_bitmap; 1577 while (mask) { 1578 u32 modem_channel_id = __ffs(mask); 1579 1580 ret = gsi_modem_channel_alloc(gsi, modem_channel_id); 1581 if (ret) 1582 goto err_unwind_modem; 1583 1584 /* Clear bit from mask only after success (for unwind) */ 1585 mask ^= BIT(modem_channel_id); 1586 } 1587 1588 mutex_unlock(&gsi->mutex); 1589 1590 return 0; 1591 1592 err_unwind_modem: 1593 /* Compute which modem channels need to be deallocated */ 1594 mask ^= gsi->modem_channel_bitmap; 1595 while (mask) { 1596 u32 channel_id = __fls(mask); 1597 1598 mask ^= BIT(channel_id); 1599 1600 gsi_modem_channel_halt(gsi, channel_id); 1601 } 1602 1603 err_unwind: 1604 while (channel_id--) 1605 gsi_channel_teardown_one(gsi, channel_id); 1606 1607 mutex_unlock(&gsi->mutex); 1608 1609 gsi_irq_disable(gsi); 1610 gsi_evt_ring_teardown(gsi); 1611 1612 return ret; 1613 } 1614 1615 /* Inverse of gsi_channel_setup() */ 1616 static void gsi_channel_teardown(struct gsi *gsi) 1617 { 1618 u32 mask = gsi->modem_channel_bitmap; 1619 u32 channel_id; 1620 1621 mutex_lock(&gsi->mutex); 1622 1623 while (mask) { 1624 u32 channel_id = __fls(mask); 1625 1626 mask ^= BIT(channel_id); 1627 1628 gsi_modem_channel_halt(gsi, channel_id); 1629 } 1630 1631 channel_id = gsi->channel_count - 1; 1632 do 1633 gsi_channel_teardown_one(gsi, channel_id); 1634 while (channel_id--); 1635 1636 mutex_unlock(&gsi->mutex); 1637 1638 gsi_irq_disable(gsi); 1639 gsi_evt_ring_teardown(gsi); 1640 } 1641 1642 /* Setup function for GSI. GSI firmware must be loaded and initialized */ 1643 int gsi_setup(struct gsi *gsi, bool legacy) 1644 { 1645 u32 val; 1646 1647 /* Here is where we first touch the GSI hardware */ 1648 val = ioread32(gsi->virt + GSI_GSI_STATUS_OFFSET); 1649 if (!(val & ENABLED_FMASK)) { 1650 dev_err(gsi->dev, "GSI has not been enabled\n"); 1651 return -EIO; 1652 } 1653 1654 val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET); 1655 1656 gsi->channel_count = u32_get_bits(val, NUM_CH_PER_EE_FMASK); 1657 if (!gsi->channel_count) { 1658 dev_err(gsi->dev, "GSI reports zero channels supported\n"); 1659 return -EINVAL; 1660 } 1661 if (gsi->channel_count > GSI_CHANNEL_COUNT_MAX) { 1662 dev_warn(gsi->dev, 1663 "limiting to %u channels (hardware supports %u)\n", 1664 GSI_CHANNEL_COUNT_MAX, gsi->channel_count); 1665 gsi->channel_count = GSI_CHANNEL_COUNT_MAX; 1666 } 1667 1668 gsi->evt_ring_count = u32_get_bits(val, NUM_EV_PER_EE_FMASK); 1669 if (!gsi->evt_ring_count) { 1670 dev_err(gsi->dev, "GSI reports zero event rings supported\n"); 1671 return -EINVAL; 1672 } 1673 if (gsi->evt_ring_count > GSI_EVT_RING_COUNT_MAX) { 1674 dev_warn(gsi->dev, 1675 "limiting to %u event rings (hardware supports %u)\n", 1676 GSI_EVT_RING_COUNT_MAX, gsi->evt_ring_count); 1677 gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; 1678 } 1679 1680 /* Initialize the error log */ 1681 iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); 1682 1683 /* Writing 1 indicates IRQ interrupts; 0 would be MSI */ 1684 iowrite32(1, gsi->virt + GSI_CNTXT_INTSET_OFFSET); 1685 1686 return gsi_channel_setup(gsi, legacy); 1687 } 1688 1689 /* Inverse of gsi_setup() */ 1690 void gsi_teardown(struct gsi *gsi) 1691 { 1692 gsi_channel_teardown(gsi); 1693 } 1694 1695 /* Initialize a channel's event ring */ 1696 static int gsi_channel_evt_ring_init(struct gsi_channel *channel) 1697 { 1698 struct gsi *gsi = channel->gsi; 1699 struct gsi_evt_ring *evt_ring; 1700 int ret; 1701 1702 ret = gsi_evt_ring_id_alloc(gsi); 1703 if (ret < 0) 1704 return ret; 1705 channel->evt_ring_id = ret; 1706 1707 evt_ring = &gsi->evt_ring[channel->evt_ring_id]; 1708 evt_ring->channel = channel; 1709 1710 ret = gsi_ring_alloc(gsi, &evt_ring->ring, channel->event_count); 1711 if (!ret) 1712 return 0; /* Success! */ 1713 1714 dev_err(gsi->dev, "error %d allocating channel %u event ring\n", 1715 ret, gsi_channel_id(channel)); 1716 1717 gsi_evt_ring_id_free(gsi, channel->evt_ring_id); 1718 1719 return ret; 1720 } 1721 1722 /* Inverse of gsi_channel_evt_ring_init() */ 1723 static void gsi_channel_evt_ring_exit(struct gsi_channel *channel) 1724 { 1725 u32 evt_ring_id = channel->evt_ring_id; 1726 struct gsi *gsi = channel->gsi; 1727 struct gsi_evt_ring *evt_ring; 1728 1729 evt_ring = &gsi->evt_ring[evt_ring_id]; 1730 gsi_ring_free(gsi, &evt_ring->ring); 1731 gsi_evt_ring_id_free(gsi, evt_ring_id); 1732 } 1733 1734 /* Init function for event rings */ 1735 static void gsi_evt_ring_init(struct gsi *gsi) 1736 { 1737 u32 evt_ring_id = 0; 1738 1739 gsi->event_bitmap = gsi_event_bitmap_init(GSI_EVT_RING_COUNT_MAX); 1740 gsi->event_enable_bitmap = 0; 1741 do 1742 init_completion(&gsi->evt_ring[evt_ring_id].completion); 1743 while (++evt_ring_id < GSI_EVT_RING_COUNT_MAX); 1744 } 1745 1746 /* Inverse of gsi_evt_ring_init() */ 1747 static void gsi_evt_ring_exit(struct gsi *gsi) 1748 { 1749 /* Nothing to do */ 1750 } 1751 1752 static bool gsi_channel_data_valid(struct gsi *gsi, 1753 const struct ipa_gsi_endpoint_data *data) 1754 { 1755 #ifdef IPA_VALIDATION 1756 u32 channel_id = data->channel_id; 1757 struct device *dev = gsi->dev; 1758 1759 /* Make sure channel ids are in the range driver supports */ 1760 if (channel_id >= GSI_CHANNEL_COUNT_MAX) { 1761 dev_err(dev, "bad channel id %u (must be less than %u)\n", 1762 channel_id, GSI_CHANNEL_COUNT_MAX); 1763 return false; 1764 } 1765 1766 if (data->ee_id != GSI_EE_AP && data->ee_id != GSI_EE_MODEM) { 1767 dev_err(dev, "bad EE id %u (AP or modem)\n", data->ee_id); 1768 return false; 1769 } 1770 1771 if (!data->channel.tlv_count || 1772 data->channel.tlv_count > GSI_TLV_MAX) { 1773 dev_err(dev, "channel %u bad tlv_count %u (must be 1..%u)\n", 1774 channel_id, data->channel.tlv_count, GSI_TLV_MAX); 1775 return false; 1776 } 1777 1778 /* We have to allow at least one maximally-sized transaction to 1779 * be outstanding (which would use tlv_count TREs). Given how 1780 * gsi_channel_tre_max() is computed, tre_count has to be almost 1781 * twice the TLV FIFO size to satisfy this requirement. 1782 */ 1783 if (data->channel.tre_count < 2 * data->channel.tlv_count - 1) { 1784 dev_err(dev, "channel %u TLV count %u exceeds TRE count %u\n", 1785 channel_id, data->channel.tlv_count, 1786 data->channel.tre_count); 1787 return false; 1788 } 1789 1790 if (!is_power_of_2(data->channel.tre_count)) { 1791 dev_err(dev, "channel %u bad tre_count %u (not power of 2)\n", 1792 channel_id, data->channel.tre_count); 1793 return false; 1794 } 1795 1796 if (!is_power_of_2(data->channel.event_count)) { 1797 dev_err(dev, "channel %u bad event_count %u (not power of 2)\n", 1798 channel_id, data->channel.event_count); 1799 return false; 1800 } 1801 #endif /* IPA_VALIDATION */ 1802 1803 return true; 1804 } 1805 1806 /* Init function for a single channel */ 1807 static int gsi_channel_init_one(struct gsi *gsi, 1808 const struct ipa_gsi_endpoint_data *data, 1809 bool command, bool prefetch) 1810 { 1811 struct gsi_channel *channel; 1812 u32 tre_count; 1813 int ret; 1814 1815 if (!gsi_channel_data_valid(gsi, data)) 1816 return -EINVAL; 1817 1818 /* Worst case we need an event for every outstanding TRE */ 1819 if (data->channel.tre_count > data->channel.event_count) { 1820 tre_count = data->channel.event_count; 1821 dev_warn(gsi->dev, "channel %u limited to %u TREs\n", 1822 data->channel_id, tre_count); 1823 } else { 1824 tre_count = data->channel.tre_count; 1825 } 1826 1827 channel = &gsi->channel[data->channel_id]; 1828 memset(channel, 0, sizeof(*channel)); 1829 1830 channel->gsi = gsi; 1831 channel->toward_ipa = data->toward_ipa; 1832 channel->command = command; 1833 channel->use_prefetch = command && prefetch; 1834 channel->tlv_count = data->channel.tlv_count; 1835 channel->tre_count = tre_count; 1836 channel->event_count = data->channel.event_count; 1837 init_completion(&channel->completion); 1838 1839 ret = gsi_channel_evt_ring_init(channel); 1840 if (ret) 1841 goto err_clear_gsi; 1842 1843 ret = gsi_ring_alloc(gsi, &channel->tre_ring, data->channel.tre_count); 1844 if (ret) { 1845 dev_err(gsi->dev, "error %d allocating channel %u ring\n", 1846 ret, data->channel_id); 1847 goto err_channel_evt_ring_exit; 1848 } 1849 1850 ret = gsi_channel_trans_init(gsi, data->channel_id); 1851 if (ret) 1852 goto err_ring_free; 1853 1854 if (command) { 1855 u32 tre_max = gsi_channel_tre_max(gsi, data->channel_id); 1856 1857 ret = ipa_cmd_pool_init(channel, tre_max); 1858 } 1859 if (!ret) 1860 return 0; /* Success! */ 1861 1862 gsi_channel_trans_exit(channel); 1863 err_ring_free: 1864 gsi_ring_free(gsi, &channel->tre_ring); 1865 err_channel_evt_ring_exit: 1866 gsi_channel_evt_ring_exit(channel); 1867 err_clear_gsi: 1868 channel->gsi = NULL; /* Mark it not (fully) initialized */ 1869 1870 return ret; 1871 } 1872 1873 /* Inverse of gsi_channel_init_one() */ 1874 static void gsi_channel_exit_one(struct gsi_channel *channel) 1875 { 1876 if (!channel->gsi) 1877 return; /* Ignore uninitialized channels */ 1878 1879 if (channel->command) 1880 ipa_cmd_pool_exit(channel); 1881 gsi_channel_trans_exit(channel); 1882 gsi_ring_free(channel->gsi, &channel->tre_ring); 1883 gsi_channel_evt_ring_exit(channel); 1884 } 1885 1886 /* Init function for channels */ 1887 static int gsi_channel_init(struct gsi *gsi, bool prefetch, u32 count, 1888 const struct ipa_gsi_endpoint_data *data, 1889 bool modem_alloc) 1890 { 1891 int ret = 0; 1892 u32 i; 1893 1894 gsi_evt_ring_init(gsi); 1895 1896 /* The endpoint data array is indexed by endpoint name */ 1897 for (i = 0; i < count; i++) { 1898 bool command = i == IPA_ENDPOINT_AP_COMMAND_TX; 1899 1900 if (ipa_gsi_endpoint_data_empty(&data[i])) 1901 continue; /* Skip over empty slots */ 1902 1903 /* Mark modem channels to be allocated (hardware workaround) */ 1904 if (data[i].ee_id == GSI_EE_MODEM) { 1905 if (modem_alloc) 1906 gsi->modem_channel_bitmap |= 1907 BIT(data[i].channel_id); 1908 continue; 1909 } 1910 1911 ret = gsi_channel_init_one(gsi, &data[i], command, prefetch); 1912 if (ret) 1913 goto err_unwind; 1914 } 1915 1916 return ret; 1917 1918 err_unwind: 1919 while (i--) { 1920 if (ipa_gsi_endpoint_data_empty(&data[i])) 1921 continue; 1922 if (modem_alloc && data[i].ee_id == GSI_EE_MODEM) { 1923 gsi->modem_channel_bitmap &= ~BIT(data[i].channel_id); 1924 continue; 1925 } 1926 gsi_channel_exit_one(&gsi->channel[data->channel_id]); 1927 } 1928 gsi_evt_ring_exit(gsi); 1929 1930 return ret; 1931 } 1932 1933 /* Inverse of gsi_channel_init() */ 1934 static void gsi_channel_exit(struct gsi *gsi) 1935 { 1936 u32 channel_id = GSI_CHANNEL_COUNT_MAX - 1; 1937 1938 do 1939 gsi_channel_exit_one(&gsi->channel[channel_id]); 1940 while (channel_id--); 1941 gsi->modem_channel_bitmap = 0; 1942 1943 gsi_evt_ring_exit(gsi); 1944 } 1945 1946 /* Init function for GSI. GSI hardware does not need to be "ready" */ 1947 int gsi_init(struct gsi *gsi, struct platform_device *pdev, bool prefetch, 1948 u32 count, const struct ipa_gsi_endpoint_data *data, 1949 bool modem_alloc) 1950 { 1951 struct resource *res; 1952 resource_size_t size; 1953 unsigned int irq; 1954 int ret; 1955 1956 gsi_validate_build(); 1957 1958 gsi->dev = &pdev->dev; 1959 1960 /* The GSI layer performs NAPI on all endpoints. NAPI requires a 1961 * network device structure, but the GSI layer does not have one, 1962 * so we must create a dummy network device for this purpose. 1963 */ 1964 init_dummy_netdev(&gsi->dummy_dev); 1965 1966 /* Get the GSI IRQ and request for it to wake the system */ 1967 ret = platform_get_irq_byname(pdev, "gsi"); 1968 if (ret <= 0) { 1969 dev_err(gsi->dev, 1970 "DT error %d getting \"gsi\" IRQ property\n", ret); 1971 return ret ? : -EINVAL; 1972 } 1973 irq = ret; 1974 1975 ret = request_irq(irq, gsi_isr, 0, "gsi", gsi); 1976 if (ret) { 1977 dev_err(gsi->dev, "error %d requesting \"gsi\" IRQ\n", ret); 1978 return ret; 1979 } 1980 gsi->irq = irq; 1981 1982 ret = enable_irq_wake(gsi->irq); 1983 if (ret) 1984 dev_warn(gsi->dev, "error %d enabling gsi wake irq\n", ret); 1985 gsi->irq_wake_enabled = !ret; 1986 1987 /* Get GSI memory range and map it */ 1988 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsi"); 1989 if (!res) { 1990 dev_err(gsi->dev, 1991 "DT error getting \"gsi\" memory property\n"); 1992 ret = -ENODEV; 1993 goto err_disable_irq_wake; 1994 } 1995 1996 size = resource_size(res); 1997 if (res->start > U32_MAX || size > U32_MAX - res->start) { 1998 dev_err(gsi->dev, "DT memory resource \"gsi\" out of range\n"); 1999 ret = -EINVAL; 2000 goto err_disable_irq_wake; 2001 } 2002 2003 gsi->virt = ioremap(res->start, size); 2004 if (!gsi->virt) { 2005 dev_err(gsi->dev, "unable to remap \"gsi\" memory\n"); 2006 ret = -ENOMEM; 2007 goto err_disable_irq_wake; 2008 } 2009 2010 ret = gsi_channel_init(gsi, prefetch, count, data, modem_alloc); 2011 if (ret) 2012 goto err_iounmap; 2013 2014 mutex_init(&gsi->mutex); 2015 init_completion(&gsi->completion); 2016 2017 return 0; 2018 2019 err_iounmap: 2020 iounmap(gsi->virt); 2021 err_disable_irq_wake: 2022 if (gsi->irq_wake_enabled) 2023 (void)disable_irq_wake(gsi->irq); 2024 free_irq(gsi->irq, gsi); 2025 2026 return ret; 2027 } 2028 2029 /* Inverse of gsi_init() */ 2030 void gsi_exit(struct gsi *gsi) 2031 { 2032 mutex_destroy(&gsi->mutex); 2033 gsi_channel_exit(gsi); 2034 if (gsi->irq_wake_enabled) 2035 (void)disable_irq_wake(gsi->irq); 2036 free_irq(gsi->irq, gsi); 2037 iounmap(gsi->virt); 2038 } 2039 2040 /* The maximum number of outstanding TREs on a channel. This limits 2041 * a channel's maximum number of transactions outstanding (worst case 2042 * is one TRE per transaction). 2043 * 2044 * The absolute limit is the number of TREs in the channel's TRE ring, 2045 * and in theory we should be able use all of them. But in practice, 2046 * doing that led to the hardware reporting exhaustion of event ring 2047 * slots for writing completion information. So the hardware limit 2048 * would be (tre_count - 1). 2049 * 2050 * We reduce it a bit further though. Transaction resource pools are 2051 * sized to be a little larger than this maximum, to allow resource 2052 * allocations to always be contiguous. The number of entries in a 2053 * TRE ring buffer is a power of 2, and the extra resources in a pool 2054 * tends to nearly double the memory allocated for it. Reducing the 2055 * maximum number of outstanding TREs allows the number of entries in 2056 * a pool to avoid crossing that power-of-2 boundary, and this can 2057 * substantially reduce pool memory requirements. The number we 2058 * reduce it by matches the number added in gsi_trans_pool_init(). 2059 */ 2060 u32 gsi_channel_tre_max(struct gsi *gsi, u32 channel_id) 2061 { 2062 struct gsi_channel *channel = &gsi->channel[channel_id]; 2063 2064 /* Hardware limit is channel->tre_count - 1 */ 2065 return channel->tre_count - (channel->tlv_count - 1); 2066 } 2067 2068 /* Returns the maximum number of TREs in a single transaction for a channel */ 2069 u32 gsi_channel_trans_tre_max(struct gsi *gsi, u32 channel_id) 2070 { 2071 struct gsi_channel *channel = &gsi->channel[channel_id]; 2072 2073 return channel->tlv_count; 2074 } 2075