1*cb7550b4SAlex Elder // SPDX-License-Identifier: GPL-2.0 2*cb7550b4SAlex Elder 3*cb7550b4SAlex Elder /* Copyright (C) 2023 Linaro Ltd. */ 4*cb7550b4SAlex Elder 5*cb7550b4SAlex Elder #include <linux/log2.h> 6*cb7550b4SAlex Elder 7*cb7550b4SAlex Elder #include "../gsi.h" 8*cb7550b4SAlex Elder #include "../ipa_data.h" 9*cb7550b4SAlex Elder #include "../ipa_endpoint.h" 10*cb7550b4SAlex Elder #include "../ipa_mem.h" 11*cb7550b4SAlex Elder 12*cb7550b4SAlex Elder /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */ 13*cb7550b4SAlex Elder enum ipa_resource_type { 14*cb7550b4SAlex Elder /* Source resource types; first must have value 0 */ 15*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 16*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 17*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 18*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 19*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 20*cb7550b4SAlex Elder 21*cb7550b4SAlex Elder /* Destination resource types; first must have value 0 */ 22*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 23*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_DPS_DMARS, 24*cb7550b4SAlex Elder IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS, 25*cb7550b4SAlex Elder }; 26*cb7550b4SAlex Elder 27*cb7550b4SAlex Elder /* Resource groups used for an SoC having IPA v5.0 */ 28*cb7550b4SAlex Elder enum ipa_rsrc_group_id { 29*cb7550b4SAlex Elder /* Source resource group identifiers */ 30*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UL = 0, 31*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_DL, 32*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_2, 33*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_UNUSED_3, 34*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_URLLC, 35*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_U_RX_QC, 36*cb7550b4SAlex Elder IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 37*cb7550b4SAlex Elder 38*cb7550b4SAlex Elder /* Destination resource group identifiers */ 39*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_UL = 0, 40*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DL, 41*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DMA, 42*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_QDSS, 43*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_CV2X, 44*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_UC, 45*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_DRB_IP, 46*cb7550b4SAlex Elder IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 47*cb7550b4SAlex Elder }; 48*cb7550b4SAlex Elder 49*cb7550b4SAlex Elder /* QSB configuration data for an SoC having IPA v5.0 */ 50*cb7550b4SAlex Elder static const struct ipa_qsb_data ipa_qsb_data[] = { 51*cb7550b4SAlex Elder [IPA_QSB_MASTER_DDR] = { 52*cb7550b4SAlex Elder .max_writes = 0, 53*cb7550b4SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 54*cb7550b4SAlex Elder .max_reads_beats = 0, 55*cb7550b4SAlex Elder }, 56*cb7550b4SAlex Elder [IPA_QSB_MASTER_PCIE] = { 57*cb7550b4SAlex Elder .max_writes = 0, 58*cb7550b4SAlex Elder .max_reads = 0, /* no limit (hardware max) */ 59*cb7550b4SAlex Elder .max_reads_beats = 0, 60*cb7550b4SAlex Elder }, 61*cb7550b4SAlex Elder }; 62*cb7550b4SAlex Elder 63*cb7550b4SAlex Elder /* Endpoint configuration data for an SoC having IPA v5.0 */ 64*cb7550b4SAlex Elder static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 65*cb7550b4SAlex Elder [IPA_ENDPOINT_AP_COMMAND_TX] = { 66*cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 67*cb7550b4SAlex Elder .channel_id = 12, 68*cb7550b4SAlex Elder .endpoint_id = 14, 69*cb7550b4SAlex Elder .toward_ipa = true, 70*cb7550b4SAlex Elder .channel = { 71*cb7550b4SAlex Elder .tre_count = 256, 72*cb7550b4SAlex Elder .event_count = 256, 73*cb7550b4SAlex Elder .tlv_count = 20, 74*cb7550b4SAlex Elder }, 75*cb7550b4SAlex Elder .endpoint = { 76*cb7550b4SAlex Elder .config = { 77*cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL, 78*cb7550b4SAlex Elder .dma_mode = true, 79*cb7550b4SAlex Elder .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 80*cb7550b4SAlex Elder .tx = { 81*cb7550b4SAlex Elder .seq_type = IPA_SEQ_DMA, 82*cb7550b4SAlex Elder }, 83*cb7550b4SAlex Elder }, 84*cb7550b4SAlex Elder }, 85*cb7550b4SAlex Elder }, 86*cb7550b4SAlex Elder [IPA_ENDPOINT_AP_LAN_RX] = { 87*cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 88*cb7550b4SAlex Elder .channel_id = 13, 89*cb7550b4SAlex Elder .endpoint_id = 16, 90*cb7550b4SAlex Elder .toward_ipa = false, 91*cb7550b4SAlex Elder .channel = { 92*cb7550b4SAlex Elder .tre_count = 256, 93*cb7550b4SAlex Elder .event_count = 256, 94*cb7550b4SAlex Elder .tlv_count = 9, 95*cb7550b4SAlex Elder }, 96*cb7550b4SAlex Elder .endpoint = { 97*cb7550b4SAlex Elder .config = { 98*cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_UL, 99*cb7550b4SAlex Elder .aggregation = true, 100*cb7550b4SAlex Elder .status_enable = true, 101*cb7550b4SAlex Elder .rx = { 102*cb7550b4SAlex Elder .buffer_size = 8192, 103*cb7550b4SAlex Elder .pad_align = ilog2(sizeof(u32)), 104*cb7550b4SAlex Elder .aggr_time_limit = 500, 105*cb7550b4SAlex Elder }, 106*cb7550b4SAlex Elder }, 107*cb7550b4SAlex Elder }, 108*cb7550b4SAlex Elder }, 109*cb7550b4SAlex Elder [IPA_ENDPOINT_AP_MODEM_TX] = { 110*cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 111*cb7550b4SAlex Elder .channel_id = 11, 112*cb7550b4SAlex Elder .endpoint_id = 2, 113*cb7550b4SAlex Elder .toward_ipa = true, 114*cb7550b4SAlex Elder .channel = { 115*cb7550b4SAlex Elder .tre_count = 512, 116*cb7550b4SAlex Elder .event_count = 512, 117*cb7550b4SAlex Elder .tlv_count = 25, 118*cb7550b4SAlex Elder }, 119*cb7550b4SAlex Elder .endpoint = { 120*cb7550b4SAlex Elder .filter_support = true, 121*cb7550b4SAlex Elder .config = { 122*cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_SRC_UL, 123*cb7550b4SAlex Elder .checksum = true, 124*cb7550b4SAlex Elder .qmap = true, 125*cb7550b4SAlex Elder .status_enable = true, 126*cb7550b4SAlex Elder .tx = { 127*cb7550b4SAlex Elder .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 128*cb7550b4SAlex Elder .status_endpoint = 129*cb7550b4SAlex Elder IPA_ENDPOINT_MODEM_AP_RX, 130*cb7550b4SAlex Elder }, 131*cb7550b4SAlex Elder }, 132*cb7550b4SAlex Elder }, 133*cb7550b4SAlex Elder }, 134*cb7550b4SAlex Elder [IPA_ENDPOINT_AP_MODEM_RX] = { 135*cb7550b4SAlex Elder .ee_id = GSI_EE_AP, 136*cb7550b4SAlex Elder .channel_id = 1, 137*cb7550b4SAlex Elder .endpoint_id = 23, 138*cb7550b4SAlex Elder .toward_ipa = false, 139*cb7550b4SAlex Elder .channel = { 140*cb7550b4SAlex Elder .tre_count = 256, 141*cb7550b4SAlex Elder .event_count = 256, 142*cb7550b4SAlex Elder .tlv_count = 9, 143*cb7550b4SAlex Elder }, 144*cb7550b4SAlex Elder .endpoint = { 145*cb7550b4SAlex Elder .config = { 146*cb7550b4SAlex Elder .resource_group = IPA_RSRC_GROUP_DST_DL, 147*cb7550b4SAlex Elder .checksum = true, 148*cb7550b4SAlex Elder .qmap = true, 149*cb7550b4SAlex Elder .aggregation = true, 150*cb7550b4SAlex Elder .rx = { 151*cb7550b4SAlex Elder .buffer_size = 8192, 152*cb7550b4SAlex Elder .aggr_time_limit = 500, 153*cb7550b4SAlex Elder .aggr_close_eof = true, 154*cb7550b4SAlex Elder }, 155*cb7550b4SAlex Elder }, 156*cb7550b4SAlex Elder }, 157*cb7550b4SAlex Elder }, 158*cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_AP_TX] = { 159*cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 160*cb7550b4SAlex Elder .channel_id = 0, 161*cb7550b4SAlex Elder .endpoint_id = 12, 162*cb7550b4SAlex Elder .toward_ipa = true, 163*cb7550b4SAlex Elder .endpoint = { 164*cb7550b4SAlex Elder .filter_support = true, 165*cb7550b4SAlex Elder }, 166*cb7550b4SAlex Elder }, 167*cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_AP_RX] = { 168*cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 169*cb7550b4SAlex Elder .channel_id = 7, 170*cb7550b4SAlex Elder .endpoint_id = 21, 171*cb7550b4SAlex Elder .toward_ipa = false, 172*cb7550b4SAlex Elder }, 173*cb7550b4SAlex Elder [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 174*cb7550b4SAlex Elder .ee_id = GSI_EE_MODEM, 175*cb7550b4SAlex Elder .channel_id = 2, 176*cb7550b4SAlex Elder .endpoint_id = 15, 177*cb7550b4SAlex Elder .toward_ipa = true, 178*cb7550b4SAlex Elder .endpoint = { 179*cb7550b4SAlex Elder .filter_support = true, 180*cb7550b4SAlex Elder }, 181*cb7550b4SAlex Elder }, 182*cb7550b4SAlex Elder }; 183*cb7550b4SAlex Elder 184*cb7550b4SAlex Elder /* Source resource configuration data for an SoC having IPA v5.0 */ 185*cb7550b4SAlex Elder static const struct ipa_resource ipa_resource_src[] = { 186*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 187*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 188*cb7550b4SAlex Elder .min = 3, .max = 9, 189*cb7550b4SAlex Elder }, 190*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 191*cb7550b4SAlex Elder .min = 4, .max = 10, 192*cb7550b4SAlex Elder }, 193*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 194*cb7550b4SAlex Elder .min = 1, .max = 63, 195*cb7550b4SAlex Elder }, 196*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 197*cb7550b4SAlex Elder .min = 0, .max = 63, 198*cb7550b4SAlex Elder }, 199*cb7550b4SAlex Elder }, 200*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 201*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 202*cb7550b4SAlex Elder .min = 9, .max = 9, 203*cb7550b4SAlex Elder }, 204*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 205*cb7550b4SAlex Elder .min = 12, .max = 12, 206*cb7550b4SAlex Elder }, 207*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 208*cb7550b4SAlex Elder .min = 10, .max = 10, 209*cb7550b4SAlex Elder }, 210*cb7550b4SAlex Elder }, 211*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 212*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 213*cb7550b4SAlex Elder .min = 9, .max = 9, 214*cb7550b4SAlex Elder }, 215*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 216*cb7550b4SAlex Elder .min = 24, .max = 24, 217*cb7550b4SAlex Elder }, 218*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 219*cb7550b4SAlex Elder .min = 20, .max = 20, 220*cb7550b4SAlex Elder }, 221*cb7550b4SAlex Elder }, 222*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 223*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 224*cb7550b4SAlex Elder .min = 0, .max = 63, 225*cb7550b4SAlex Elder }, 226*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 227*cb7550b4SAlex Elder .min = 0, .max = 63, 228*cb7550b4SAlex Elder }, 229*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 230*cb7550b4SAlex Elder .min = 1, .max = 63, 231*cb7550b4SAlex Elder }, 232*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 233*cb7550b4SAlex Elder .min = 0, .max = 63, 234*cb7550b4SAlex Elder }, 235*cb7550b4SAlex Elder }, 236*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 237*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_UL] = { 238*cb7550b4SAlex Elder .min = 22, .max = 22, 239*cb7550b4SAlex Elder }, 240*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_DL] = { 241*cb7550b4SAlex Elder .min = 16, .max = 16, 242*cb7550b4SAlex Elder }, 243*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 244*cb7550b4SAlex Elder .min = 16, .max = 16, 245*cb7550b4SAlex Elder }, 246*cb7550b4SAlex Elder }, 247*cb7550b4SAlex Elder }; 248*cb7550b4SAlex Elder 249*cb7550b4SAlex Elder /* Destination resource configuration data for an SoC having IPA v5.0 */ 250*cb7550b4SAlex Elder static const struct ipa_resource ipa_resource_dst[] = { 251*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 252*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 253*cb7550b4SAlex Elder .min = 6, .max = 6, 254*cb7550b4SAlex Elder }, 255*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 256*cb7550b4SAlex Elder .min = 5, .max = 5, 257*cb7550b4SAlex Elder }, 258*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { 259*cb7550b4SAlex Elder .min = 39, .max = 39, 260*cb7550b4SAlex Elder }, 261*cb7550b4SAlex Elder }, 262*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 263*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 264*cb7550b4SAlex Elder .min = 0, .max = 3, 265*cb7550b4SAlex Elder }, 266*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 267*cb7550b4SAlex Elder .min = 0, .max = 3, 268*cb7550b4SAlex Elder }, 269*cb7550b4SAlex Elder }, 270*cb7550b4SAlex Elder [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = { 271*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_UL] = { 272*cb7550b4SAlex Elder .min = 0, .max = 63, 273*cb7550b4SAlex Elder }, 274*cb7550b4SAlex Elder .limits[IPA_RSRC_GROUP_DST_DL] = { 275*cb7550b4SAlex Elder .min = 0, .max = 63, 276*cb7550b4SAlex Elder }, 277*cb7550b4SAlex Elder }, 278*cb7550b4SAlex Elder }; 279*cb7550b4SAlex Elder 280*cb7550b4SAlex Elder /* Resource configuration data for an SoC having IPA v5.0 */ 281*cb7550b4SAlex Elder static const struct ipa_resource_data ipa_resource_data = { 282*cb7550b4SAlex Elder .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 283*cb7550b4SAlex Elder .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 284*cb7550b4SAlex Elder .resource_src_count = ARRAY_SIZE(ipa_resource_src), 285*cb7550b4SAlex Elder .resource_src = ipa_resource_src, 286*cb7550b4SAlex Elder .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 287*cb7550b4SAlex Elder .resource_dst = ipa_resource_dst, 288*cb7550b4SAlex Elder }; 289*cb7550b4SAlex Elder 290*cb7550b4SAlex Elder /* IPA-resident memory region data for an SoC having IPA v5.0 */ 291*cb7550b4SAlex Elder static const struct ipa_mem ipa_mem_local_data[] = { 292*cb7550b4SAlex Elder { 293*cb7550b4SAlex Elder .id = IPA_MEM_UC_EVENT_RING, 294*cb7550b4SAlex Elder .offset = 0x0000, 295*cb7550b4SAlex Elder .size = 0x1000, 296*cb7550b4SAlex Elder .canary_count = 0, 297*cb7550b4SAlex Elder }, 298*cb7550b4SAlex Elder { 299*cb7550b4SAlex Elder .id = IPA_MEM_UC_SHARED, 300*cb7550b4SAlex Elder .offset = 0x1000, 301*cb7550b4SAlex Elder .size = 0x0080, 302*cb7550b4SAlex Elder .canary_count = 0, 303*cb7550b4SAlex Elder }, 304*cb7550b4SAlex Elder { 305*cb7550b4SAlex Elder .id = IPA_MEM_UC_INFO, 306*cb7550b4SAlex Elder .offset = 0x1080, 307*cb7550b4SAlex Elder .size = 0x0200, 308*cb7550b4SAlex Elder .canary_count = 0, 309*cb7550b4SAlex Elder }, 310*cb7550b4SAlex Elder { 311*cb7550b4SAlex Elder .id = IPA_MEM_V4_FILTER_HASHED, 312*cb7550b4SAlex Elder .offset = 0x1288, 313*cb7550b4SAlex Elder .size = 0x0078, 314*cb7550b4SAlex Elder .canary_count = 2, 315*cb7550b4SAlex Elder }, 316*cb7550b4SAlex Elder { 317*cb7550b4SAlex Elder .id = IPA_MEM_V4_FILTER, 318*cb7550b4SAlex Elder .offset = 0x1308, 319*cb7550b4SAlex Elder .size = 0x0078, 320*cb7550b4SAlex Elder .canary_count = 2, 321*cb7550b4SAlex Elder }, 322*cb7550b4SAlex Elder { 323*cb7550b4SAlex Elder .id = IPA_MEM_V6_FILTER_HASHED, 324*cb7550b4SAlex Elder .offset = 0x1388, 325*cb7550b4SAlex Elder .size = 0x0078, 326*cb7550b4SAlex Elder .canary_count = 2, 327*cb7550b4SAlex Elder }, 328*cb7550b4SAlex Elder { 329*cb7550b4SAlex Elder .id = IPA_MEM_V6_FILTER, 330*cb7550b4SAlex Elder .offset = 0x1408, 331*cb7550b4SAlex Elder .size = 0x0078, 332*cb7550b4SAlex Elder .canary_count = 2, 333*cb7550b4SAlex Elder }, 334*cb7550b4SAlex Elder { 335*cb7550b4SAlex Elder .id = IPA_MEM_V4_ROUTE_HASHED, 336*cb7550b4SAlex Elder .offset = 0x1488, 337*cb7550b4SAlex Elder .size = 0x0098, 338*cb7550b4SAlex Elder .canary_count = 2, 339*cb7550b4SAlex Elder }, 340*cb7550b4SAlex Elder { 341*cb7550b4SAlex Elder .id = IPA_MEM_V4_ROUTE, 342*cb7550b4SAlex Elder .offset = 0x1528, 343*cb7550b4SAlex Elder .size = 0x0098, 344*cb7550b4SAlex Elder .canary_count = 2, 345*cb7550b4SAlex Elder }, 346*cb7550b4SAlex Elder { 347*cb7550b4SAlex Elder .id = IPA_MEM_V6_ROUTE_HASHED, 348*cb7550b4SAlex Elder .offset = 0x15c8, 349*cb7550b4SAlex Elder .size = 0x0098, 350*cb7550b4SAlex Elder .canary_count = 2, 351*cb7550b4SAlex Elder }, 352*cb7550b4SAlex Elder { 353*cb7550b4SAlex Elder .id = IPA_MEM_V6_ROUTE, 354*cb7550b4SAlex Elder .offset = 0x1668, 355*cb7550b4SAlex Elder .size = 0x0098, 356*cb7550b4SAlex Elder .canary_count = 2, 357*cb7550b4SAlex Elder }, 358*cb7550b4SAlex Elder { 359*cb7550b4SAlex Elder .id = IPA_MEM_MODEM_HEADER, 360*cb7550b4SAlex Elder .offset = 0x1708, 361*cb7550b4SAlex Elder .size = 0x0240, 362*cb7550b4SAlex Elder .canary_count = 2, 363*cb7550b4SAlex Elder }, 364*cb7550b4SAlex Elder { 365*cb7550b4SAlex Elder .id = IPA_MEM_AP_HEADER, 366*cb7550b4SAlex Elder .offset = 0x1948, 367*cb7550b4SAlex Elder .size = 0x01e0, 368*cb7550b4SAlex Elder .canary_count = 0, 369*cb7550b4SAlex Elder }, 370*cb7550b4SAlex Elder { 371*cb7550b4SAlex Elder .id = IPA_MEM_MODEM_PROC_CTX, 372*cb7550b4SAlex Elder .offset = 0x1b40, 373*cb7550b4SAlex Elder .size = 0x0b20, 374*cb7550b4SAlex Elder .canary_count = 2, 375*cb7550b4SAlex Elder }, 376*cb7550b4SAlex Elder { 377*cb7550b4SAlex Elder .id = IPA_MEM_AP_PROC_CTX, 378*cb7550b4SAlex Elder .offset = 0x2660, 379*cb7550b4SAlex Elder .size = 0x0200, 380*cb7550b4SAlex Elder .canary_count = 0, 381*cb7550b4SAlex Elder }, 382*cb7550b4SAlex Elder { 383*cb7550b4SAlex Elder .id = IPA_MEM_STATS_QUOTA_MODEM, 384*cb7550b4SAlex Elder .offset = 0x2868, 385*cb7550b4SAlex Elder .size = 0x0060, 386*cb7550b4SAlex Elder .canary_count = 2, 387*cb7550b4SAlex Elder }, 388*cb7550b4SAlex Elder { 389*cb7550b4SAlex Elder .id = IPA_MEM_STATS_QUOTA_AP, 390*cb7550b4SAlex Elder .offset = 0x28c8, 391*cb7550b4SAlex Elder .size = 0x0048, 392*cb7550b4SAlex Elder .canary_count = 0, 393*cb7550b4SAlex Elder }, 394*cb7550b4SAlex Elder { 395*cb7550b4SAlex Elder .id = IPA_MEM_AP_V4_FILTER, 396*cb7550b4SAlex Elder .offset = 0x2918, 397*cb7550b4SAlex Elder .size = 0x0118, 398*cb7550b4SAlex Elder .canary_count = 2, 399*cb7550b4SAlex Elder }, 400*cb7550b4SAlex Elder { 401*cb7550b4SAlex Elder .id = IPA_MEM_AP_V6_FILTER, 402*cb7550b4SAlex Elder .offset = 0x2aa0, 403*cb7550b4SAlex Elder .size = 0x0228, 404*cb7550b4SAlex Elder .canary_count = 0, 405*cb7550b4SAlex Elder }, 406*cb7550b4SAlex Elder { 407*cb7550b4SAlex Elder .id = IPA_MEM_STATS_FILTER_ROUTE, 408*cb7550b4SAlex Elder .offset = 0x2cd0, 409*cb7550b4SAlex Elder .size = 0x0ba0, 410*cb7550b4SAlex Elder .canary_count = 2, 411*cb7550b4SAlex Elder }, 412*cb7550b4SAlex Elder { 413*cb7550b4SAlex Elder .id = IPA_MEM_STATS_DROP, 414*cb7550b4SAlex Elder .offset = 0x3870, 415*cb7550b4SAlex Elder .size = 0x0020, 416*cb7550b4SAlex Elder .canary_count = 0, 417*cb7550b4SAlex Elder }, 418*cb7550b4SAlex Elder { 419*cb7550b4SAlex Elder .id = IPA_MEM_MODEM, 420*cb7550b4SAlex Elder .offset = 0x3898, 421*cb7550b4SAlex Elder .size = 0x0d48, 422*cb7550b4SAlex Elder .canary_count = 2, 423*cb7550b4SAlex Elder }, 424*cb7550b4SAlex Elder { 425*cb7550b4SAlex Elder .id = IPA_MEM_NAT_TABLE, 426*cb7550b4SAlex Elder .offset = 0x45e0, 427*cb7550b4SAlex Elder .size = 0x0900, 428*cb7550b4SAlex Elder .canary_count = 0, 429*cb7550b4SAlex Elder }, 430*cb7550b4SAlex Elder { 431*cb7550b4SAlex Elder .id = IPA_MEM_PDN_CONFIG, 432*cb7550b4SAlex Elder .offset = 0x4ee8, 433*cb7550b4SAlex Elder .size = 0x0100, 434*cb7550b4SAlex Elder .canary_count = 2, 435*cb7550b4SAlex Elder }, 436*cb7550b4SAlex Elder }; 437*cb7550b4SAlex Elder 438*cb7550b4SAlex Elder /* Memory configuration data for an SoC having IPA v5.0 */ 439*cb7550b4SAlex Elder static const struct ipa_mem_data ipa_mem_data = { 440*cb7550b4SAlex Elder .local_count = ARRAY_SIZE(ipa_mem_local_data), 441*cb7550b4SAlex Elder .local = ipa_mem_local_data, 442*cb7550b4SAlex Elder .imem_addr = 0x14688000, 443*cb7550b4SAlex Elder .imem_size = 0x00003000, 444*cb7550b4SAlex Elder .smem_id = 497, 445*cb7550b4SAlex Elder .smem_size = 0x00009000, 446*cb7550b4SAlex Elder }; 447*cb7550b4SAlex Elder 448*cb7550b4SAlex Elder /* Interconnect rates are in 1000 byte/second units */ 449*cb7550b4SAlex Elder static const struct ipa_interconnect_data ipa_interconnect_data[] = { 450*cb7550b4SAlex Elder { 451*cb7550b4SAlex Elder .name = "memory", 452*cb7550b4SAlex Elder .peak_bandwidth = 1900000, /* 1.9 GBps */ 453*cb7550b4SAlex Elder .average_bandwidth = 600000, /* 600 MBps */ 454*cb7550b4SAlex Elder }, 455*cb7550b4SAlex Elder /* Average rate is unused for the next interconnect */ 456*cb7550b4SAlex Elder { 457*cb7550b4SAlex Elder .name = "config", 458*cb7550b4SAlex Elder .peak_bandwidth = 76800, /* 76.8 MBps */ 459*cb7550b4SAlex Elder .average_bandwidth = 0, /* unused */ 460*cb7550b4SAlex Elder }, 461*cb7550b4SAlex Elder }; 462*cb7550b4SAlex Elder 463*cb7550b4SAlex Elder /* Clock and interconnect configuration data for an SoC having IPA v5.0 */ 464*cb7550b4SAlex Elder static const struct ipa_power_data ipa_power_data = { 465*cb7550b4SAlex Elder .core_clock_rate = 120 * 1000 * 1000, /* Hz */ 466*cb7550b4SAlex Elder .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 467*cb7550b4SAlex Elder .interconnect_data = ipa_interconnect_data, 468*cb7550b4SAlex Elder }; 469*cb7550b4SAlex Elder 470*cb7550b4SAlex Elder /* Configuration data for an SoC having IPA v5.0. */ 471*cb7550b4SAlex Elder const struct ipa_data ipa_data_v5_0 = { 472*cb7550b4SAlex Elder .version = IPA_VERSION_5_0, 473*cb7550b4SAlex Elder .qsb_count = ARRAY_SIZE(ipa_qsb_data), 474*cb7550b4SAlex Elder .qsb_data = ipa_qsb_data, 475*cb7550b4SAlex Elder .modem_route_count = 11, 476*cb7550b4SAlex Elder .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 477*cb7550b4SAlex Elder .endpoint_data = ipa_gsi_endpoint_data, 478*cb7550b4SAlex Elder .resource_data = &ipa_resource_data, 479*cb7550b4SAlex Elder .mem_data = &ipa_mem_data, 480*cb7550b4SAlex Elder .power_data = &ipa_power_data, 481*cb7550b4SAlex Elder }; 482