1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2019-2021 Linaro Ltd. */
4 
5 #include <linux/log2.h>
6 
7 #include "gsi.h"
8 #include "ipa_data.h"
9 #include "ipa_endpoint.h"
10 #include "ipa_mem.h"
11 
12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */
13 enum ipa_resource_type {
14 	/* Source resource types; first must have value 0 */
15 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
16 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20 
21 	/* Destination resource types; first must have value 0 */
22 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
23 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24 };
25 
26 /* Resource groups used for an SoC having IPA v4.2 */
27 enum ipa_rsrc_group_id {
28 	/* Source resource group identifiers */
29 	IPA_RSRC_GROUP_SRC_UL_DL	= 0,
30 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
31 
32 	/* Destination resource group identifiers */
33 	IPA_RSRC_GROUP_DST_UL_DL_DPL	= 0,
34 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
35 };
36 
37 /* QSB configuration data for an SoC having IPA v4.2 */
38 static const struct ipa_qsb_data ipa_qsb_data[] = {
39 	[IPA_QSB_MASTER_DDR] = {
40 		.max_writes	= 8,
41 		.max_reads	= 12,
42 		/* no outstanding read byte (beat) limit */
43 	},
44 };
45 
46 /* Endpoint configuration data for an SoC having IPA v4.2 */
47 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
48 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
49 		.ee_id		= GSI_EE_AP,
50 		.channel_id	= 1,
51 		.endpoint_id	= 6,
52 		.toward_ipa	= true,
53 		.channel = {
54 			.tre_count	= 256,
55 			.event_count	= 256,
56 			.tlv_count	= 20,
57 		},
58 		.endpoint = {
59 			.config = {
60 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
61 				.dma_mode	= true,
62 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
63 				.tx = {
64 					.seq_type = IPA_SEQ_DMA,
65 				},
66 			},
67 		},
68 	},
69 	[IPA_ENDPOINT_AP_LAN_RX] = {
70 		.ee_id		= GSI_EE_AP,
71 		.channel_id	= 2,
72 		.endpoint_id	= 8,
73 		.toward_ipa	= false,
74 		.channel = {
75 			.tre_count	= 256,
76 			.event_count	= 256,
77 			.tlv_count	= 6,
78 		},
79 		.endpoint = {
80 			.config = {
81 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
82 				.aggregation	= true,
83 				.status_enable	= true,
84 				.rx = {
85 					.buffer_size	= 8192,
86 					.pad_align	= ilog2(sizeof(u32)),
87 					.aggr_time_limit = 500,
88 				},
89 			},
90 		},
91 	},
92 	[IPA_ENDPOINT_AP_MODEM_TX] = {
93 		.ee_id		= GSI_EE_AP,
94 		.channel_id	= 0,
95 		.endpoint_id	= 1,
96 		.toward_ipa	= true,
97 		.channel = {
98 			.tre_count	= 512,
99 			.event_count	= 512,
100 			.tlv_count	= 8,
101 		},
102 		.endpoint = {
103 			.filter_support	= true,
104 			.config = {
105 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
106 				.checksum	= true,
107 				.qmap		= true,
108 				.status_enable	= true,
109 				.tx = {
110 					.seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
111 					.seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
112 					.status_endpoint =
113 						IPA_ENDPOINT_MODEM_AP_RX,
114 				},
115 			},
116 		},
117 	},
118 	[IPA_ENDPOINT_AP_MODEM_RX] = {
119 		.ee_id		= GSI_EE_AP,
120 		.channel_id	= 3,
121 		.endpoint_id	= 9,
122 		.toward_ipa	= false,
123 		.channel = {
124 			.tre_count	= 256,
125 			.event_count	= 256,
126 			.tlv_count	= 6,
127 		},
128 		.endpoint = {
129 			.config = {
130 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
131 				.checksum	= true,
132 				.qmap		= true,
133 				.aggregation	= true,
134 				.rx = {
135 					.buffer_size	= 8192,
136 					.aggr_time_limit = 500,
137 					.aggr_close_eof	= true,
138 				},
139 			},
140 		},
141 	},
142 	[IPA_ENDPOINT_MODEM_COMMAND_TX] = {
143 		.ee_id		= GSI_EE_MODEM,
144 		.channel_id	= 1,
145 		.endpoint_id	= 5,
146 		.toward_ipa	= true,
147 	},
148 	[IPA_ENDPOINT_MODEM_LAN_RX] = {
149 		.ee_id		= GSI_EE_MODEM,
150 		.channel_id	= 3,
151 		.endpoint_id	= 11,
152 		.toward_ipa	= false,
153 	},
154 	[IPA_ENDPOINT_MODEM_AP_TX] = {
155 		.ee_id		= GSI_EE_MODEM,
156 		.channel_id	= 0,
157 		.endpoint_id	= 4,
158 		.toward_ipa	= true,
159 		.endpoint = {
160 			.filter_support	= true,
161 		},
162 	},
163 	[IPA_ENDPOINT_MODEM_AP_RX] = {
164 		.ee_id		= GSI_EE_MODEM,
165 		.channel_id	= 2,
166 		.endpoint_id	= 10,
167 		.toward_ipa	= false,
168 	},
169 };
170 
171 /* Source resource configuration data for an SoC having IPA v4.2 */
172 static const struct ipa_resource ipa_resource_src[] = {
173 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
174 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
175 			.min = 3,	.max = 63,
176 		},
177 	},
178 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
179 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
180 			.min = 3,	.max = 3,
181 		},
182 	},
183 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
184 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
185 			.min = 10,	.max = 10,
186 		},
187 	},
188 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
189 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
190 			.min = 1,	.max = 1,
191 		},
192 	},
193 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
194 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
195 			.min = 5,	.max = 5,
196 		},
197 	},
198 };
199 
200 /* Destination resource configuration data for an SoC having IPA v4.2 */
201 static const struct ipa_resource ipa_resource_dst[] = {
202 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
203 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
204 			.min = 3,	.max = 3,
205 		},
206 	},
207 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
208 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
209 			.min = 1,	.max = 63,
210 		},
211 	},
212 };
213 
214 /* Resource configuration data for an SoC having IPA v4.2 */
215 static const struct ipa_resource_data ipa_resource_data = {
216 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
217 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
218 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
219 	.resource_src		= ipa_resource_src,
220 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
221 	.resource_dst		= ipa_resource_dst,
222 };
223 
224 /* IPA-resident memory region data for an SoC having IPA v4.2 */
225 static const struct ipa_mem ipa_mem_local_data[] = {
226 	{
227 		.id		= IPA_MEM_UC_SHARED,
228 		.offset		= 0x0000,
229 		.size		= 0x0080,
230 		.canary_count	= 0,
231 	},
232 	{
233 		.id		= IPA_MEM_UC_INFO,
234 		.offset		= 0x0080,
235 		.size		= 0x0200,
236 		.canary_count	= 0,
237 	},
238 	{
239 		.id		= IPA_MEM_V4_FILTER_HASHED,
240 		.offset		= 0x0288,
241 		.size		= 0,
242 		.canary_count	= 2,
243 	},
244 	{
245 		.id		= IPA_MEM_V4_FILTER,
246 		.offset		= 0x0290,
247 		.size		= 0x0078,
248 		.canary_count	= 2,
249 	},
250 	{
251 		.id		= IPA_MEM_V6_FILTER_HASHED,
252 		.offset		= 0x0310,
253 		.size		= 0,
254 		.canary_count	= 2,
255 	},
256 	{
257 		.id		= IPA_MEM_V6_FILTER,
258 		.offset		= 0x0318,
259 		.size		= 0x0078,
260 		.canary_count	= 2,
261 	},
262 	{
263 		.id		= IPA_MEM_V4_ROUTE_HASHED,
264 		.offset		= 0x0398,
265 		.size		= 0,
266 		.canary_count	= 2,
267 	},
268 	{
269 		.id		= IPA_MEM_V4_ROUTE,
270 		.offset		= 0x03a0,
271 		.size		= 0x0078,
272 		.canary_count	= 2,
273 	},
274 	{
275 		.id		= IPA_MEM_V6_ROUTE_HASHED,
276 		.offset		= 0x0420,
277 		.size		= 0,
278 		.canary_count	= 2,
279 	},
280 	{
281 		.id		= IPA_MEM_V6_ROUTE,
282 		.offset		= 0x0428,
283 		.size		= 0x0078,
284 		.canary_count	= 2,
285 	},
286 	{
287 		.id		= IPA_MEM_MODEM_HEADER,
288 		.offset		= 0x04a8,
289 		.size		= 0x0140,
290 		.canary_count	= 2,
291 	},
292 	{
293 		.id		= IPA_MEM_MODEM_PROC_CTX,
294 		.offset		= 0x05f0,
295 		.size		= 0x0200,
296 		.canary_count	= 2,
297 	},
298 	{
299 		.id		= IPA_MEM_AP_PROC_CTX,
300 		.offset		= 0x07f0,
301 		.size		= 0x0200,
302 		.canary_count	= 0,
303 	},
304 	{
305 		.id		= IPA_MEM_PDN_CONFIG,
306 		.offset		= 0x09f8,
307 		.size		= 0x0050,
308 		.canary_count	= 2,
309 	},
310 	{
311 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
312 		.offset		= 0x0a50,
313 		.size		= 0x0060,
314 		.canary_count	= 2,
315 	},
316 	{
317 		.id		= IPA_MEM_STATS_TETHERING,
318 		.offset		= 0x0ab0,
319 		.size		= 0x0140,
320 		.canary_count	= 0,
321 	},
322 	{
323 		.id		= IPA_MEM_MODEM,
324 		.offset		= 0x0bf0,
325 		.size		= 0x140c,
326 		.canary_count	= 0,
327 	},
328 	{
329 		.id		= IPA_MEM_END_MARKER,
330 		.offset		= 0x2000,
331 		.size		= 0,
332 		.canary_count	= 1,
333 	},
334 };
335 
336 /* Memory configuration data for an SoC having IPA v4.2 */
337 static const struct ipa_mem_data ipa_mem_data = {
338 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
339 	.local		= ipa_mem_local_data,
340 	.imem_addr	= 0x146a8000,
341 	.imem_size	= 0x00002000,
342 	.smem_id	= 497,
343 	.smem_size	= 0x00002000,
344 };
345 
346 /* Interconnect rates are in 1000 byte/second units */
347 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
348 	{
349 		.name			= "memory",
350 		.peak_bandwidth		= 465000,	/* 465 MBps */
351 		.average_bandwidth	= 80000,	/* 80 MBps */
352 	},
353 	/* Average bandwidth is unused for the next two interconnects */
354 	{
355 		.name			= "imem",
356 		.peak_bandwidth		= 68570,	/* 68.570 MBps */
357 		.average_bandwidth	= 0,		/* unused */
358 	},
359 	{
360 		.name			= "config",
361 		.peak_bandwidth		= 30000,	/* 30 MBps */
362 		.average_bandwidth	= 0,		/* unused */
363 	},
364 };
365 
366 /* Clock and interconnect configuration data for an SoC having IPA v4.2 */
367 static const struct ipa_power_data ipa_power_data = {
368 	.core_clock_rate	= 100 * 1000 * 1000,	/* Hz */
369 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
370 	.interconnect_data	= ipa_interconnect_data,
371 };
372 
373 /* Configuration data for an SoC having IPA v4.2 */
374 const struct ipa_data ipa_data_v4_2 = {
375 	.version	= IPA_VERSION_4_2,
376 	/* backward_compat value is 0 */
377 	.qsb_count	= ARRAY_SIZE(ipa_qsb_data),
378 	.qsb_data	= ipa_qsb_data,
379 	.endpoint_count	= ARRAY_SIZE(ipa_gsi_endpoint_data),
380 	.endpoint_data	= ipa_gsi_endpoint_data,
381 	.resource_data	= &ipa_resource_data,
382 	.mem_data	= &ipa_mem_data,
383 	.power_data	= &ipa_power_data,
384 };
385