1 /*
2  * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
3  *
4  * Copyright (C) 2012 Alan Ott <alan@signal11.us>
5  *                    Signal 11 Software
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17 
18 #include <linux/spi/spi.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/regmap.h>
23 #include <linux/ieee802154.h>
24 #include <linux/irq.h>
25 #include <net/cfg802154.h>
26 #include <net/mac802154.h>
27 
28 /* MRF24J40 Short Address Registers */
29 #define REG_RXMCR	0x00  /* Receive MAC control */
30 #define BIT_PROMI	BIT(0)
31 #define BIT_ERRPKT	BIT(1)
32 #define BIT_NOACKRSP	BIT(5)
33 #define BIT_PANCOORD	BIT(3)
34 
35 #define REG_PANIDL	0x01  /* PAN ID (low) */
36 #define REG_PANIDH	0x02  /* PAN ID (high) */
37 #define REG_SADRL	0x03  /* Short address (low) */
38 #define REG_SADRH	0x04  /* Short address (high) */
39 #define REG_EADR0	0x05  /* Long address (low) (high is EADR7) */
40 #define REG_EADR1	0x06
41 #define REG_EADR2	0x07
42 #define REG_EADR3	0x08
43 #define REG_EADR4	0x09
44 #define REG_EADR5	0x0A
45 #define REG_EADR6	0x0B
46 #define REG_EADR7	0x0C
47 #define REG_RXFLUSH	0x0D
48 #define REG_ORDER	0x10
49 #define REG_TXMCR	0x11  /* Transmit MAC control */
50 #define TXMCR_MIN_BE_SHIFT		3
51 #define TXMCR_MIN_BE_MASK		0x18
52 #define TXMCR_CSMA_RETRIES_SHIFT	0
53 #define TXMCR_CSMA_RETRIES_MASK		0x07
54 
55 #define REG_ACKTMOUT	0x12
56 #define REG_ESLOTG1	0x13
57 #define REG_SYMTICKL	0x14
58 #define REG_SYMTICKH	0x15
59 #define REG_PACON0	0x16  /* Power Amplifier Control */
60 #define REG_PACON1	0x17  /* Power Amplifier Control */
61 #define REG_PACON2	0x18  /* Power Amplifier Control */
62 #define REG_TXBCON0	0x1A
63 #define REG_TXNCON	0x1B  /* Transmit Normal FIFO Control */
64 #define BIT_TXNTRIG	BIT(0)
65 #define BIT_TXNSECEN	BIT(1)
66 #define BIT_TXNACKREQ	BIT(2)
67 
68 #define REG_TXG1CON	0x1C
69 #define REG_TXG2CON	0x1D
70 #define REG_ESLOTG23	0x1E
71 #define REG_ESLOTG45	0x1F
72 #define REG_ESLOTG67	0x20
73 #define REG_TXPEND	0x21
74 #define REG_WAKECON	0x22
75 #define REG_FROMOFFSET	0x23
76 #define REG_TXSTAT	0x24  /* TX MAC Status Register */
77 #define REG_TXBCON1	0x25
78 #define REG_GATECLK	0x26
79 #define REG_TXTIME	0x27
80 #define REG_HSYMTMRL	0x28
81 #define REG_HSYMTMRH	0x29
82 #define REG_SOFTRST	0x2A  /* Soft Reset */
83 #define REG_SECCON0	0x2C
84 #define REG_SECCON1	0x2D
85 #define REG_TXSTBL	0x2E  /* TX Stabilization */
86 #define REG_RXSR	0x30
87 #define REG_INTSTAT	0x31  /* Interrupt Status */
88 #define BIT_TXNIF	BIT(0)
89 #define BIT_RXIF	BIT(3)
90 #define BIT_SECIF	BIT(4)
91 #define BIT_SECIGNORE	BIT(7)
92 
93 #define REG_INTCON	0x32  /* Interrupt Control */
94 #define BIT_TXNIE	BIT(0)
95 #define BIT_RXIE	BIT(3)
96 #define BIT_SECIE	BIT(4)
97 
98 #define REG_GPIO	0x33  /* GPIO */
99 #define REG_TRISGPIO	0x34  /* GPIO direction */
100 #define REG_SLPACK	0x35
101 #define REG_RFCTL	0x36  /* RF Control Mode Register */
102 #define BIT_RFRST	BIT(2)
103 
104 #define REG_SECCR2	0x37
105 #define REG_BBREG0	0x38
106 #define REG_BBREG1	0x39  /* Baseband Registers */
107 #define BIT_RXDECINV	BIT(2)
108 
109 #define REG_BBREG2	0x3A  /* */
110 #define BBREG2_CCA_MODE_SHIFT	6
111 #define BBREG2_CCA_MODE_MASK	0xc0
112 
113 #define REG_BBREG3	0x3B
114 #define REG_BBREG4	0x3C
115 #define REG_BBREG6	0x3E  /* */
116 #define REG_CCAEDTH	0x3F  /* Energy Detection Threshold */
117 
118 /* MRF24J40 Long Address Registers */
119 #define REG_RFCON0	0x200  /* RF Control Registers */
120 #define RFCON0_CH_SHIFT	4
121 #define RFCON0_CH_MASK	0xf0
122 #define RFOPT_RECOMMEND	3
123 
124 #define REG_RFCON1	0x201
125 #define REG_RFCON2	0x202
126 #define REG_RFCON3	0x203
127 
128 #define TXPWRL_MASK	0xc0
129 #define TXPWRL_SHIFT	6
130 #define TXPWRL_30	0x3
131 #define TXPWRL_20	0x2
132 #define TXPWRL_10	0x1
133 #define TXPWRL_0	0x0
134 
135 #define TXPWRS_MASK	0x38
136 #define TXPWRS_SHIFT	3
137 #define TXPWRS_6_3	0x7
138 #define TXPWRS_4_9	0x6
139 #define TXPWRS_3_7	0x5
140 #define TXPWRS_2_8	0x4
141 #define TXPWRS_1_9	0x3
142 #define TXPWRS_1_2	0x2
143 #define TXPWRS_0_5	0x1
144 #define TXPWRS_0	0x0
145 
146 #define REG_RFCON5	0x205
147 #define REG_RFCON6	0x206
148 #define REG_RFCON7	0x207
149 #define REG_RFCON8	0x208
150 #define REG_SLPCAL0	0x209
151 #define REG_SLPCAL1	0x20A
152 #define REG_SLPCAL2	0x20B
153 #define REG_RFSTATE	0x20F
154 #define REG_RSSI	0x210
155 #define REG_SLPCON0	0x211  /* Sleep Clock Control Registers */
156 #define BIT_INTEDGE	BIT(1)
157 
158 #define REG_SLPCON1	0x220
159 #define REG_WAKETIMEL	0x222  /* Wake-up Time Match Value Low */
160 #define REG_WAKETIMEH	0x223  /* Wake-up Time Match Value High */
161 #define REG_REMCNTL	0x224
162 #define REG_REMCNTH	0x225
163 #define REG_MAINCNT0	0x226
164 #define REG_MAINCNT1	0x227
165 #define REG_MAINCNT2	0x228
166 #define REG_MAINCNT3	0x229
167 #define REG_TESTMODE	0x22F  /* Test mode */
168 #define REG_ASSOEAR0	0x230
169 #define REG_ASSOEAR1	0x231
170 #define REG_ASSOEAR2	0x232
171 #define REG_ASSOEAR3	0x233
172 #define REG_ASSOEAR4	0x234
173 #define REG_ASSOEAR5	0x235
174 #define REG_ASSOEAR6	0x236
175 #define REG_ASSOEAR7	0x237
176 #define REG_ASSOSAR0	0x238
177 #define REG_ASSOSAR1	0x239
178 #define REG_UNONCE0	0x240
179 #define REG_UNONCE1	0x241
180 #define REG_UNONCE2	0x242
181 #define REG_UNONCE3	0x243
182 #define REG_UNONCE4	0x244
183 #define REG_UNONCE5	0x245
184 #define REG_UNONCE6	0x246
185 #define REG_UNONCE7	0x247
186 #define REG_UNONCE8	0x248
187 #define REG_UNONCE9	0x249
188 #define REG_UNONCE10	0x24A
189 #define REG_UNONCE11	0x24B
190 #define REG_UNONCE12	0x24C
191 #define REG_RX_FIFO	0x300  /* Receive FIFO */
192 
193 /* Device configuration: Only channels 11-26 on page 0 are supported. */
194 #define MRF24J40_CHAN_MIN 11
195 #define MRF24J40_CHAN_MAX 26
196 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
197 		      - ((u32)1 << MRF24J40_CHAN_MIN))
198 
199 #define TX_FIFO_SIZE 128 /* From datasheet */
200 #define RX_FIFO_SIZE 144 /* From datasheet */
201 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
202 
203 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
204 
205 /* Device Private Data */
206 struct mrf24j40 {
207 	struct spi_device *spi;
208 	struct ieee802154_hw *hw;
209 
210 	struct regmap *regmap_short;
211 	struct regmap *regmap_long;
212 
213 	/* for writing txfifo */
214 	struct spi_message tx_msg;
215 	u8 tx_hdr_buf[2];
216 	struct spi_transfer tx_hdr_trx;
217 	u8 tx_len_buf[2];
218 	struct spi_transfer tx_len_trx;
219 	struct spi_transfer tx_buf_trx;
220 	struct sk_buff *tx_skb;
221 
222 	/* post transmit message to send frame out  */
223 	struct spi_message tx_post_msg;
224 	u8 tx_post_buf[2];
225 	struct spi_transfer tx_post_trx;
226 
227 	/* for protect/unprotect/read length rxfifo */
228 	struct spi_message rx_msg;
229 	u8 rx_buf[3];
230 	struct spi_transfer rx_trx;
231 
232 	/* receive handling */
233 	struct spi_message rx_buf_msg;
234 	u8 rx_addr_buf[2];
235 	struct spi_transfer rx_addr_trx;
236 	u8 rx_lqi_buf[2];
237 	struct spi_transfer rx_lqi_trx;
238 	u8 rx_fifo_buf[RX_FIFO_SIZE];
239 	struct spi_transfer rx_fifo_buf_trx;
240 
241 	/* isr handling for reading intstat */
242 	struct spi_message irq_msg;
243 	u8 irq_buf[2];
244 	struct spi_transfer irq_trx;
245 };
246 
247 /* regmap information for short address register access */
248 #define MRF24J40_SHORT_WRITE	0x01
249 #define MRF24J40_SHORT_READ	0x00
250 #define MRF24J40_SHORT_NUMREGS	0x3F
251 
252 /* regmap information for long address register access */
253 #define MRF24J40_LONG_ACCESS	0x80
254 #define MRF24J40_LONG_NUMREGS	0x38F
255 
256 /* Read/Write SPI Commands for Short and Long Address registers. */
257 #define MRF24J40_READSHORT(reg) ((reg) << 1)
258 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
259 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
260 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
261 
262 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
263 #define MAX_SPI_SPEED_HZ 10000000
264 
265 #define printdev(X) (&X->spi->dev)
266 
267 static bool
268 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
269 {
270 	switch (reg) {
271 	case REG_RXMCR:
272 	case REG_PANIDL:
273 	case REG_PANIDH:
274 	case REG_SADRL:
275 	case REG_SADRH:
276 	case REG_EADR0:
277 	case REG_EADR1:
278 	case REG_EADR2:
279 	case REG_EADR3:
280 	case REG_EADR4:
281 	case REG_EADR5:
282 	case REG_EADR6:
283 	case REG_EADR7:
284 	case REG_RXFLUSH:
285 	case REG_ORDER:
286 	case REG_TXMCR:
287 	case REG_ACKTMOUT:
288 	case REG_ESLOTG1:
289 	case REG_SYMTICKL:
290 	case REG_SYMTICKH:
291 	case REG_PACON0:
292 	case REG_PACON1:
293 	case REG_PACON2:
294 	case REG_TXBCON0:
295 	case REG_TXNCON:
296 	case REG_TXG1CON:
297 	case REG_TXG2CON:
298 	case REG_ESLOTG23:
299 	case REG_ESLOTG45:
300 	case REG_ESLOTG67:
301 	case REG_TXPEND:
302 	case REG_WAKECON:
303 	case REG_FROMOFFSET:
304 	case REG_TXBCON1:
305 	case REG_GATECLK:
306 	case REG_TXTIME:
307 	case REG_HSYMTMRL:
308 	case REG_HSYMTMRH:
309 	case REG_SOFTRST:
310 	case REG_SECCON0:
311 	case REG_SECCON1:
312 	case REG_TXSTBL:
313 	case REG_RXSR:
314 	case REG_INTCON:
315 	case REG_TRISGPIO:
316 	case REG_GPIO:
317 	case REG_RFCTL:
318 	case REG_SECCR2:
319 	case REG_SLPACK:
320 	case REG_BBREG0:
321 	case REG_BBREG1:
322 	case REG_BBREG2:
323 	case REG_BBREG3:
324 	case REG_BBREG4:
325 	case REG_BBREG6:
326 	case REG_CCAEDTH:
327 		return true;
328 	default:
329 		return false;
330 	}
331 }
332 
333 static bool
334 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
335 {
336 	bool rc;
337 
338 	/* all writeable are also readable */
339 	rc = mrf24j40_short_reg_writeable(dev, reg);
340 	if (rc)
341 		return rc;
342 
343 	/* readonly regs */
344 	switch (reg) {
345 	case REG_TXSTAT:
346 	case REG_INTSTAT:
347 		return true;
348 	default:
349 		return false;
350 	}
351 }
352 
353 static bool
354 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
355 {
356 	/* can be changed during runtime */
357 	switch (reg) {
358 	case REG_TXSTAT:
359 	case REG_INTSTAT:
360 	case REG_RXFLUSH:
361 	case REG_TXNCON:
362 	case REG_SOFTRST:
363 	case REG_RFCTL:
364 	case REG_TXBCON0:
365 	case REG_TXG1CON:
366 	case REG_TXG2CON:
367 	case REG_TXBCON1:
368 	case REG_SECCON0:
369 	case REG_RXSR:
370 	case REG_SLPACK:
371 	case REG_SECCR2:
372 	case REG_BBREG6:
373 	/* use them in spi_async and regmap so it's volatile */
374 	case REG_BBREG1:
375 		return true;
376 	default:
377 		return false;
378 	}
379 }
380 
381 static bool
382 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
383 {
384 	/* don't clear irq line on read */
385 	switch (reg) {
386 	case REG_INTSTAT:
387 		return true;
388 	default:
389 		return false;
390 	}
391 }
392 
393 static const struct regmap_config mrf24j40_short_regmap = {
394 	.name = "mrf24j40_short",
395 	.reg_bits = 7,
396 	.val_bits = 8,
397 	.pad_bits = 1,
398 	.write_flag_mask = MRF24J40_SHORT_WRITE,
399 	.read_flag_mask = MRF24J40_SHORT_READ,
400 	.cache_type = REGCACHE_RBTREE,
401 	.max_register = MRF24J40_SHORT_NUMREGS,
402 	.writeable_reg = mrf24j40_short_reg_writeable,
403 	.readable_reg = mrf24j40_short_reg_readable,
404 	.volatile_reg = mrf24j40_short_reg_volatile,
405 	.precious_reg = mrf24j40_short_reg_precious,
406 };
407 
408 static bool
409 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
410 {
411 	switch (reg) {
412 	case REG_RFCON0:
413 	case REG_RFCON1:
414 	case REG_RFCON2:
415 	case REG_RFCON3:
416 	case REG_RFCON5:
417 	case REG_RFCON6:
418 	case REG_RFCON7:
419 	case REG_RFCON8:
420 	case REG_SLPCAL2:
421 	case REG_SLPCON0:
422 	case REG_SLPCON1:
423 	case REG_WAKETIMEL:
424 	case REG_WAKETIMEH:
425 	case REG_REMCNTL:
426 	case REG_REMCNTH:
427 	case REG_MAINCNT0:
428 	case REG_MAINCNT1:
429 	case REG_MAINCNT2:
430 	case REG_MAINCNT3:
431 	case REG_TESTMODE:
432 	case REG_ASSOEAR0:
433 	case REG_ASSOEAR1:
434 	case REG_ASSOEAR2:
435 	case REG_ASSOEAR3:
436 	case REG_ASSOEAR4:
437 	case REG_ASSOEAR5:
438 	case REG_ASSOEAR6:
439 	case REG_ASSOEAR7:
440 	case REG_ASSOSAR0:
441 	case REG_ASSOSAR1:
442 	case REG_UNONCE0:
443 	case REG_UNONCE1:
444 	case REG_UNONCE2:
445 	case REG_UNONCE3:
446 	case REG_UNONCE4:
447 	case REG_UNONCE5:
448 	case REG_UNONCE6:
449 	case REG_UNONCE7:
450 	case REG_UNONCE8:
451 	case REG_UNONCE9:
452 	case REG_UNONCE10:
453 	case REG_UNONCE11:
454 	case REG_UNONCE12:
455 		return true;
456 	default:
457 		return false;
458 	}
459 }
460 
461 static bool
462 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
463 {
464 	bool rc;
465 
466 	/* all writeable are also readable */
467 	rc = mrf24j40_long_reg_writeable(dev, reg);
468 	if (rc)
469 		return rc;
470 
471 	/* readonly regs */
472 	switch (reg) {
473 	case REG_SLPCAL0:
474 	case REG_SLPCAL1:
475 	case REG_RFSTATE:
476 	case REG_RSSI:
477 		return true;
478 	default:
479 		return false;
480 	}
481 }
482 
483 static bool
484 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
485 {
486 	/* can be changed during runtime */
487 	switch (reg) {
488 	case REG_SLPCAL0:
489 	case REG_SLPCAL1:
490 	case REG_SLPCAL2:
491 	case REG_RFSTATE:
492 	case REG_RSSI:
493 	case REG_MAINCNT3:
494 		return true;
495 	default:
496 		return false;
497 	}
498 }
499 
500 static const struct regmap_config mrf24j40_long_regmap = {
501 	.name = "mrf24j40_long",
502 	.reg_bits = 11,
503 	.val_bits = 8,
504 	.pad_bits = 5,
505 	.write_flag_mask = MRF24J40_LONG_ACCESS,
506 	.read_flag_mask = MRF24J40_LONG_ACCESS,
507 	.cache_type = REGCACHE_RBTREE,
508 	.max_register = MRF24J40_LONG_NUMREGS,
509 	.writeable_reg = mrf24j40_long_reg_writeable,
510 	.readable_reg = mrf24j40_long_reg_readable,
511 	.volatile_reg = mrf24j40_long_reg_volatile,
512 };
513 
514 static int mrf24j40_long_regmap_write(void *context, const void *data,
515 				      size_t count)
516 {
517 	struct spi_device *spi = context;
518 	u8 buf[3];
519 
520 	if (count > 3)
521 		return -EINVAL;
522 
523 	/* regmap supports read/write mask only in frist byte
524 	 * long write access need to set the 12th bit, so we
525 	 * make special handling for write.
526 	 */
527 	memcpy(buf, data, count);
528 	buf[1] |= (1 << 4);
529 
530 	return spi_write(spi, buf, count);
531 }
532 
533 static int
534 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
535 			  void *val, size_t val_size)
536 {
537 	struct spi_device *spi = context;
538 
539 	return spi_write_then_read(spi, reg, reg_size, val, val_size);
540 }
541 
542 static const struct regmap_bus mrf24j40_long_regmap_bus = {
543 	.write = mrf24j40_long_regmap_write,
544 	.read = mrf24j40_long_regmap_read,
545 	.reg_format_endian_default = REGMAP_ENDIAN_BIG,
546 	.val_format_endian_default = REGMAP_ENDIAN_BIG,
547 };
548 
549 static void write_tx_buf_complete(void *context)
550 {
551 	struct mrf24j40 *devrec = context;
552 	__le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
553 	u8 val = BIT_TXNTRIG;
554 	int ret;
555 
556 	if (ieee802154_is_secen(fc))
557 		val |= BIT_TXNSECEN;
558 
559 	if (ieee802154_is_ackreq(fc))
560 		val |= BIT_TXNACKREQ;
561 
562 	devrec->tx_post_msg.complete = NULL;
563 	devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
564 	devrec->tx_post_buf[1] = val;
565 
566 	ret = spi_async(devrec->spi, &devrec->tx_post_msg);
567 	if (ret)
568 		dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
569 }
570 
571 /* This function relies on an undocumented write method. Once a write command
572    and address is set, as many bytes of data as desired can be clocked into
573    the device. The datasheet only shows setting one byte at a time. */
574 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
575 			const u8 *data, size_t length)
576 {
577 	u16 cmd;
578 	int ret;
579 
580 	/* Range check the length. 2 bytes are used for the length fields.*/
581 	if (length > TX_FIFO_SIZE-2) {
582 		dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
583 		length = TX_FIFO_SIZE-2;
584 	}
585 
586 	cmd = MRF24J40_WRITELONG(reg);
587 	devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
588 	devrec->tx_hdr_buf[1] = cmd & 0xff;
589 	devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
590 	devrec->tx_len_buf[1] = length; /* Total length */
591 	devrec->tx_buf_trx.tx_buf = data;
592 	devrec->tx_buf_trx.len = length;
593 
594 	ret = spi_async(devrec->spi, &devrec->tx_msg);
595 	if (ret)
596 		dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
597 
598 	return ret;
599 }
600 
601 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
602 {
603 	struct mrf24j40 *devrec = hw->priv;
604 
605 	dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
606 	devrec->tx_skb = skb;
607 
608 	return write_tx_buf(devrec, 0x000, skb->data, skb->len);
609 }
610 
611 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
612 {
613 	/* TODO: */
614 	pr_warn("mrf24j40: ed not implemented\n");
615 	*level = 0;
616 	return 0;
617 }
618 
619 static int mrf24j40_start(struct ieee802154_hw *hw)
620 {
621 	struct mrf24j40 *devrec = hw->priv;
622 
623 	dev_dbg(printdev(devrec), "start\n");
624 
625 	/* Clear TXNIE and RXIE. Enable interrupts */
626 	return regmap_update_bits(devrec->regmap_short, REG_INTCON,
627 				  BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0);
628 }
629 
630 static void mrf24j40_stop(struct ieee802154_hw *hw)
631 {
632 	struct mrf24j40 *devrec = hw->priv;
633 
634 	dev_dbg(printdev(devrec), "stop\n");
635 
636 	/* Set TXNIE and RXIE. Disable Interrupts */
637 	regmap_update_bits(devrec->regmap_short, REG_INTCON,
638 			   BIT_TXNIE | BIT_RXIE, BIT_TXNIE | BIT_RXIE);
639 }
640 
641 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
642 {
643 	struct mrf24j40 *devrec = hw->priv;
644 	u8 val;
645 	int ret;
646 
647 	dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
648 
649 	WARN_ON(page != 0);
650 	WARN_ON(channel < MRF24J40_CHAN_MIN);
651 	WARN_ON(channel > MRF24J40_CHAN_MAX);
652 
653 	/* Set Channel TODO */
654 	val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
655 	ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
656 				 RFCON0_CH_MASK, val);
657 	if (ret)
658 		return ret;
659 
660 	/* RF Reset */
661 	ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
662 				 BIT_RFRST);
663 	if (ret)
664 		return ret;
665 
666 	ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
667 	if (!ret)
668 		udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
669 
670 	return ret;
671 }
672 
673 static int mrf24j40_filter(struct ieee802154_hw *hw,
674 			   struct ieee802154_hw_addr_filt *filt,
675 			   unsigned long changed)
676 {
677 	struct mrf24j40 *devrec = hw->priv;
678 
679 	dev_dbg(printdev(devrec), "filter\n");
680 
681 	if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
682 		/* Short Addr */
683 		u8 addrh, addrl;
684 
685 		addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
686 		addrl = le16_to_cpu(filt->short_addr) & 0xff;
687 
688 		regmap_write(devrec->regmap_short, REG_SADRH, addrh);
689 		regmap_write(devrec->regmap_short, REG_SADRL, addrl);
690 		dev_dbg(printdev(devrec),
691 			"Set short addr to %04hx\n", filt->short_addr);
692 	}
693 
694 	if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
695 		/* Device Address */
696 		u8 i, addr[8];
697 
698 		memcpy(addr, &filt->ieee_addr, 8);
699 		for (i = 0; i < 8; i++)
700 			regmap_write(devrec->regmap_short, REG_EADR0 + i,
701 				     addr[i]);
702 
703 #ifdef DEBUG
704 		pr_debug("Set long addr to: ");
705 		for (i = 0; i < 8; i++)
706 			pr_debug("%02hhx ", addr[7 - i]);
707 		pr_debug("\n");
708 #endif
709 	}
710 
711 	if (changed & IEEE802154_AFILT_PANID_CHANGED) {
712 		/* PAN ID */
713 		u8 panidl, panidh;
714 
715 		panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
716 		panidl = le16_to_cpu(filt->pan_id) & 0xff;
717 		regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
718 		regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
719 
720 		dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
721 	}
722 
723 	if (changed & IEEE802154_AFILT_PANC_CHANGED) {
724 		/* Pan Coordinator */
725 		u8 val;
726 		int ret;
727 
728 		if (filt->pan_coord)
729 			val = BIT_PANCOORD;
730 		else
731 			val = 0;
732 		ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
733 					 BIT_PANCOORD, val);
734 		if (ret)
735 			return ret;
736 
737 		/* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
738 		 * REG_ORDER is maintained as default (no beacon/superframe).
739 		 */
740 
741 		dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
742 			filt->pan_coord ? "on" : "off");
743 	}
744 
745 	return 0;
746 }
747 
748 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
749 {
750 	int ret;
751 
752 	/* Turn back on reception of packets off the air. */
753 	devrec->rx_msg.complete = NULL;
754 	devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
755 	devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
756 	ret = spi_async(devrec->spi, &devrec->rx_msg);
757 	if (ret)
758 		dev_err(printdev(devrec), "failed to unlock rx buffer\n");
759 }
760 
761 static void mrf24j40_handle_rx_read_buf_complete(void *context)
762 {
763 	struct mrf24j40 *devrec = context;
764 	u8 len = devrec->rx_buf[2];
765 	u8 rx_local_buf[RX_FIFO_SIZE];
766 	struct sk_buff *skb;
767 
768 	memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
769 	mrf24j40_handle_rx_read_buf_unlock(devrec);
770 
771 	skb = dev_alloc_skb(IEEE802154_MTU);
772 	if (!skb) {
773 		dev_err(printdev(devrec), "failed to allocate skb\n");
774 		return;
775 	}
776 
777 	skb_put_data(skb, rx_local_buf, len);
778 	ieee802154_rx_irqsafe(devrec->hw, skb, 0);
779 
780 #ifdef DEBUG
781 	 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
782 			rx_local_buf, len, 0);
783 	 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
784 		  devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
785 #endif
786 }
787 
788 static void mrf24j40_handle_rx_read_buf(void *context)
789 {
790 	struct mrf24j40 *devrec = context;
791 	u16 cmd;
792 	int ret;
793 
794 	/* if length is invalid read the full MTU */
795 	if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
796 		devrec->rx_buf[2] = IEEE802154_MTU;
797 
798 	cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
799 	devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
800 	devrec->rx_addr_buf[1] = cmd & 0xff;
801 	devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
802 	ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
803 	if (ret) {
804 		dev_err(printdev(devrec), "failed to read rx buffer\n");
805 		mrf24j40_handle_rx_read_buf_unlock(devrec);
806 	}
807 }
808 
809 static void mrf24j40_handle_rx_read_len(void *context)
810 {
811 	struct mrf24j40 *devrec = context;
812 	u16 cmd;
813 	int ret;
814 
815 	/* read the length of received frame */
816 	devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
817 	devrec->rx_trx.len = 3;
818 	cmd = MRF24J40_READLONG(REG_RX_FIFO);
819 	devrec->rx_buf[0] = cmd >> 8 & 0xff;
820 	devrec->rx_buf[1] = cmd & 0xff;
821 
822 	ret = spi_async(devrec->spi, &devrec->rx_msg);
823 	if (ret) {
824 		dev_err(printdev(devrec), "failed to read rx buffer length\n");
825 		mrf24j40_handle_rx_read_buf_unlock(devrec);
826 	}
827 }
828 
829 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
830 {
831 	/* Turn off reception of packets off the air. This prevents the
832 	 * device from overwriting the buffer while we're reading it.
833 	 */
834 	devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
835 	devrec->rx_trx.len = 2;
836 	devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
837 	devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
838 
839 	return spi_async(devrec->spi, &devrec->rx_msg);
840 }
841 
842 static int
843 mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
844 		     u8 retries)
845 {
846 	struct mrf24j40 *devrec = hw->priv;
847 	u8 val;
848 
849 	/* min_be */
850 	val = min_be << TXMCR_MIN_BE_SHIFT;
851 	/* csma backoffs */
852 	val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
853 
854 	return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
855 				  TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
856 				  val);
857 }
858 
859 static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
860 				 const struct wpan_phy_cca *cca)
861 {
862 	struct mrf24j40 *devrec = hw->priv;
863 	u8 val;
864 
865 	/* mapping 802.15.4 to driver spec */
866 	switch (cca->mode) {
867 	case NL802154_CCA_ENERGY:
868 		val = 2;
869 		break;
870 	case NL802154_CCA_CARRIER:
871 		val = 1;
872 		break;
873 	case NL802154_CCA_ENERGY_CARRIER:
874 		switch (cca->opt) {
875 		case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
876 			val = 3;
877 			break;
878 		default:
879 			return -EINVAL;
880 		}
881 		break;
882 	default:
883 		return -EINVAL;
884 	}
885 
886 	return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
887 				  BBREG2_CCA_MODE_MASK,
888 				  val << BBREG2_CCA_MODE_SHIFT);
889 }
890 
891 /* array for representing ed levels */
892 static const s32 mrf24j40_ed_levels[] = {
893 	-9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
894 	-8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
895 	-7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
896 	-6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
897 	-5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
898 	-4000, -3900, -3800, -3700, -3600, -3500
899 };
900 
901 /* map ed levels to register value */
902 static const s32 mrf24j40_ed_levels_map[][2] = {
903 	{ -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
904 	{ -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
905 	{ -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
906 	{ -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
907 	{ -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
908 	{ -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
909 	{ -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
910 	{ -6100, 133 },	{ -6000, 138 }, { -5900, 143 }, { -5800, 148 },
911 	{ -5700, 153 }, { -5600, 159 },	{ -5500, 165 }, { -5400, 170 },
912 	{ -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
913 	{ -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
914 	{ -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
915 	{ -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
916 	{ -3700, 253 }, { -3600, 254 }, { -3500, 255 },
917 };
918 
919 static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
920 {
921 	struct mrf24j40 *devrec = hw->priv;
922 	int i;
923 
924 	for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
925 		if (mrf24j40_ed_levels_map[i][0] == mbm)
926 			return regmap_write(devrec->regmap_short, REG_CCAEDTH,
927 					    mrf24j40_ed_levels_map[i][1]);
928 	}
929 
930 	return -EINVAL;
931 }
932 
933 static const s32 mrf24j40ma_powers[] = {
934 	0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190,
935 	-1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370,
936 	-2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630,
937 };
938 
939 static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
940 {
941 	struct mrf24j40 *devrec = hw->priv;
942 	s32 small_scale;
943 	u8 val;
944 
945 	if (0 >= mbm && mbm > -1000) {
946 		val = TXPWRL_0 << TXPWRL_SHIFT;
947 		small_scale = mbm;
948 	} else if (-1000 >= mbm && mbm > -2000) {
949 		val = TXPWRL_10 << TXPWRL_SHIFT;
950 		small_scale = mbm + 1000;
951 	} else if (-2000 >= mbm && mbm > -3000) {
952 		val = TXPWRL_20 << TXPWRL_SHIFT;
953 		small_scale = mbm + 2000;
954 	} else if (-3000 >= mbm && mbm > -4000) {
955 		val = TXPWRL_30 << TXPWRL_SHIFT;
956 		small_scale = mbm + 3000;
957 	} else {
958 		return -EINVAL;
959 	}
960 
961 	switch (small_scale) {
962 	case 0:
963 		val |= (TXPWRS_0 << TXPWRS_SHIFT);
964 		break;
965 	case -50:
966 		val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
967 		break;
968 	case -120:
969 		val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
970 		break;
971 	case -190:
972 		val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
973 		break;
974 	case -280:
975 		val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
976 		break;
977 	case -370:
978 		val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
979 		break;
980 	case -490:
981 		val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
982 		break;
983 	case -630:
984 		val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
985 		break;
986 	default:
987 		return -EINVAL;
988 	}
989 
990 	return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
991 				  TXPWRL_MASK | TXPWRS_MASK, val);
992 }
993 
994 static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
995 {
996 	struct mrf24j40 *devrec = hw->priv;
997 	int ret;
998 
999 	if (on) {
1000 		/* set PROMI, ERRPKT and NOACKRSP */
1001 		ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
1002 					 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
1003 					 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
1004 	} else {
1005 		/* clear PROMI, ERRPKT and NOACKRSP */
1006 		ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
1007 					 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
1008 					 0);
1009 	}
1010 
1011 	return ret;
1012 }
1013 
1014 static const struct ieee802154_ops mrf24j40_ops = {
1015 	.owner = THIS_MODULE,
1016 	.xmit_async = mrf24j40_tx,
1017 	.ed = mrf24j40_ed,
1018 	.start = mrf24j40_start,
1019 	.stop = mrf24j40_stop,
1020 	.set_channel = mrf24j40_set_channel,
1021 	.set_hw_addr_filt = mrf24j40_filter,
1022 	.set_csma_params = mrf24j40_csma_params,
1023 	.set_cca_mode = mrf24j40_set_cca_mode,
1024 	.set_cca_ed_level = mrf24j40_set_cca_ed_level,
1025 	.set_txpower = mrf24j40_set_txpower,
1026 	.set_promiscuous_mode = mrf24j40_set_promiscuous_mode,
1027 };
1028 
1029 static void mrf24j40_intstat_complete(void *context)
1030 {
1031 	struct mrf24j40 *devrec = context;
1032 	u8 intstat = devrec->irq_buf[1];
1033 
1034 	enable_irq(devrec->spi->irq);
1035 
1036 	/* Ignore Rx security decryption */
1037 	if (intstat & BIT_SECIF)
1038 		regmap_write_async(devrec->regmap_short, REG_SECCON0,
1039 				   BIT_SECIGNORE);
1040 
1041 	/* Check for TX complete */
1042 	if (intstat & BIT_TXNIF)
1043 		ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
1044 
1045 	/* Check for Rx */
1046 	if (intstat & BIT_RXIF)
1047 		mrf24j40_handle_rx(devrec);
1048 }
1049 
1050 static irqreturn_t mrf24j40_isr(int irq, void *data)
1051 {
1052 	struct mrf24j40 *devrec = data;
1053 	int ret;
1054 
1055 	disable_irq_nosync(irq);
1056 
1057 	devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
1058 	devrec->irq_buf[1] = 0;
1059 
1060 	/* Read the interrupt status */
1061 	ret = spi_async(devrec->spi, &devrec->irq_msg);
1062 	if (ret) {
1063 		enable_irq(irq);
1064 		return IRQ_NONE;
1065 	}
1066 
1067 	return IRQ_HANDLED;
1068 }
1069 
1070 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
1071 {
1072 	u32 irq_type;
1073 	int ret;
1074 
1075 	/* Initialize the device.
1076 		From datasheet section 3.2: Initialization. */
1077 	ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
1078 	if (ret)
1079 		goto err_ret;
1080 
1081 	ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
1082 	if (ret)
1083 		goto err_ret;
1084 
1085 	ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
1086 	if (ret)
1087 		goto err_ret;
1088 
1089 	ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
1090 	if (ret)
1091 		goto err_ret;
1092 
1093 	ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
1094 	if (ret)
1095 		goto err_ret;
1096 
1097 	ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
1098 	if (ret)
1099 		goto err_ret;
1100 
1101 	ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
1102 	if (ret)
1103 		goto err_ret;
1104 
1105 	ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
1106 	if (ret)
1107 		goto err_ret;
1108 
1109 	ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
1110 	if (ret)
1111 		goto err_ret;
1112 
1113 	ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
1114 	if (ret)
1115 		goto err_ret;
1116 
1117 	ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
1118 	if (ret)
1119 		goto err_ret;
1120 
1121 	ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
1122 	if (ret)
1123 		goto err_ret;
1124 
1125 	ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
1126 	if (ret)
1127 		goto err_ret;
1128 
1129 	ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
1130 	if (ret)
1131 		goto err_ret;
1132 
1133 	ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
1134 	if (ret)
1135 		goto err_ret;
1136 
1137 	udelay(192);
1138 
1139 	/* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
1140 	ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
1141 	if (ret)
1142 		goto err_ret;
1143 
1144 	if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
1145 		/* Enable external amplifier.
1146 		 * From MRF24J40MC datasheet section 1.3: Operation.
1147 		 */
1148 		regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
1149 				   0x07);
1150 
1151 		/* Set GPIO3 as output. */
1152 		regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
1153 				   0x08);
1154 
1155 		/* Set GPIO3 HIGH to enable U5 voltage regulator */
1156 		regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
1157 
1158 		/* Reduce TX pwr to meet FCC requirements.
1159 		 * From MRF24J40MC datasheet section 3.1.1
1160 		 */
1161 		regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
1162 	}
1163 
1164 	irq_type = irq_get_trigger_type(devrec->spi->irq);
1165 	if (irq_type == IRQ_TYPE_EDGE_RISING ||
1166 	    irq_type == IRQ_TYPE_EDGE_FALLING)
1167 		dev_warn(&devrec->spi->dev,
1168 			 "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n");
1169 	switch (irq_type) {
1170 	case IRQ_TYPE_EDGE_RISING:
1171 	case IRQ_TYPE_LEVEL_HIGH:
1172 		/* set interrupt polarity to rising */
1173 		ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
1174 					 BIT_INTEDGE, BIT_INTEDGE);
1175 		if (ret)
1176 			goto err_ret;
1177 		break;
1178 	default:
1179 		/* default is falling edge */
1180 		break;
1181 	}
1182 
1183 	return 0;
1184 
1185 err_ret:
1186 	return ret;
1187 }
1188 
1189 static void
1190 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1191 {
1192 	spi_message_init(&devrec->tx_msg);
1193 	devrec->tx_msg.context = devrec;
1194 	devrec->tx_msg.complete = write_tx_buf_complete;
1195 	devrec->tx_hdr_trx.len = 2;
1196 	devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1197 	spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1198 	devrec->tx_len_trx.len = 2;
1199 	devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1200 	spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1201 	spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1202 
1203 	spi_message_init(&devrec->tx_post_msg);
1204 	devrec->tx_post_msg.context = devrec;
1205 	devrec->tx_post_trx.len = 2;
1206 	devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1207 	spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1208 }
1209 
1210 static void
1211 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
1212 {
1213 	spi_message_init(&devrec->rx_msg);
1214 	devrec->rx_msg.context = devrec;
1215 	devrec->rx_trx.len = 2;
1216 	devrec->rx_trx.tx_buf = devrec->rx_buf;
1217 	devrec->rx_trx.rx_buf = devrec->rx_buf;
1218 	spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1219 
1220 	spi_message_init(&devrec->rx_buf_msg);
1221 	devrec->rx_buf_msg.context = devrec;
1222 	devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1223 	devrec->rx_addr_trx.len = 2;
1224 	devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1225 	spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1226 	devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1227 	spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1228 	devrec->rx_lqi_trx.len = 2;
1229 	devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1230 	spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1231 }
1232 
1233 static void
1234 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1235 {
1236 	spi_message_init(&devrec->irq_msg);
1237 	devrec->irq_msg.context = devrec;
1238 	devrec->irq_msg.complete = mrf24j40_intstat_complete;
1239 	devrec->irq_trx.len = 2;
1240 	devrec->irq_trx.tx_buf = devrec->irq_buf;
1241 	devrec->irq_trx.rx_buf = devrec->irq_buf;
1242 	spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1243 }
1244 
1245 static void  mrf24j40_phy_setup(struct mrf24j40 *devrec)
1246 {
1247 	ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1248 	devrec->hw->phy->current_channel = 11;
1249 
1250 	/* mrf24j40 supports max_minbe 0 - 3 */
1251 	devrec->hw->phy->supported.max_minbe = 3;
1252 	/* datasheet doesn't say anything about max_be, but we have min_be
1253 	 * So we assume the max_be default.
1254 	 */
1255 	devrec->hw->phy->supported.min_maxbe = 5;
1256 	devrec->hw->phy->supported.max_maxbe = 5;
1257 
1258 	devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;
1259 	devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1260 					       BIT(NL802154_CCA_CARRIER) |
1261 					       BIT(NL802154_CCA_ENERGY_CARRIER);
1262 	devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
1263 
1264 	devrec->hw->phy->cca_ed_level = -6900;
1265 	devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
1266 	devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
1267 
1268 	switch (spi_get_device_id(devrec->spi)->driver_data) {
1269 	case MRF24J40:
1270 	case MRF24J40MA:
1271 		devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers;
1272 		devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers);
1273 		devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER;
1274 		break;
1275 	default:
1276 		break;
1277 	}
1278 }
1279 
1280 static int mrf24j40_probe(struct spi_device *spi)
1281 {
1282 	int ret = -ENOMEM, irq_type;
1283 	struct ieee802154_hw *hw;
1284 	struct mrf24j40 *devrec;
1285 
1286 	dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
1287 
1288 	/* Register with the 802154 subsystem */
1289 
1290 	hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1291 	if (!hw)
1292 		goto err_ret;
1293 
1294 	devrec = hw->priv;
1295 	devrec->spi = spi;
1296 	spi_set_drvdata(spi, devrec);
1297 	devrec->hw = hw;
1298 	devrec->hw->parent = &spi->dev;
1299 	devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1300 	devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1301 			    IEEE802154_HW_CSMA_PARAMS |
1302 			    IEEE802154_HW_PROMISCUOUS;
1303 
1304 	devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
1305 				 WPAN_PHY_FLAG_CCA_ED_LEVEL;
1306 
1307 	mrf24j40_setup_tx_spi_messages(devrec);
1308 	mrf24j40_setup_rx_spi_messages(devrec);
1309 	mrf24j40_setup_irq_spi_messages(devrec);
1310 
1311 	devrec->regmap_short = devm_regmap_init_spi(spi,
1312 						    &mrf24j40_short_regmap);
1313 	if (IS_ERR(devrec->regmap_short)) {
1314 		ret = PTR_ERR(devrec->regmap_short);
1315 		dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1316 			ret);
1317 		goto err_register_device;
1318 	}
1319 
1320 	devrec->regmap_long = devm_regmap_init(&spi->dev,
1321 					       &mrf24j40_long_regmap_bus,
1322 					       spi, &mrf24j40_long_regmap);
1323 	if (IS_ERR(devrec->regmap_long)) {
1324 		ret = PTR_ERR(devrec->regmap_long);
1325 		dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1326 			ret);
1327 		goto err_register_device;
1328 	}
1329 
1330 	if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1331 		dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1332 			 MAX_SPI_SPEED_HZ);
1333 		ret = -EINVAL;
1334 		goto err_register_device;
1335 	}
1336 
1337 	ret = mrf24j40_hw_init(devrec);
1338 	if (ret)
1339 		goto err_register_device;
1340 
1341 	mrf24j40_phy_setup(devrec);
1342 
1343 	/* request IRQF_TRIGGER_LOW as fallback default */
1344 	irq_type = irq_get_trigger_type(spi->irq);
1345 	if (!irq_type)
1346 		irq_type = IRQF_TRIGGER_LOW;
1347 
1348 	ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1349 			       irq_type, dev_name(&spi->dev), devrec);
1350 	if (ret) {
1351 		dev_err(printdev(devrec), "Unable to get IRQ");
1352 		goto err_register_device;
1353 	}
1354 
1355 	dev_dbg(printdev(devrec), "registered mrf24j40\n");
1356 	ret = ieee802154_register_hw(devrec->hw);
1357 	if (ret)
1358 		goto err_register_device;
1359 
1360 	return 0;
1361 
1362 err_register_device:
1363 	ieee802154_free_hw(devrec->hw);
1364 err_ret:
1365 	return ret;
1366 }
1367 
1368 static int mrf24j40_remove(struct spi_device *spi)
1369 {
1370 	struct mrf24j40 *devrec = spi_get_drvdata(spi);
1371 
1372 	dev_dbg(printdev(devrec), "remove\n");
1373 
1374 	ieee802154_unregister_hw(devrec->hw);
1375 	ieee802154_free_hw(devrec->hw);
1376 	/* TODO: Will ieee802154_free_device() wait until ->xmit() is
1377 	 * complete? */
1378 
1379 	return 0;
1380 }
1381 
1382 static const struct of_device_id mrf24j40_of_match[] = {
1383 	{ .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1384 	{ .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1385 	{ .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1386 	{ },
1387 };
1388 MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1389 
1390 static const struct spi_device_id mrf24j40_ids[] = {
1391 	{ "mrf24j40", MRF24J40 },
1392 	{ "mrf24j40ma", MRF24J40MA },
1393 	{ "mrf24j40mc", MRF24J40MC },
1394 	{ },
1395 };
1396 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1397 
1398 static struct spi_driver mrf24j40_driver = {
1399 	.driver = {
1400 		.of_match_table = of_match_ptr(mrf24j40_of_match),
1401 		.name = "mrf24j40",
1402 	},
1403 	.id_table = mrf24j40_ids,
1404 	.probe = mrf24j40_probe,
1405 	.remove = mrf24j40_remove,
1406 };
1407 
1408 module_spi_driver(mrf24j40_driver);
1409 
1410 MODULE_LICENSE("GPL");
1411 MODULE_AUTHOR("Alan Ott");
1412 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
1413