11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28c6ad9ccSXue Liu /* 38c6ad9ccSXue Liu * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller 48c6ad9ccSXue Liu * 58c6ad9ccSXue Liu * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com> 68c6ad9ccSXue Liu */ 78c6ad9ccSXue Liu #ifndef _MCR20A_H 88c6ad9ccSXue Liu #define _MCR20A_H 98c6ad9ccSXue Liu 108c6ad9ccSXue Liu /* Direct Accress Register */ 118c6ad9ccSXue Liu #define DAR_IRQ_STS1 0x00 128c6ad9ccSXue Liu #define DAR_IRQ_STS2 0x01 138c6ad9ccSXue Liu #define DAR_IRQ_STS3 0x02 148c6ad9ccSXue Liu #define DAR_PHY_CTRL1 0x03 158c6ad9ccSXue Liu #define DAR_PHY_CTRL2 0x04 168c6ad9ccSXue Liu #define DAR_PHY_CTRL3 0x05 178c6ad9ccSXue Liu #define DAR_RX_FRM_LEN 0x06 188c6ad9ccSXue Liu #define DAR_PHY_CTRL4 0x07 198c6ad9ccSXue Liu #define DAR_SRC_CTRL 0x08 208c6ad9ccSXue Liu #define DAR_SRC_ADDRS_SUM_LSB 0x09 218c6ad9ccSXue Liu #define DAR_SRC_ADDRS_SUM_MSB 0x0A 228c6ad9ccSXue Liu #define DAR_CCA1_ED_FNL 0x0B 238c6ad9ccSXue Liu #define DAR_EVENT_TMR_LSB 0x0C 248c6ad9ccSXue Liu #define DAR_EVENT_TMR_MSB 0x0D 258c6ad9ccSXue Liu #define DAR_EVENT_TMR_USB 0x0E 268c6ad9ccSXue Liu #define DAR_TIMESTAMP_LSB 0x0F 278c6ad9ccSXue Liu #define DAR_TIMESTAMP_MSB 0x10 288c6ad9ccSXue Liu #define DAR_TIMESTAMP_USB 0x11 298c6ad9ccSXue Liu #define DAR_T3CMP_LSB 0x12 308c6ad9ccSXue Liu #define DAR_T3CMP_MSB 0x13 318c6ad9ccSXue Liu #define DAR_T3CMP_USB 0x14 328c6ad9ccSXue Liu #define DAR_T2PRIMECMP_LSB 0x15 338c6ad9ccSXue Liu #define DAR_T2PRIMECMP_MSB 0x16 348c6ad9ccSXue Liu #define DAR_T1CMP_LSB 0x17 358c6ad9ccSXue Liu #define DAR_T1CMP_MSB 0x18 368c6ad9ccSXue Liu #define DAR_T1CMP_USB 0x19 378c6ad9ccSXue Liu #define DAR_T2CMP_LSB 0x1A 388c6ad9ccSXue Liu #define DAR_T2CMP_MSB 0x1B 398c6ad9ccSXue Liu #define DAR_T2CMP_USB 0x1C 408c6ad9ccSXue Liu #define DAR_T4CMP_LSB 0x1D 418c6ad9ccSXue Liu #define DAR_T4CMP_MSB 0x1E 428c6ad9ccSXue Liu #define DAR_T4CMP_USB 0x1F 438c6ad9ccSXue Liu #define DAR_PLL_INT0 0x20 448c6ad9ccSXue Liu #define DAR_PLL_FRAC0_LSB 0x21 458c6ad9ccSXue Liu #define DAR_PLL_FRAC0_MSB 0x22 468c6ad9ccSXue Liu #define DAR_PA_PWR 0x23 478c6ad9ccSXue Liu #define DAR_SEQ_STATE 0x24 488c6ad9ccSXue Liu #define DAR_LQI_VALUE 0x25 498c6ad9ccSXue Liu #define DAR_RSSI_CCA_CONT 0x26 508c6ad9ccSXue Liu /*------------------ 0x27 */ 518c6ad9ccSXue Liu #define DAR_ASM_CTRL1 0x28 528c6ad9ccSXue Liu #define DAR_ASM_CTRL2 0x29 538c6ad9ccSXue Liu #define DAR_ASM_DATA_0 0x2A 548c6ad9ccSXue Liu #define DAR_ASM_DATA_1 0x2B 558c6ad9ccSXue Liu #define DAR_ASM_DATA_2 0x2C 568c6ad9ccSXue Liu #define DAR_ASM_DATA_3 0x2D 578c6ad9ccSXue Liu #define DAR_ASM_DATA_4 0x2E 588c6ad9ccSXue Liu #define DAR_ASM_DATA_5 0x2F 598c6ad9ccSXue Liu #define DAR_ASM_DATA_6 0x30 608c6ad9ccSXue Liu #define DAR_ASM_DATA_7 0x31 618c6ad9ccSXue Liu #define DAR_ASM_DATA_8 0x32 628c6ad9ccSXue Liu #define DAR_ASM_DATA_9 0x33 638c6ad9ccSXue Liu #define DAR_ASM_DATA_A 0x34 648c6ad9ccSXue Liu #define DAR_ASM_DATA_B 0x35 658c6ad9ccSXue Liu #define DAR_ASM_DATA_C 0x36 668c6ad9ccSXue Liu #define DAR_ASM_DATA_D 0x37 678c6ad9ccSXue Liu #define DAR_ASM_DATA_E 0x38 688c6ad9ccSXue Liu #define DAR_ASM_DATA_F 0x39 698c6ad9ccSXue Liu /*----------------------- 0x3A */ 708c6ad9ccSXue Liu #define DAR_OVERWRITE_VER 0x3B 718c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL 0x3C 728c6ad9ccSXue Liu #define DAR_PWR_MODES 0x3D 738c6ad9ccSXue Liu #define IAR_INDEX 0x3E 748c6ad9ccSXue Liu #define IAR_DATA 0x3F 758c6ad9ccSXue Liu 768c6ad9ccSXue Liu /* Indirect Resgister Memory */ 778c6ad9ccSXue Liu #define IAR_PART_ID 0x00 788c6ad9ccSXue Liu #define IAR_XTAL_TRIM 0x01 798c6ad9ccSXue Liu #define IAR_PMC_LP_TRIM 0x02 808c6ad9ccSXue Liu #define IAR_MACPANID0_LSB 0x03 818c6ad9ccSXue Liu #define IAR_MACPANID0_MSB 0x04 828c6ad9ccSXue Liu #define IAR_MACSHORTADDRS0_LSB 0x05 838c6ad9ccSXue Liu #define IAR_MACSHORTADDRS0_MSB 0x06 848c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_0 0x07 858c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_8 0x08 868c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_16 0x09 878c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_24 0x0A 888c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_32 0x0B 898c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_40 0x0C 908c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_48 0x0D 918c6ad9ccSXue Liu #define IAR_MACLONGADDRS0_56 0x0E 928c6ad9ccSXue Liu #define IAR_RX_FRAME_FILTER 0x0F 938c6ad9ccSXue Liu #define IAR_PLL_INT1 0x10 948c6ad9ccSXue Liu #define IAR_PLL_FRAC1_LSB 0x11 958c6ad9ccSXue Liu #define IAR_PLL_FRAC1_MSB 0x12 968c6ad9ccSXue Liu #define IAR_MACPANID1_LSB 0x13 978c6ad9ccSXue Liu #define IAR_MACPANID1_MSB 0x14 988c6ad9ccSXue Liu #define IAR_MACSHORTADDRS1_LSB 0x15 998c6ad9ccSXue Liu #define IAR_MACSHORTADDRS1_MSB 0x16 1008c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_0 0x17 1018c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_8 0x18 1028c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_16 0x19 1038c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_24 0x1A 1048c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_32 0x1B 1058c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_40 0x1C 1068c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_48 0x1D 1078c6ad9ccSXue Liu #define IAR_MACLONGADDRS1_56 0x1E 1088c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL 0x1F 1098c6ad9ccSXue Liu #define IAR_DUAL_PAN_DWELL 0x20 1108c6ad9ccSXue Liu #define IAR_DUAL_PAN_STS 0x21 1118c6ad9ccSXue Liu #define IAR_CCA1_THRESH 0x22 1128c6ad9ccSXue Liu #define IAR_CCA1_ED_OFFSET_COMP 0x23 1138c6ad9ccSXue Liu #define IAR_LQI_OFFSET_COMP 0x24 1148c6ad9ccSXue Liu #define IAR_CCA_CTRL 0x25 1158c6ad9ccSXue Liu #define IAR_CCA2_CORR_PEAKS 0x26 1168c6ad9ccSXue Liu #define IAR_CCA2_CORR_THRESH 0x27 1178c6ad9ccSXue Liu #define IAR_TMR_PRESCALE 0x28 1188c6ad9ccSXue Liu /*-------------------- 0x29 */ 1198c6ad9ccSXue Liu #define IAR_GPIO_DATA 0x2A 1208c6ad9ccSXue Liu #define IAR_GPIO_DIR 0x2B 1218c6ad9ccSXue Liu #define IAR_GPIO_PUL_EN 0x2C 1228c6ad9ccSXue Liu #define IAR_GPIO_PUL_SEL 0x2D 1238c6ad9ccSXue Liu #define IAR_GPIO_DS 0x2E 1248c6ad9ccSXue Liu /*------------------ 0x2F */ 1258c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL 0x30 1268c6ad9ccSXue Liu #define IAR_MISC_PAD_CTRL 0x31 1278c6ad9ccSXue Liu #define IAR_BSM_CTRL 0x32 1288c6ad9ccSXue Liu /*------------------- 0x33 */ 1298c6ad9ccSXue Liu #define IAR_RNG 0x34 1308c6ad9ccSXue Liu #define IAR_RX_BYTE_COUNT 0x35 1318c6ad9ccSXue Liu #define IAR_RX_WTR_MARK 0x36 1328c6ad9ccSXue Liu #define IAR_SOFT_RESET 0x37 1338c6ad9ccSXue Liu #define IAR_TXDELAY 0x38 1348c6ad9ccSXue Liu #define IAR_ACKDELAY 0x39 1358c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL 0x3A 1368c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS 0x3B 1378c6ad9ccSXue Liu #define IAR_SEQ_T_STS 0x3C 1388c6ad9ccSXue Liu #define IAR_ABORT_STS 0x3D 1398c6ad9ccSXue Liu #define IAR_CCCA_BUSY_CNT 0x3E 1408c6ad9ccSXue Liu #define IAR_SRC_ADDR_CHECKSUM1 0x3F 1418c6ad9ccSXue Liu #define IAR_SRC_ADDR_CHECKSUM2 0x40 1428c6ad9ccSXue Liu #define IAR_SRC_TBL_VALID1 0x41 1438c6ad9ccSXue Liu #define IAR_SRC_TBL_VALID2 0x42 1448c6ad9ccSXue Liu #define IAR_FILTERFAIL_CODE1 0x43 1458c6ad9ccSXue Liu #define IAR_FILTERFAIL_CODE2 0x44 1468c6ad9ccSXue Liu #define IAR_SLOT_PRELOAD 0x45 1478c6ad9ccSXue Liu /*-------------------- 0x46 */ 1488c6ad9ccSXue Liu #define IAR_CORR_VT 0x47 1498c6ad9ccSXue Liu #define IAR_SYNC_CTRL 0x48 1508c6ad9ccSXue Liu #define IAR_PN_LSB_0 0x49 1518c6ad9ccSXue Liu #define IAR_PN_LSB_1 0x4A 1528c6ad9ccSXue Liu #define IAR_PN_MSB_0 0x4B 1538c6ad9ccSXue Liu #define IAR_PN_MSB_1 0x4C 1548c6ad9ccSXue Liu #define IAR_CORR_NVAL 0x4D 1558c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL 0x4E 1568c6ad9ccSXue Liu #define IAR_SNF_THR 0x4F 1578c6ad9ccSXue Liu #define IAR_FAD_THR 0x50 1588c6ad9ccSXue Liu #define IAR_ANT_AGC_CTRL 0x51 1598c6ad9ccSXue Liu #define IAR_AGC_THR1 0x52 1608c6ad9ccSXue Liu #define IAR_AGC_THR2 0x53 1618c6ad9ccSXue Liu #define IAR_AGC_HYS 0x54 1628c6ad9ccSXue Liu #define IAR_AFC 0x55 1638c6ad9ccSXue Liu /*------------------- 0x56 */ 1648c6ad9ccSXue Liu /*------------------- 0x57 */ 1658c6ad9ccSXue Liu #define IAR_PHY_STS 0x58 1668c6ad9ccSXue Liu #define IAR_RX_MAX_CORR 0x59 1678c6ad9ccSXue Liu #define IAR_RX_MAX_PREAMBLE 0x5A 1688c6ad9ccSXue Liu #define IAR_RSSI 0x5B 1698c6ad9ccSXue Liu /*------------------- 0x5C */ 1708c6ad9ccSXue Liu /*------------------- 0x5D */ 1718c6ad9ccSXue Liu #define IAR_PLL_DIG_CTRL 0x5E 1728c6ad9ccSXue Liu #define IAR_VCO_CAL 0x5F 1738c6ad9ccSXue Liu #define IAR_VCO_BEST_DIFF 0x60 1748c6ad9ccSXue Liu #define IAR_VCO_BIAS 0x61 1758c6ad9ccSXue Liu #define IAR_KMOD_CTRL 0x62 1768c6ad9ccSXue Liu #define IAR_KMOD_CAL 0x63 1778c6ad9ccSXue Liu #define IAR_PA_CAL 0x64 1788c6ad9ccSXue Liu #define IAR_PA_PWRCAL 0x65 1798c6ad9ccSXue Liu #define IAR_ATT_RSSI1 0x66 1808c6ad9ccSXue Liu #define IAR_ATT_RSSI2 0x67 1818c6ad9ccSXue Liu #define IAR_RSSI_OFFSET 0x68 1828c6ad9ccSXue Liu #define IAR_RSSI_SLOPE 0x69 1838c6ad9ccSXue Liu #define IAR_RSSI_CAL1 0x6A 1848c6ad9ccSXue Liu #define IAR_RSSI_CAL2 0x6B 1858c6ad9ccSXue Liu /*------------------- 0x6C */ 1868c6ad9ccSXue Liu /*------------------- 0x6D */ 1878c6ad9ccSXue Liu #define IAR_XTAL_CTRL 0x6E 1888c6ad9ccSXue Liu #define IAR_XTAL_COMP_MIN 0x6F 1898c6ad9ccSXue Liu #define IAR_XTAL_COMP_MAX 0x70 1908c6ad9ccSXue Liu #define IAR_XTAL_GM 0x71 1918c6ad9ccSXue Liu /*------------------- 0x72 */ 1928c6ad9ccSXue Liu /*------------------- 0x73 */ 1938c6ad9ccSXue Liu #define IAR_LNA_TUNE 0x74 1948c6ad9ccSXue Liu #define IAR_LNA_AGCGAIN 0x75 1958c6ad9ccSXue Liu /*------------------- 0x76 */ 1968c6ad9ccSXue Liu /*------------------- 0x77 */ 1978c6ad9ccSXue Liu #define IAR_CHF_PMA_GAIN 0x78 1988c6ad9ccSXue Liu #define IAR_CHF_IBUF 0x79 1998c6ad9ccSXue Liu #define IAR_CHF_QBUF 0x7A 2008c6ad9ccSXue Liu #define IAR_CHF_IRIN 0x7B 2018c6ad9ccSXue Liu #define IAR_CHF_QRIN 0x7C 2028c6ad9ccSXue Liu #define IAR_CHF_IL 0x7D 2038c6ad9ccSXue Liu #define IAR_CHF_QL 0x7E 2048c6ad9ccSXue Liu #define IAR_CHF_CC1 0x7F 2058c6ad9ccSXue Liu #define IAR_CHF_CCL 0x80 2068c6ad9ccSXue Liu #define IAR_CHF_CC2 0x81 2078c6ad9ccSXue Liu #define IAR_CHF_IROUT 0x82 2088c6ad9ccSXue Liu #define IAR_CHF_QROUT 0x83 2098c6ad9ccSXue Liu /*------------------- 0x84 */ 2108c6ad9ccSXue Liu /*------------------- 0x85 */ 2118c6ad9ccSXue Liu #define IAR_RSSI_CTRL 0x86 2128c6ad9ccSXue Liu /*------------------- 0x87 */ 2138c6ad9ccSXue Liu /*------------------- 0x88 */ 2148c6ad9ccSXue Liu #define IAR_PA_BIAS 0x89 2158c6ad9ccSXue Liu #define IAR_PA_TUNING 0x8A 2168c6ad9ccSXue Liu /*------------------- 0x8B */ 2178c6ad9ccSXue Liu /*------------------- 0x8C */ 2188c6ad9ccSXue Liu #define IAR_PMC_HP_TRIM 0x8D 2198c6ad9ccSXue Liu #define IAR_VREGA_TRIM 0x8E 2208c6ad9ccSXue Liu /*------------------- 0x8F */ 2218c6ad9ccSXue Liu /*------------------- 0x90 */ 2228c6ad9ccSXue Liu #define IAR_VCO_CTRL1 0x91 2238c6ad9ccSXue Liu #define IAR_VCO_CTRL2 0x92 2248c6ad9ccSXue Liu /*------------------- 0x93 */ 2258c6ad9ccSXue Liu /*------------------- 0x94 */ 2268c6ad9ccSXue Liu #define IAR_ANA_SPARE_OUT1 0x95 2278c6ad9ccSXue Liu #define IAR_ANA_SPARE_OUT2 0x96 2288c6ad9ccSXue Liu #define IAR_ANA_SPARE_IN 0x97 2298c6ad9ccSXue Liu #define IAR_MISCELLANEOUS 0x98 2308c6ad9ccSXue Liu /*------------------- 0x99 */ 2318c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD0 0x9A 2328c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD1 0x9B 2338c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD2 0x9C 2348c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD3 0x9D 2358c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD4 0x9E 2368c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD5 0x9F 2378c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD6 0xA0 2388c6ad9ccSXue Liu #define IAR_SEQ_MGR_OVRD7 0xA1 2398c6ad9ccSXue Liu /*------------------- 0xA2 */ 2408c6ad9ccSXue Liu #define IAR_TESTMODE_CTRL 0xA3 2418c6ad9ccSXue Liu #define IAR_DTM_CTRL1 0xA4 2428c6ad9ccSXue Liu #define IAR_DTM_CTRL2 0xA5 2438c6ad9ccSXue Liu #define IAR_ATM_CTRL1 0xA6 2448c6ad9ccSXue Liu #define IAR_ATM_CTRL2 0xA7 2458c6ad9ccSXue Liu #define IAR_ATM_CTRL3 0xA8 2468c6ad9ccSXue Liu /*------------------- 0xA9 */ 2478c6ad9ccSXue Liu #define IAR_LIM_FE_TEST_CTRL 0xAA 2488c6ad9ccSXue Liu #define IAR_CHF_TEST_CTRL 0xAB 2498c6ad9ccSXue Liu #define IAR_VCO_TEST_CTRL 0xAC 2508c6ad9ccSXue Liu #define IAR_PLL_TEST_CTRL 0xAD 2518c6ad9ccSXue Liu #define IAR_PA_TEST_CTRL 0xAE 2528c6ad9ccSXue Liu #define IAR_PMC_TEST_CTRL 0xAF 2538c6ad9ccSXue Liu #define IAR_SCAN_DTM_PROTECT_1 0xFE 2548c6ad9ccSXue Liu #define IAR_SCAN_DTM_PROTECT_0 0xFF 2558c6ad9ccSXue Liu 2568c6ad9ccSXue Liu /* IRQSTS1 bits */ 2578c6ad9ccSXue Liu #define DAR_IRQSTS1_RX_FRM_PEND BIT(7) 2588c6ad9ccSXue Liu #define DAR_IRQSTS1_PLL_UNLOCK_IRQ BIT(6) 2598c6ad9ccSXue Liu #define DAR_IRQSTS1_FILTERFAIL_IRQ BIT(5) 2608c6ad9ccSXue Liu #define DAR_IRQSTS1_RXWTRMRKIRQ BIT(4) 2618c6ad9ccSXue Liu #define DAR_IRQSTS1_CCAIRQ BIT(3) 2628c6ad9ccSXue Liu #define DAR_IRQSTS1_RXIRQ BIT(2) 2638c6ad9ccSXue Liu #define DAR_IRQSTS1_TXIRQ BIT(1) 2648c6ad9ccSXue Liu #define DAR_IRQSTS1_SEQIRQ BIT(0) 2658c6ad9ccSXue Liu 2668c6ad9ccSXue Liu /* IRQSTS2 bits */ 2678c6ad9ccSXue Liu #define DAR_IRQSTS2_CRCVALID BIT(7) 2688c6ad9ccSXue Liu #define DAR_IRQSTS2_CCA BIT(6) 2698c6ad9ccSXue Liu #define DAR_IRQSTS2_SRCADDR BIT(5) 2708c6ad9ccSXue Liu #define DAR_IRQSTS2_PI BIT(4) 2718c6ad9ccSXue Liu #define DAR_IRQSTS2_TMRSTATUS BIT(3) 2728c6ad9ccSXue Liu #define DAR_IRQSTS2_ASM_IRQ BIT(2) 2738c6ad9ccSXue Liu #define DAR_IRQSTS2_PB_ERR_IRQ BIT(1) 2748c6ad9ccSXue Liu #define DAR_IRQSTS2_WAKE_IRQ BIT(0) 2758c6ad9ccSXue Liu 2768c6ad9ccSXue Liu /* IRQSTS3 bits */ 2778c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR4MSK BIT(7) 2788c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR3MSK BIT(6) 2798c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR2MSK BIT(5) 2808c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR1MSK BIT(4) 2818c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR4IRQ BIT(3) 2828c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR3IRQ BIT(2) 2838c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR2IRQ BIT(1) 2848c6ad9ccSXue Liu #define DAR_IRQSTS3_TMR1IRQ BIT(0) 2858c6ad9ccSXue Liu 2868c6ad9ccSXue Liu /* PHY_CTRL1 bits */ 2878c6ad9ccSXue Liu #define DAR_PHY_CTRL1_TMRTRIGEN BIT(7) 2888c6ad9ccSXue Liu #define DAR_PHY_CTRL1_SLOTTED BIT(6) 2898c6ad9ccSXue Liu #define DAR_PHY_CTRL1_CCABFRTX BIT(5) 2908c6ad9ccSXue Liu #define DAR_PHY_CTRL1_CCABFRTX_SHIFT 5 2918c6ad9ccSXue Liu #define DAR_PHY_CTRL1_RXACKRQD BIT(4) 2928c6ad9ccSXue Liu #define DAR_PHY_CTRL1_AUTOACK BIT(3) 2938c6ad9ccSXue Liu #define DAR_PHY_CTRL1_XCVSEQ_MASK 0x07 2948c6ad9ccSXue Liu 2958c6ad9ccSXue Liu /* PHY_CTRL2 bits */ 2968c6ad9ccSXue Liu #define DAR_PHY_CTRL2_CRC_MSK BIT(7) 2978c6ad9ccSXue Liu #define DAR_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6) 2988c6ad9ccSXue Liu #define DAR_PHY_CTRL2_FILTERFAIL_MSK BIT(5) 2998c6ad9ccSXue Liu #define DAR_PHY_CTRL2_RX_WMRK_MSK BIT(4) 3008c6ad9ccSXue Liu #define DAR_PHY_CTRL2_CCAMSK BIT(3) 3018c6ad9ccSXue Liu #define DAR_PHY_CTRL2_RXMSK BIT(2) 3028c6ad9ccSXue Liu #define DAR_PHY_CTRL2_TXMSK BIT(1) 3038c6ad9ccSXue Liu #define DAR_PHY_CTRL2_SEQMSK BIT(0) 3048c6ad9ccSXue Liu 3058c6ad9ccSXue Liu /* PHY_CTRL3 bits */ 3068c6ad9ccSXue Liu #define DAR_PHY_CTRL3_TMR4CMP_EN BIT(7) 3078c6ad9ccSXue Liu #define DAR_PHY_CTRL3_TMR3CMP_EN BIT(6) 3088c6ad9ccSXue Liu #define DAR_PHY_CTRL3_TMR2CMP_EN BIT(5) 3098c6ad9ccSXue Liu #define DAR_PHY_CTRL3_TMR1CMP_EN BIT(4) 3108c6ad9ccSXue Liu #define DAR_PHY_CTRL3_ASM_MSK BIT(2) 3118c6ad9ccSXue Liu #define DAR_PHY_CTRL3_PB_ERR_MSK BIT(1) 3128c6ad9ccSXue Liu #define DAR_PHY_CTRL3_WAKE_MSK BIT(0) 3138c6ad9ccSXue Liu 3148c6ad9ccSXue Liu /* RX_FRM_LEN bits */ 3158c6ad9ccSXue Liu #define DAR_RX_FRAME_LENGTH_MASK (0x7F) 3168c6ad9ccSXue Liu 3178c6ad9ccSXue Liu /* PHY_CTRL4 bits */ 3188c6ad9ccSXue Liu #define DAR_PHY_CTRL4_TRCV_MSK BIT(7) 3198c6ad9ccSXue Liu #define DAR_PHY_CTRL4_TC3TMOUT BIT(6) 3208c6ad9ccSXue Liu #define DAR_PHY_CTRL4_PANCORDNTR0 BIT(5) 3218c6ad9ccSXue Liu #define DAR_PHY_CTRL4_CCATYPE (3) 3228c6ad9ccSXue Liu #define DAR_PHY_CTRL4_CCATYPE_SHIFT (3) 3238c6ad9ccSXue Liu #define DAR_PHY_CTRL4_CCATYPE_MASK (0x18) 3248c6ad9ccSXue Liu #define DAR_PHY_CTRL4_TMRLOAD BIT(2) 3258c6ad9ccSXue Liu #define DAR_PHY_CTRL4_PROMISCUOUS BIT(1) 3268c6ad9ccSXue Liu #define DAR_PHY_CTRL4_TC2PRIME_EN BIT(0) 3278c6ad9ccSXue Liu 3288c6ad9ccSXue Liu /* SRC_CTRL bits */ 3298c6ad9ccSXue Liu #define DAR_SRC_CTRL_INDEX (0x0F) 3308c6ad9ccSXue Liu #define DAR_SRC_CTRL_INDEX_SHIFT (4) 3318c6ad9ccSXue Liu #define DAR_SRC_CTRL_ACK_FRM_PND BIT(3) 3328c6ad9ccSXue Liu #define DAR_SRC_CTRL_SRCADDR_EN BIT(2) 3338c6ad9ccSXue Liu #define DAR_SRC_CTRL_INDEX_EN BIT(1) 3348c6ad9ccSXue Liu #define DAR_SRC_CTRL_INDEX_DISABLE BIT(0) 3358c6ad9ccSXue Liu 3368c6ad9ccSXue Liu /* DAR_ASM_CTRL1 bits */ 3378c6ad9ccSXue Liu #define DAR_ASM_CTRL1_CLEAR BIT(7) 3388c6ad9ccSXue Liu #define DAR_ASM_CTRL1_START BIT(6) 3398c6ad9ccSXue Liu #define DAR_ASM_CTRL1_SELFTST BIT(5) 3408c6ad9ccSXue Liu #define DAR_ASM_CTRL1_CTR BIT(4) 3418c6ad9ccSXue Liu #define DAR_ASM_CTRL1_CBC BIT(3) 3428c6ad9ccSXue Liu #define DAR_ASM_CTRL1_AES BIT(2) 3438c6ad9ccSXue Liu #define DAR_ASM_CTRL1_LOAD_MAC BIT(1) 3448c6ad9ccSXue Liu 3458c6ad9ccSXue Liu /* DAR_ASM_CTRL2 bits */ 3468c6ad9ccSXue Liu #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL (7) 3478c6ad9ccSXue Liu #define DAR_ASM_CTRL2_DATA_REG_TYPE_SEL_SHIFT (5) 3488c6ad9ccSXue Liu #define DAR_ASM_CTRL2_TSTPAS BIT(1) 3498c6ad9ccSXue Liu 3508c6ad9ccSXue Liu /* DAR_CLK_OUT_CTRL bits */ 3518c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_EXTEND BIT(7) 3528c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_HIZ BIT(6) 3538c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_SR BIT(5) 3548c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_DS BIT(4) 3558c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_EN BIT(3) 3568c6ad9ccSXue Liu #define DAR_CLK_OUT_CTRL_DIV (7) 3578c6ad9ccSXue Liu 3588c6ad9ccSXue Liu /* DAR_PWR_MODES bits */ 3598c6ad9ccSXue Liu #define DAR_PWR_MODES_XTAL_READY BIT(5) 3608c6ad9ccSXue Liu #define DAR_PWR_MODES_XTALEN BIT(4) 3618c6ad9ccSXue Liu #define DAR_PWR_MODES_ASM_CLK_EN BIT(3) 3628c6ad9ccSXue Liu #define DAR_PWR_MODES_AUTODOZE BIT(1) 3638c6ad9ccSXue Liu #define DAR_PWR_MODES_PMC_MODE BIT(0) 3648c6ad9ccSXue Liu 3658c6ad9ccSXue Liu /* RX_FRAME_FILTER bits */ 3668c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_FRM_VER (0xC0) 3678c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_FRM_VER_SHIFT (6) 3688c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS BIT(5) 3698c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_NS_FT BIT(4) 3708c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_CMD_FT BIT(3) 3718c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_ACK_FT BIT(2) 3728c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_DATA_FT BIT(1) 3738c6ad9ccSXue Liu #define IAR_RX_FRAME_FLT_BEACON_FT BIT(0) 3748c6ad9ccSXue Liu 3758c6ad9ccSXue Liu /* DUAL_PAN_CTRL bits */ 3768c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0) 3778c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4) 3788c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3) 3798c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2) 3808c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1) 3818c6ad9ccSXue Liu #define IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0) 3828c6ad9ccSXue Liu 3838c6ad9ccSXue Liu /* DUAL_PAN_STS bits */ 3848c6ad9ccSXue Liu #define IAR_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7) 3858c6ad9ccSXue Liu #define IAR_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6) 3868c6ad9ccSXue Liu #define IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F) 3878c6ad9ccSXue Liu 3888c6ad9ccSXue Liu /* CCA_CTRL bits */ 3898c6ad9ccSXue Liu #define IAR_CCA_CTRL_AGC_FRZ_EN BIT(6) 3908c6ad9ccSXue Liu #define IAR_CCA_CTRL_CONT_RSSI_EN BIT(5) 3918c6ad9ccSXue Liu #define IAR_CCA_CTRL_LQI_RSSI_NOT_CORR BIT(4) 3928c6ad9ccSXue Liu #define IAR_CCA_CTRL_CCA3_AND_NOT_OR BIT(3) 3938c6ad9ccSXue Liu #define IAR_CCA_CTRL_POWER_COMP_EN_LQI BIT(2) 3948c6ad9ccSXue Liu #define IAR_CCA_CTRL_POWER_COMP_EN_ED BIT(1) 3958c6ad9ccSXue Liu #define IAR_CCA_CTRL_POWER_COMP_EN_CCA1 BIT(0) 3968c6ad9ccSXue Liu 3978c6ad9ccSXue Liu /* ANT_PAD_CTRL bits */ 3988c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL_ANTX_POL (0x0F) 3998c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT (4) 4008c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3) 4018c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL_ANTX_HZ BIT(2) 4028c6ad9ccSXue Liu #define IAR_ANT_PAD_CTRL_ANTX_EN (3) 4038c6ad9ccSXue Liu 4048c6ad9ccSXue Liu /* MISC_PAD_CTRL bits */ 4058c6ad9ccSXue Liu #define IAR_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3) 4068c6ad9ccSXue Liu #define IAR_MISC_PAD_CTRL_IRQ_B_OD BIT(2) 4078c6ad9ccSXue Liu #define IAR_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) 4088c6ad9ccSXue Liu #define IAR_MISC_PAD_CTRL_ANTX_CURR (1) 4098c6ad9ccSXue Liu 4108c6ad9ccSXue Liu /* ANT_AGC_CTRL bits */ 4118c6ad9ccSXue Liu #define IAR_ANT_AGC_CTRL_FAD_EN_SHIFT (0) 4128c6ad9ccSXue Liu #define IAR_ANT_AGC_CTRL_FAD_EN_MASK (1) 4138c6ad9ccSXue Liu #define IAR_ANT_AGC_CTRL_ANTX_SHIFT (1) 4148c6ad9ccSXue Liu #define IAR_ANT_AGC_CTRL_ANTX_MASK BIT(AR_ANT_AGC_CTRL_ANTX_SHIFT) 4158c6ad9ccSXue Liu 4168c6ad9ccSXue Liu /* BSM_CTRL bits */ 4178c6ad9ccSXue Liu #define BSM_CTRL_BSM_EN (1) 4188c6ad9ccSXue Liu 4198c6ad9ccSXue Liu /* SOFT_RESET bits */ 4208c6ad9ccSXue Liu #define IAR_SOFT_RESET_SOG_RST BIT(7) 4218c6ad9ccSXue Liu #define IAR_SOFT_RESET_REGS_RST BIT(4) 4228c6ad9ccSXue Liu #define IAR_SOFT_RESET_PLL_RST BIT(3) 4238c6ad9ccSXue Liu #define IAR_SOFT_RESET_TX_RST BIT(2) 4248c6ad9ccSXue Liu #define IAR_SOFT_RESET_RX_RST BIT(1) 4258c6ad9ccSXue Liu #define IAR_SOFT_RESET_SEQ_MGR_RST BIT(0) 4268c6ad9ccSXue Liu 4278c6ad9ccSXue Liu /* SEQ_MGR_CTRL bits */ 4288c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL (3) 4298c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6) 4308c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5) 4318c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4) 4328c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3) 4338c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2) 4348c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1) 4358c6ad9ccSXue Liu #define IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0) 4368c6ad9ccSXue Liu 4378c6ad9ccSXue Liu /* SEQ_MGR_STS bits */ 4388c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7) 4398c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_RX_MODE BIT(6) 4408c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5) 4418c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4) 4428c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_SEQ_IDLE BIT(3) 4438c6ad9ccSXue Liu #define IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL (7) 4448c6ad9ccSXue Liu 4458c6ad9ccSXue Liu /* ABORT_STS bits */ 4468c6ad9ccSXue Liu #define IAR_ABORT_STS_PLL_ABORTED BIT(2) 4478c6ad9ccSXue Liu #define IAR_ABORT_STS_TC3_ABORTED BIT(1) 4488c6ad9ccSXue Liu #define IAR_ABORT_STS_SW_ABORTED BIT(0) 4498c6ad9ccSXue Liu 4508c6ad9ccSXue Liu /* IAR_FILTERFAIL_CODE2 bits */ 4518c6ad9ccSXue Liu #define IAR_FILTERFAIL_CODE2_PAN_SEL BIT(7) 4528c6ad9ccSXue Liu #define IAR_FILTERFAIL_CODE2_9_8 (3) 4538c6ad9ccSXue Liu 4548c6ad9ccSXue Liu /* PHY_STS bits */ 4558c6ad9ccSXue Liu #define IAR_PHY_STS_PLL_UNLOCK BIT(7) 4568c6ad9ccSXue Liu #define IAR_PHY_STS_PLL_LOCK_ERR BIT(6) 4578c6ad9ccSXue Liu #define IAR_PHY_STS_PLL_LOCK BIT(5) 4588c6ad9ccSXue Liu #define IAR_PHY_STS_CRCVALID BIT(3) 4598c6ad9ccSXue Liu #define IAR_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2) 4608c6ad9ccSXue Liu #define IAR_PHY_STS_SFD_DET BIT(1) 4618c6ad9ccSXue Liu #define IAR_PHY_STS_PREAMBLE_DET BIT(0) 4628c6ad9ccSXue Liu 4638c6ad9ccSXue Liu /* TESTMODE_CTRL bits */ 4648c6ad9ccSXue Liu #define IAR_TEST_MODE_CTRL_HOT_ANT BIT(4) 4658c6ad9ccSXue Liu #define IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN BIT(3) 4668c6ad9ccSXue Liu #define IAR_TEST_MODE_CTRL_IDEAL_PFC_EN BIT(2) 4678c6ad9ccSXue Liu #define IAR_TEST_MODE_CTRL_CONTINUOUS_EN BIT(1) 4688c6ad9ccSXue Liu #define IAR_TEST_MODE_CTRL_FPGA_EN BIT(0) 4698c6ad9ccSXue Liu 4708c6ad9ccSXue Liu /* DTM_CTRL1 bits */ 4718c6ad9ccSXue Liu #define IAR_DTM_CTRL1_ATM_LOCKED BIT(7) 4728c6ad9ccSXue Liu #define IAR_DTM_CTRL1_DTM_EN BIT(6) 4738c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE5 BIT(5) 4748c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE4 BIT(4) 4758c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE3 BIT(3) 4768c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE2 BIT(2) 4778c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE1 BIT(1) 4788c6ad9ccSXue Liu #define IAR_DTM_CTRL1_PAGE0 BIT(0) 4798c6ad9ccSXue Liu 4808c6ad9ccSXue Liu /* TX_MODE_CTRL */ 4818c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL_TX_INV BIT(4) 4828c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL_BT_EN BIT(3) 4838c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL_DTS2 BIT(2) 4848c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL_DTS1 BIT(1) 4858c6ad9ccSXue Liu #define IAR_TX_MODE_CTRL_DTS0 BIT(0) 4868c6ad9ccSXue Liu 4878c6ad9ccSXue Liu #define TX_MODE_CTRL_DTS_MASK (7) 4888c6ad9ccSXue Liu 4898c6ad9ccSXue Liu #endif /* _MCR20A_H */ 490