1 /* 2 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver 3 * 4 * Copyright 2009-2017 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 * 8 * http://www.analog.com/ADF7242 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/delay.h> 15 #include <linux/mutex.h> 16 #include <linux/workqueue.h> 17 #include <linux/spinlock.h> 18 #include <linux/firmware.h> 19 #include <linux/spi/spi.h> 20 #include <linux/skbuff.h> 21 #include <linux/of.h> 22 #include <linux/irq.h> 23 #include <linux/debugfs.h> 24 #include <linux/bitops.h> 25 #include <linux/ieee802154.h> 26 #include <net/mac802154.h> 27 #include <net/cfg802154.h> 28 29 #define FIRMWARE "adf7242_firmware.bin" 30 #define MAX_POLL_LOOPS 200 31 32 /* All Registers */ 33 34 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */ 35 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */ 36 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */ 37 #define REG_CCA2 0x106 /* RW CCA mode configuration */ 38 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */ 39 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */ 40 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */ 41 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */ 42 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */ 43 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */ 44 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */ 45 #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */ 46 #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */ 47 #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */ 48 #define REG_RC_VAR44 0x13F /* RW RESERVED */ 49 #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */ 50 #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */ 51 #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */ 52 #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */ 53 #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */ 54 #define REG_TX_M 0x306 /* RW TX Mode Register */ 55 #define REG_RX_M 0x307 /* RW RX Mode Register */ 56 #define REG_RRB 0x30C /* R RSSI Readback Register */ 57 #define REG_LRB 0x30D /* R Link Quality Readback Register */ 58 #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */ 59 #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */ 60 #define REG_PRAMPG 0x313 /* RW RESERVED */ 61 #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */ 62 #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */ 63 #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */ 64 #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */ 65 #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */ 66 #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */ 67 #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */ 68 #define REG_PD_AUX 0x31E /* RW Battmon enable */ 69 #define REG_GP_CFG 0x32C /* RW GPIO Configuration */ 70 #define REG_GP_OUT 0x32D /* RW GPIO Configuration */ 71 #define REG_GP_IN 0x32E /* R GPIO Configuration */ 72 #define REG_SYNT 0x335 /* RW bandwidth calibration timers */ 73 #define REG_CAL_CFG 0x33D /* RW Calibration Settings */ 74 #define REG_PA_BIAS 0x36E /* RW PA BIAS */ 75 #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */ 76 #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */ 77 #define REG_CDR_CFG 0x38A /* RW CDR kVCO */ 78 #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */ 79 #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */ 80 #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */ 81 #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */ 82 #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */ 83 #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */ 84 #define REG_PA_CFG 0x3A8 /* RW PA enable */ 85 #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */ 86 #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */ 87 #define REG_ADC_RBK 0x3AE /* R Readback temp */ 88 #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */ 89 #define REG_AGC_MAX 0x3B4 /* RW Slew rate */ 90 #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */ 91 #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */ 92 #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */ 93 #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */ 94 #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */ 95 #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */ 96 #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */ 97 #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */ 98 #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */ 99 #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */ 100 #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */ 101 #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */ 102 #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */ 103 #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */ 104 #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */ 105 #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */ 106 #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */ 107 #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */ 108 #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */ 109 #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */ 110 #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */ 111 #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */ 112 #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */ 113 #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */ 114 #define REG_AFC_RANGE 0x3F9 /* RW AFC range */ 115 #define REG_AFC_READ 0x3FA /* RW Readback frequency error */ 116 117 /* REG_EXTPA_MSC */ 118 #define PA_PWR(x) (((x) & 0xF) << 4) 119 #define EXTPA_BIAS_SRC BIT(3) 120 #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0) 121 122 /* REG_PA_CFG */ 123 #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0) 124 #define PA_DBIAS_HIGH_POWER 21 125 #define PA_DBIAS_LOW_POWER 13 126 127 /* REG_PA_BIAS */ 128 #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1) 129 #define REG_PA_BIAS_DFL BIT(0) 130 #define PA_BIAS_HIGH_POWER 63 131 #define PA_BIAS_LOW_POWER 55 132 133 #define REG_PAN_ID0 0x112 134 #define REG_PAN_ID1 0x113 135 #define REG_SHORT_ADDR_0 0x114 136 #define REG_SHORT_ADDR_1 0x115 137 #define REG_IEEE_ADDR_0 0x116 138 #define REG_IEEE_ADDR_1 0x117 139 #define REG_IEEE_ADDR_2 0x118 140 #define REG_IEEE_ADDR_3 0x119 141 #define REG_IEEE_ADDR_4 0x11A 142 #define REG_IEEE_ADDR_5 0x11B 143 #define REG_IEEE_ADDR_6 0x11C 144 #define REG_IEEE_ADDR_7 0x11D 145 #define REG_FFILT_CFG 0x11E 146 #define REG_AUTO_CFG 0x11F 147 #define REG_AUTO_TX1 0x120 148 #define REG_AUTO_TX2 0x121 149 #define REG_AUTO_STATUS 0x122 150 151 /* REG_FFILT_CFG */ 152 #define ACCEPT_BEACON_FRAMES BIT(0) 153 #define ACCEPT_DATA_FRAMES BIT(1) 154 #define ACCEPT_ACK_FRAMES BIT(2) 155 #define ACCEPT_MACCMD_FRAMES BIT(3) 156 #define ACCEPT_RESERVED_FRAMES BIT(4) 157 #define ACCEPT_ALL_ADDRESS BIT(5) 158 159 /* REG_AUTO_CFG */ 160 #define AUTO_ACK_FRAMEPEND BIT(0) 161 #define IS_PANCOORD BIT(1) 162 #define RX_AUTO_ACK_EN BIT(3) 163 #define CSMA_CA_RX_TURNAROUND BIT(4) 164 165 /* REG_AUTO_TX1 */ 166 #define MAX_FRAME_RETRIES(x) ((x) & 0xF) 167 #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4) 168 169 /* REG_AUTO_TX2 */ 170 #define CSMA_MAX_BE(x) ((x) & 0xF) 171 #define CSMA_MIN_BE(x) (((x) & 0xF) << 4) 172 173 #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */ 174 #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM 175 * starting from the TX packet base address 176 * pointer tx_packet_base 177 */ 178 #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM 179 * starting from RX packet base address 180 * pointer rxpb.rx_packet_base 181 */ 182 #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or 183 * Packet RAM sequentially 184 */ 185 #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or 186 * Packet RAM sequentially 187 */ 188 #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet 189 * RAM as random block 190 */ 191 #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or 192 * Packet RAM random block 193 */ 194 #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current 195 * PRAM page selected 196 */ 197 #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current 198 * PRAM page selected 199 */ 200 #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller 201 * into SLEEP state 202 */ 203 #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller 204 * into IDLE state 205 */ 206 #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller 207 * into PHY_RDY state 208 */ 209 #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller 210 * into RX state 211 */ 212 #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller 213 * into TX state 214 */ 215 #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller 216 * into MEAS state 217 */ 218 #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */ 219 #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access 220 * sequence and frame transmission 221 */ 222 #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */ 223 #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in 224 * the sleep state 225 */ 226 #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31)) 227 228 /* STATUS */ 229 230 #define STAT_SPI_READY BIT(7) 231 #define STAT_IRQ_STATUS BIT(6) 232 #define STAT_RC_READY BIT(5) 233 #define STAT_CCA_RESULT BIT(4) 234 #define RC_STATUS_IDLE 1 235 #define RC_STATUS_MEAS 2 236 #define RC_STATUS_PHY_RDY 3 237 #define RC_STATUS_RX 4 238 #define RC_STATUS_TX 5 239 #define RC_STATUS_MASK 0xF 240 241 /* AUTO_STATUS */ 242 243 #define SUCCESS 0 244 #define SUCCESS_DATPEND 1 245 #define FAILURE_CSMACA 2 246 #define FAILURE_NOACK 3 247 #define AUTO_STATUS_MASK 0x3 248 249 #define PRAM_PAGESIZE 256 250 251 /* IRQ1 */ 252 253 #define IRQ_CCA_COMPLETE BIT(0) 254 #define IRQ_SFD_RX BIT(1) 255 #define IRQ_SFD_TX BIT(2) 256 #define IRQ_RX_PKT_RCVD BIT(3) 257 #define IRQ_TX_PKT_SENT BIT(4) 258 #define IRQ_FRAME_VALID BIT(5) 259 #define IRQ_ADDRESS_VALID BIT(6) 260 #define IRQ_CSMA_CA BIT(7) 261 262 #define AUTO_TX_TURNAROUND BIT(3) 263 #define ADDON_EN BIT(4) 264 265 #define FLAG_XMIT 0 266 #define FLAG_START 1 267 268 #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */ 269 270 struct adf7242_local { 271 struct spi_device *spi; 272 struct completion tx_complete; 273 struct ieee802154_hw *hw; 274 struct mutex bmux; /* protect SPI messages */ 275 struct spi_message stat_msg; 276 struct spi_transfer stat_xfer; 277 struct dentry *debugfs_root; 278 unsigned long flags; 279 int tx_stat; 280 bool promiscuous; 281 s8 rssi; 282 u8 max_frame_retries; 283 u8 max_cca_retries; 284 u8 max_be; 285 u8 min_be; 286 287 /* DMA (thus cache coherency maintenance) requires the 288 * transfer buffers to live in their own cache lines. 289 */ 290 291 u8 buf[3] ____cacheline_aligned; 292 u8 buf_reg_tx[3]; 293 u8 buf_read_tx[4]; 294 u8 buf_read_rx[4]; 295 u8 buf_stat_rx; 296 u8 buf_stat_tx; 297 u8 buf_cmd; 298 }; 299 300 static int adf7242_soft_reset(struct adf7242_local *lp, int line); 301 302 static int adf7242_status(struct adf7242_local *lp, u8 *stat) 303 { 304 int status; 305 306 mutex_lock(&lp->bmux); 307 status = spi_sync(lp->spi, &lp->stat_msg); 308 *stat = lp->buf_stat_rx; 309 mutex_unlock(&lp->bmux); 310 311 return status; 312 } 313 314 static int adf7242_wait_status(struct adf7242_local *lp, unsigned int status, 315 unsigned int mask, int line) 316 { 317 int cnt = 0, ret = 0; 318 u8 stat; 319 320 do { 321 adf7242_status(lp, &stat); 322 cnt++; 323 } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS)); 324 325 if (cnt >= MAX_POLL_LOOPS) { 326 ret = -ETIMEDOUT; 327 328 if (!(stat & STAT_RC_READY)) { 329 adf7242_soft_reset(lp, line); 330 adf7242_status(lp, &stat); 331 332 if ((stat & mask) == status) 333 ret = 0; 334 } 335 336 if (ret < 0) 337 dev_warn(&lp->spi->dev, 338 "%s:line %d Timeout status 0x%x (%d)\n", 339 __func__, line, stat, cnt); 340 } 341 342 dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line); 343 344 return ret; 345 } 346 347 static int adf7242_wait_rc_ready(struct adf7242_local *lp, int line) 348 { 349 return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY, 350 STAT_RC_READY | STAT_SPI_READY, line); 351 } 352 353 static int adf7242_wait_spi_ready(struct adf7242_local *lp, int line) 354 { 355 return adf7242_wait_status(lp, STAT_SPI_READY, 356 STAT_SPI_READY, line); 357 } 358 359 static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len) 360 { 361 u8 *buf = lp->buf; 362 int status; 363 struct spi_message msg; 364 struct spi_transfer xfer_head = { 365 .len = 2, 366 .tx_buf = buf, 367 368 }; 369 struct spi_transfer xfer_buf = { 370 .len = len, 371 .tx_buf = data, 372 }; 373 374 spi_message_init(&msg); 375 spi_message_add_tail(&xfer_head, &msg); 376 spi_message_add_tail(&xfer_buf, &msg); 377 378 adf7242_wait_spi_ready(lp, __LINE__); 379 380 mutex_lock(&lp->bmux); 381 buf[0] = CMD_SPI_PKT_WR; 382 buf[1] = len + 2; 383 384 status = spi_sync(lp->spi, &msg); 385 mutex_unlock(&lp->bmux); 386 387 return status; 388 } 389 390 static int adf7242_read_fbuf(struct adf7242_local *lp, 391 u8 *data, size_t len, bool packet_read) 392 { 393 u8 *buf = lp->buf; 394 int status; 395 struct spi_message msg; 396 struct spi_transfer xfer_head = { 397 .len = 3, 398 .tx_buf = buf, 399 .rx_buf = buf, 400 }; 401 struct spi_transfer xfer_buf = { 402 .len = len, 403 .rx_buf = data, 404 }; 405 406 spi_message_init(&msg); 407 spi_message_add_tail(&xfer_head, &msg); 408 spi_message_add_tail(&xfer_buf, &msg); 409 410 adf7242_wait_spi_ready(lp, __LINE__); 411 412 mutex_lock(&lp->bmux); 413 if (packet_read) { 414 buf[0] = CMD_SPI_PKT_RD; 415 buf[1] = CMD_SPI_NOP; 416 buf[2] = 0; /* PHR */ 417 } else { 418 buf[0] = CMD_SPI_PRAM_RD; 419 buf[1] = 0; 420 buf[2] = CMD_SPI_NOP; 421 } 422 423 status = spi_sync(lp->spi, &msg); 424 425 mutex_unlock(&lp->bmux); 426 427 return status; 428 } 429 430 static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data) 431 { 432 int status; 433 struct spi_message msg; 434 435 struct spi_transfer xfer = { 436 .len = 4, 437 .tx_buf = lp->buf_read_tx, 438 .rx_buf = lp->buf_read_rx, 439 }; 440 441 adf7242_wait_spi_ready(lp, __LINE__); 442 443 mutex_lock(&lp->bmux); 444 lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr); 445 lp->buf_read_tx[1] = addr; 446 lp->buf_read_tx[2] = CMD_SPI_NOP; 447 lp->buf_read_tx[3] = CMD_SPI_NOP; 448 449 spi_message_init(&msg); 450 spi_message_add_tail(&xfer, &msg); 451 452 status = spi_sync(lp->spi, &msg); 453 if (msg.status) 454 status = msg.status; 455 456 if (!status) 457 *data = lp->buf_read_rx[3]; 458 459 mutex_unlock(&lp->bmux); 460 461 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__, 462 addr, *data); 463 464 return status; 465 } 466 467 static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data) 468 { 469 int status; 470 471 adf7242_wait_spi_ready(lp, __LINE__); 472 473 mutex_lock(&lp->bmux); 474 lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr); 475 lp->buf_reg_tx[1] = addr; 476 lp->buf_reg_tx[2] = data; 477 status = spi_write(lp->spi, lp->buf_reg_tx, 3); 478 mutex_unlock(&lp->bmux); 479 480 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", 481 __func__, addr, data); 482 483 return status; 484 } 485 486 static int adf7242_cmd(struct adf7242_local *lp, unsigned int cmd) 487 { 488 int status; 489 490 dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd); 491 492 if (cmd != CMD_RC_PC_RESET_NO_WAIT) 493 adf7242_wait_rc_ready(lp, __LINE__); 494 495 mutex_lock(&lp->bmux); 496 lp->buf_cmd = cmd; 497 status = spi_write(lp->spi, &lp->buf_cmd, 1); 498 mutex_unlock(&lp->bmux); 499 500 return status; 501 } 502 503 static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len) 504 { 505 struct spi_message msg; 506 struct spi_transfer xfer_buf = { }; 507 int status, i, page = 0; 508 u8 *buf = lp->buf; 509 510 struct spi_transfer xfer_head = { 511 .len = 2, 512 .tx_buf = buf, 513 }; 514 515 buf[0] = CMD_SPI_PRAM_WR; 516 buf[1] = 0; 517 518 spi_message_init(&msg); 519 spi_message_add_tail(&xfer_head, &msg); 520 spi_message_add_tail(&xfer_buf, &msg); 521 522 for (i = len; i >= 0; i -= PRAM_PAGESIZE) { 523 adf7242_write_reg(lp, REG_PRAMPG, page); 524 525 xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 526 xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE]; 527 528 mutex_lock(&lp->bmux); 529 status = spi_sync(lp->spi, &msg); 530 mutex_unlock(&lp->bmux); 531 page++; 532 } 533 534 return status; 535 } 536 537 static int adf7242_verify_firmware(struct adf7242_local *lp, 538 const u8 *data, size_t len) 539 { 540 #ifdef DEBUG 541 int i, j; 542 unsigned int page; 543 u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL); 544 545 if (!buf) 546 return -ENOMEM; 547 548 for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) { 549 size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 550 551 adf7242_write_reg(lp, REG_PRAMPG, page); 552 adf7242_read_fbuf(lp, buf, nb, false); 553 554 for (j = 0; j < nb; j++) { 555 if (buf[j] != data[page * PRAM_PAGESIZE + j]) { 556 kfree(buf); 557 return -EIO; 558 } 559 } 560 } 561 kfree(buf); 562 #endif 563 return 0; 564 } 565 566 static void adf7242_clear_irqstat(struct adf7242_local *lp) 567 { 568 adf7242_write_reg(lp, REG_IRQ1_SRC1, IRQ_CCA_COMPLETE | IRQ_SFD_RX | 569 IRQ_SFD_TX | IRQ_RX_PKT_RCVD | IRQ_TX_PKT_SENT | 570 IRQ_FRAME_VALID | IRQ_ADDRESS_VALID | IRQ_CSMA_CA); 571 } 572 573 static int adf7242_cmd_rx(struct adf7242_local *lp) 574 { 575 /* Wait until the ACK is sent */ 576 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__); 577 adf7242_clear_irqstat(lp); 578 579 return adf7242_cmd(lp, CMD_RC_RX); 580 } 581 582 static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm) 583 { 584 struct adf7242_local *lp = hw->priv; 585 u8 pwr, bias_ctrl, dbias, tmp; 586 int db = mbm / 100; 587 588 dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db); 589 590 if (db > 5 || db < -26) 591 return -EINVAL; 592 593 db = DIV_ROUND_CLOSEST(db + 29, 2); 594 595 if (db > 15) { 596 dbias = PA_DBIAS_HIGH_POWER; 597 bias_ctrl = PA_BIAS_HIGH_POWER; 598 } else { 599 dbias = PA_DBIAS_LOW_POWER; 600 bias_ctrl = PA_BIAS_LOW_POWER; 601 } 602 603 pwr = clamp_t(u8, db, 3, 15); 604 605 adf7242_read_reg(lp, REG_PA_CFG, &tmp); 606 tmp &= ~PA_BRIDGE_DBIAS(~0); 607 tmp |= PA_BRIDGE_DBIAS(dbias); 608 adf7242_write_reg(lp, REG_PA_CFG, tmp); 609 610 adf7242_read_reg(lp, REG_PA_BIAS, &tmp); 611 tmp &= ~PA_BIAS_CTRL(~0); 612 tmp |= PA_BIAS_CTRL(bias_ctrl); 613 adf7242_write_reg(lp, REG_PA_BIAS, tmp); 614 615 adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp); 616 tmp &= ~PA_PWR(~0); 617 tmp |= PA_PWR(pwr); 618 619 return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp); 620 } 621 622 static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be, 623 u8 max_be, u8 retries) 624 { 625 struct adf7242_local *lp = hw->priv; 626 int ret; 627 628 dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n", 629 __func__, min_be, max_be, retries); 630 631 if (min_be > max_be || max_be > 8 || retries > 5) 632 return -EINVAL; 633 634 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 635 MAX_FRAME_RETRIES(lp->max_frame_retries) | 636 MAX_CCA_RETRIES(retries)); 637 if (ret) 638 return ret; 639 640 lp->max_cca_retries = retries; 641 lp->max_be = max_be; 642 lp->min_be = min_be; 643 644 return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) | 645 CSMA_MIN_BE(min_be)); 646 } 647 648 static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries) 649 { 650 struct adf7242_local *lp = hw->priv; 651 int ret = 0; 652 653 dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries); 654 655 if (retries < -1 || retries > 15) 656 return -EINVAL; 657 658 if (retries >= 0) 659 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 660 MAX_FRAME_RETRIES(retries) | 661 MAX_CCA_RETRIES(lp->max_cca_retries)); 662 663 lp->max_frame_retries = retries; 664 665 return ret; 666 } 667 668 static int adf7242_ed(struct ieee802154_hw *hw, u8 *level) 669 { 670 struct adf7242_local *lp = hw->priv; 671 672 *level = lp->rssi; 673 674 dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n", 675 __func__, *level); 676 677 return 0; 678 } 679 680 static int adf7242_start(struct ieee802154_hw *hw) 681 { 682 struct adf7242_local *lp = hw->priv; 683 684 adf7242_cmd(lp, CMD_RC_PHY_RDY); 685 adf7242_clear_irqstat(lp); 686 enable_irq(lp->spi->irq); 687 set_bit(FLAG_START, &lp->flags); 688 689 return adf7242_cmd(lp, CMD_RC_RX); 690 } 691 692 static void adf7242_stop(struct ieee802154_hw *hw) 693 { 694 struct adf7242_local *lp = hw->priv; 695 696 disable_irq(lp->spi->irq); 697 adf7242_cmd(lp, CMD_RC_IDLE); 698 clear_bit(FLAG_START, &lp->flags); 699 adf7242_clear_irqstat(lp); 700 } 701 702 static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel) 703 { 704 struct adf7242_local *lp = hw->priv; 705 unsigned long freq; 706 707 dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel); 708 709 might_sleep(); 710 711 WARN_ON(page != 0); 712 WARN_ON(channel < 11); 713 WARN_ON(channel > 26); 714 715 freq = (2405 + 5 * (channel - 11)) * 100; 716 adf7242_cmd(lp, CMD_RC_PHY_RDY); 717 718 adf7242_write_reg(lp, REG_CH_FREQ0, freq); 719 adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8); 720 adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16); 721 722 return adf7242_cmd(lp, CMD_RC_RX); 723 } 724 725 static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw, 726 struct ieee802154_hw_addr_filt *filt, 727 unsigned long changed) 728 { 729 struct adf7242_local *lp = hw->priv; 730 u8 reg; 731 732 dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed); 733 734 might_sleep(); 735 736 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { 737 u8 addr[8], i; 738 739 memcpy(addr, &filt->ieee_addr, 8); 740 741 for (i = 0; i < 8; i++) 742 adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]); 743 } 744 745 if (changed & IEEE802154_AFILT_SADDR_CHANGED) { 746 u16 saddr = le16_to_cpu(filt->short_addr); 747 748 adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr); 749 adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8); 750 } 751 752 if (changed & IEEE802154_AFILT_PANID_CHANGED) { 753 u16 pan_id = le16_to_cpu(filt->pan_id); 754 755 adf7242_write_reg(lp, REG_PAN_ID0, pan_id); 756 adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8); 757 } 758 759 if (changed & IEEE802154_AFILT_PANC_CHANGED) { 760 adf7242_read_reg(lp, REG_AUTO_CFG, ®); 761 if (filt->pan_coord) 762 reg |= IS_PANCOORD; 763 else 764 reg &= ~IS_PANCOORD; 765 adf7242_write_reg(lp, REG_AUTO_CFG, reg); 766 } 767 768 return 0; 769 } 770 771 static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) 772 { 773 struct adf7242_local *lp = hw->priv; 774 775 dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on); 776 777 lp->promiscuous = on; 778 779 if (on) { 780 adf7242_write_reg(lp, REG_AUTO_CFG, 0); 781 return adf7242_write_reg(lp, REG_FFILT_CFG, 782 ACCEPT_BEACON_FRAMES | 783 ACCEPT_DATA_FRAMES | 784 ACCEPT_MACCMD_FRAMES | 785 ACCEPT_ALL_ADDRESS | 786 ACCEPT_ACK_FRAMES | 787 ACCEPT_RESERVED_FRAMES); 788 } else { 789 adf7242_write_reg(lp, REG_FFILT_CFG, 790 ACCEPT_BEACON_FRAMES | 791 ACCEPT_DATA_FRAMES | 792 ACCEPT_MACCMD_FRAMES | 793 ACCEPT_RESERVED_FRAMES); 794 795 return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 796 } 797 } 798 799 static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) 800 { 801 struct adf7242_local *lp = hw->priv; 802 s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX); 803 804 dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level); 805 806 return adf7242_write_reg(lp, REG_CCA1, level); 807 } 808 809 static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) 810 { 811 struct adf7242_local *lp = hw->priv; 812 int ret; 813 814 /* ensure existing instances of the IRQ handler have completed */ 815 disable_irq(lp->spi->irq); 816 set_bit(FLAG_XMIT, &lp->flags); 817 reinit_completion(&lp->tx_complete); 818 adf7242_cmd(lp, CMD_RC_PHY_RDY); 819 adf7242_clear_irqstat(lp); 820 821 ret = adf7242_write_fbuf(lp, skb->data, skb->len); 822 if (ret) 823 goto err; 824 825 ret = adf7242_cmd(lp, CMD_RC_CSMACA); 826 if (ret) 827 goto err; 828 enable_irq(lp->spi->irq); 829 830 ret = wait_for_completion_interruptible_timeout(&lp->tx_complete, 831 HZ / 10); 832 if (ret < 0) 833 goto err; 834 if (ret == 0) { 835 dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n"); 836 ret = -ETIMEDOUT; 837 goto err; 838 } 839 840 if (lp->tx_stat != SUCCESS) { 841 dev_dbg(&lp->spi->dev, 842 "Error xmit: Retry count exceeded Status=0x%x\n", 843 lp->tx_stat); 844 ret = -ECOMM; 845 } else { 846 ret = 0; 847 } 848 849 err: 850 clear_bit(FLAG_XMIT, &lp->flags); 851 adf7242_cmd_rx(lp); 852 853 return ret; 854 } 855 856 static int adf7242_rx(struct adf7242_local *lp) 857 { 858 struct sk_buff *skb; 859 size_t len; 860 int ret; 861 u8 lqi, len_u8, *data; 862 863 adf7242_read_reg(lp, 0, &len_u8); 864 865 len = len_u8; 866 867 if (!ieee802154_is_valid_psdu_len(len)) { 868 dev_dbg(&lp->spi->dev, 869 "corrupted frame received len %d\n", (int)len); 870 len = IEEE802154_MTU; 871 } 872 873 skb = dev_alloc_skb(len); 874 if (!skb) { 875 adf7242_cmd_rx(lp); 876 return -ENOMEM; 877 } 878 879 data = skb_put(skb, len); 880 ret = adf7242_read_fbuf(lp, data, len, true); 881 if (ret < 0) { 882 kfree_skb(skb); 883 adf7242_cmd_rx(lp); 884 return ret; 885 } 886 887 lqi = data[len - 2]; 888 lp->rssi = data[len - 1]; 889 890 ret = adf7242_cmd_rx(lp); 891 892 skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */ 893 894 ieee802154_rx_irqsafe(lp->hw, skb, lqi); 895 896 dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n", 897 __func__, ret, (int)len, (int)lqi, lp->rssi); 898 899 return ret; 900 } 901 902 static const struct ieee802154_ops adf7242_ops = { 903 .owner = THIS_MODULE, 904 .xmit_sync = adf7242_xmit, 905 .ed = adf7242_ed, 906 .set_channel = adf7242_channel, 907 .set_hw_addr_filt = adf7242_set_hw_addr_filt, 908 .start = adf7242_start, 909 .stop = adf7242_stop, 910 .set_csma_params = adf7242_set_csma_params, 911 .set_frame_retries = adf7242_set_frame_retries, 912 .set_txpower = adf7242_set_txpower, 913 .set_promiscuous_mode = adf7242_set_promiscuous_mode, 914 .set_cca_ed_level = adf7242_set_cca_ed_level, 915 }; 916 917 static void adf7242_debug(struct adf7242_local *lp, u8 irq1) 918 { 919 #ifdef DEBUG 920 u8 stat; 921 922 adf7242_status(lp, &stat); 923 924 dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", 925 __func__, irq1, 926 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 927 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 928 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 929 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 930 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 931 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 932 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 933 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 934 935 dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", 936 __func__, stat, 937 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY", 938 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR", 939 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 940 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY", 941 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 942 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 943 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 944 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 945 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 946 #endif 947 } 948 949 static irqreturn_t adf7242_isr(int irq, void *data) 950 { 951 struct adf7242_local *lp = data; 952 unsigned int xmit; 953 u8 irq1; 954 955 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 956 957 if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA))) 958 dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n", 959 __func__, irq1); 960 961 adf7242_debug(lp, irq1); 962 963 xmit = test_bit(FLAG_XMIT, &lp->flags); 964 965 if (xmit && (irq1 & IRQ_CSMA_CA)) { 966 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, 967 RC_STATUS_MASK, __LINE__); 968 969 if (ADF7242_REPORT_CSMA_CA_STAT) { 970 u8 astat; 971 972 adf7242_read_reg(lp, REG_AUTO_STATUS, &astat); 973 astat &= AUTO_STATUS_MASK; 974 975 dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n", 976 astat, 977 astat == SUCCESS ? "SUCCESS" : "", 978 astat == 979 SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "", 980 astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "", 981 astat == FAILURE_NOACK ? "FAILURE_NOACK" : ""); 982 983 /* save CSMA-CA completion status */ 984 lp->tx_stat = astat; 985 } else { 986 lp->tx_stat = SUCCESS; 987 } 988 complete(&lp->tx_complete); 989 adf7242_clear_irqstat(lp); 990 } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) && 991 (irq1 & IRQ_FRAME_VALID)) { 992 adf7242_rx(lp); 993 } else if (!xmit && test_bit(FLAG_START, &lp->flags)) { 994 /* Invalid packet received - drop it and restart */ 995 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n", 996 __func__, __LINE__, irq1); 997 adf7242_cmd(lp, CMD_RC_PHY_RDY); 998 adf7242_cmd_rx(lp); 999 } else { 1000 /* This can only be xmit without IRQ, likely a RX packet. 1001 * we get an TX IRQ shortly - do nothing or let the xmit 1002 * timeout handle this 1003 */ 1004 1005 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n", 1006 __func__, __LINE__, irq1, xmit); 1007 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, 1008 RC_STATUS_MASK, __LINE__); 1009 complete(&lp->tx_complete); 1010 adf7242_clear_irqstat(lp); 1011 } 1012 1013 return IRQ_HANDLED; 1014 } 1015 1016 static int adf7242_soft_reset(struct adf7242_local *lp, int line) 1017 { 1018 dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line); 1019 1020 if (test_bit(FLAG_START, &lp->flags)) 1021 disable_irq_nosync(lp->spi->irq); 1022 1023 adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT); 1024 usleep_range(200, 250); 1025 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 1026 adf7242_cmd(lp, CMD_RC_PHY_RDY); 1027 adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous); 1028 adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be, 1029 lp->max_cca_retries); 1030 adf7242_clear_irqstat(lp); 1031 1032 if (test_bit(FLAG_START, &lp->flags)) { 1033 enable_irq(lp->spi->irq); 1034 return adf7242_cmd(lp, CMD_RC_RX); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int adf7242_hw_init(struct adf7242_local *lp) 1041 { 1042 int ret; 1043 const struct firmware *fw; 1044 1045 adf7242_cmd(lp, CMD_RC_RESET); 1046 adf7242_cmd(lp, CMD_RC_IDLE); 1047 1048 /* get ADF7242 addon firmware 1049 * build this driver as module 1050 * and place under /lib/firmware/adf7242_firmware.bin 1051 * or compile firmware into the kernel. 1052 */ 1053 ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev); 1054 if (ret) { 1055 dev_err(&lp->spi->dev, 1056 "request_firmware() failed with %d\n", ret); 1057 return ret; 1058 } 1059 1060 ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size); 1061 if (ret) { 1062 dev_err(&lp->spi->dev, 1063 "upload firmware failed with %d\n", ret); 1064 release_firmware(fw); 1065 return ret; 1066 } 1067 1068 ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size); 1069 if (ret) { 1070 dev_err(&lp->spi->dev, 1071 "verify firmware failed with %d\n", ret); 1072 release_firmware(fw); 1073 return ret; 1074 } 1075 1076 adf7242_cmd(lp, CMD_RC_PC_RESET); 1077 1078 release_firmware(fw); 1079 1080 adf7242_write_reg(lp, REG_FFILT_CFG, 1081 ACCEPT_BEACON_FRAMES | 1082 ACCEPT_DATA_FRAMES | 1083 ACCEPT_MACCMD_FRAMES | 1084 ACCEPT_RESERVED_FRAMES); 1085 1086 adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 1087 1088 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 1089 1090 adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1); 1091 adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D); 1092 1093 adf7242_write_reg(lp, REG_IRQ1_EN0, 0); 1094 adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA); 1095 1096 adf7242_clear_irqstat(lp); 1097 adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF); 1098 1099 adf7242_cmd(lp, CMD_RC_IDLE); 1100 1101 return 0; 1102 } 1103 1104 static int adf7242_stats_show(struct seq_file *file, void *offset) 1105 { 1106 struct adf7242_local *lp = spi_get_drvdata(file->private); 1107 u8 stat, irq1; 1108 1109 adf7242_status(lp, &stat); 1110 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 1111 1112 seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1, 1113 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 1114 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 1115 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 1116 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 1117 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 1118 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 1119 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 1120 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 1121 1122 seq_printf(file, "STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", stat, 1123 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY", 1124 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR", 1125 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 1126 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY", 1127 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 1128 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 1129 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 1130 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 1131 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 1132 1133 seq_printf(file, "RSSI = %d\n", lp->rssi); 1134 1135 return 0; 1136 } 1137 1138 static int adf7242_debugfs_init(struct adf7242_local *lp) 1139 { 1140 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-"; 1141 struct dentry *stats; 1142 1143 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN); 1144 1145 lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1146 if (IS_ERR_OR_NULL(lp->debugfs_root)) 1147 return PTR_ERR_OR_ZERO(lp->debugfs_root); 1148 1149 stats = debugfs_create_devm_seqfile(&lp->spi->dev, "status", 1150 lp->debugfs_root, 1151 adf7242_stats_show); 1152 return PTR_ERR_OR_ZERO(stats); 1153 1154 return 0; 1155 } 1156 1157 static const s32 adf7242_powers[] = { 1158 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700, 1159 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700, 1160 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600, 1161 }; 1162 1163 static const s32 adf7242_ed_levels[] = { 1164 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, 1165 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, 1166 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, 1167 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, 1168 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, 1169 -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000 1170 }; 1171 1172 static int adf7242_probe(struct spi_device *spi) 1173 { 1174 struct ieee802154_hw *hw; 1175 struct adf7242_local *lp; 1176 int ret, irq_type; 1177 1178 if (!spi->irq) { 1179 dev_err(&spi->dev, "no IRQ specified\n"); 1180 return -EINVAL; 1181 } 1182 1183 hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops); 1184 if (!hw) 1185 return -ENOMEM; 1186 1187 lp = hw->priv; 1188 lp->hw = hw; 1189 lp->spi = spi; 1190 1191 hw->priv = lp; 1192 hw->parent = &spi->dev; 1193 hw->extra_tx_headroom = 0; 1194 1195 /* We support only 2.4 Ghz */ 1196 hw->phy->supported.channels[0] = 0x7FFF800; 1197 1198 hw->flags = IEEE802154_HW_OMIT_CKSUM | 1199 IEEE802154_HW_CSMA_PARAMS | 1200 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT | 1201 IEEE802154_HW_PROMISCUOUS; 1202 1203 hw->phy->flags = WPAN_PHY_FLAG_TXPOWER | 1204 WPAN_PHY_FLAG_CCA_ED_LEVEL | 1205 WPAN_PHY_FLAG_CCA_MODE; 1206 1207 hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY); 1208 1209 hw->phy->supported.cca_ed_levels = adf7242_ed_levels; 1210 hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels); 1211 1212 hw->phy->cca.mode = NL802154_CCA_ENERGY; 1213 1214 hw->phy->supported.tx_powers = adf7242_powers; 1215 hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers); 1216 1217 hw->phy->supported.min_minbe = 0; 1218 hw->phy->supported.max_minbe = 8; 1219 1220 hw->phy->supported.min_maxbe = 3; 1221 hw->phy->supported.max_maxbe = 8; 1222 1223 hw->phy->supported.min_frame_retries = 0; 1224 hw->phy->supported.max_frame_retries = 15; 1225 1226 hw->phy->supported.min_csma_backoffs = 0; 1227 hw->phy->supported.max_csma_backoffs = 5; 1228 1229 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); 1230 1231 mutex_init(&lp->bmux); 1232 init_completion(&lp->tx_complete); 1233 1234 /* Setup Status Message */ 1235 lp->stat_xfer.len = 1; 1236 lp->stat_xfer.tx_buf = &lp->buf_stat_tx; 1237 lp->stat_xfer.rx_buf = &lp->buf_stat_rx; 1238 lp->buf_stat_tx = CMD_SPI_NOP; 1239 1240 spi_message_init(&lp->stat_msg); 1241 spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg); 1242 1243 spi_set_drvdata(spi, lp); 1244 1245 ret = adf7242_hw_init(lp); 1246 if (ret) 1247 goto err_hw_init; 1248 1249 irq_type = irq_get_trigger_type(spi->irq); 1250 if (!irq_type) 1251 irq_type = IRQF_TRIGGER_HIGH; 1252 1253 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr, 1254 irq_type | IRQF_ONESHOT, 1255 dev_name(&spi->dev), lp); 1256 if (ret) 1257 goto err_hw_init; 1258 1259 disable_irq(spi->irq); 1260 1261 ret = ieee802154_register_hw(lp->hw); 1262 if (ret) 1263 goto err_hw_init; 1264 1265 dev_set_drvdata(&spi->dev, lp); 1266 1267 adf7242_debugfs_init(lp); 1268 1269 dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq); 1270 1271 return ret; 1272 1273 err_hw_init: 1274 mutex_destroy(&lp->bmux); 1275 ieee802154_free_hw(lp->hw); 1276 1277 return ret; 1278 } 1279 1280 static int adf7242_remove(struct spi_device *spi) 1281 { 1282 struct adf7242_local *lp = spi_get_drvdata(spi); 1283 1284 if (!IS_ERR_OR_NULL(lp->debugfs_root)) 1285 debugfs_remove_recursive(lp->debugfs_root); 1286 1287 ieee802154_unregister_hw(lp->hw); 1288 mutex_destroy(&lp->bmux); 1289 ieee802154_free_hw(lp->hw); 1290 1291 return 0; 1292 } 1293 1294 static const struct of_device_id adf7242_of_match[] = { 1295 { .compatible = "adi,adf7242", }, 1296 { .compatible = "adi,adf7241", }, 1297 { }, 1298 }; 1299 MODULE_DEVICE_TABLE(of, adf7242_of_match); 1300 1301 static const struct spi_device_id adf7242_device_id[] = { 1302 { .name = "adf7242", }, 1303 { .name = "adf7241", }, 1304 { }, 1305 }; 1306 MODULE_DEVICE_TABLE(spi, adf7242_device_id); 1307 1308 static struct spi_driver adf7242_driver = { 1309 .id_table = adf7242_device_id, 1310 .driver = { 1311 .of_match_table = of_match_ptr(adf7242_of_match), 1312 .name = "adf7242", 1313 .owner = THIS_MODULE, 1314 }, 1315 .probe = adf7242_probe, 1316 .remove = adf7242_remove, 1317 }; 1318 1319 module_spi_driver(adf7242_driver); 1320 1321 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1322 MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver"); 1323 MODULE_LICENSE("GPL"); 1324