1 /* 2 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver 3 * 4 * Copyright 2009-2015 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 * 8 * http://www.analog.com/ADF7242 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/delay.h> 15 #include <linux/mutex.h> 16 #include <linux/workqueue.h> 17 #include <linux/spinlock.h> 18 #include <linux/firmware.h> 19 #include <linux/spi/spi.h> 20 #include <linux/skbuff.h> 21 #include <linux/of.h> 22 #include <linux/irq.h> 23 #include <linux/debugfs.h> 24 #include <linux/bitops.h> 25 #include <linux/ieee802154.h> 26 #include <net/mac802154.h> 27 #include <net/cfg802154.h> 28 29 #define FIRMWARE "adf7242_firmware.bin" 30 #define MAX_POLL_LOOPS 200 31 32 /* All Registers */ 33 34 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */ 35 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */ 36 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */ 37 #define REG_CCA2 0x106 /* RW CCA mode configuration */ 38 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */ 39 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */ 40 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */ 41 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */ 42 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */ 43 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */ 44 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */ 45 #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */ 46 #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */ 47 #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */ 48 #define REG_RC_VAR44 0x13F /* RW RESERVED */ 49 #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */ 50 #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */ 51 #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */ 52 #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */ 53 #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */ 54 #define REG_TX_M 0x306 /* RW TX Mode Register */ 55 #define REG_RX_M 0x307 /* RW RX Mode Register */ 56 #define REG_RRB 0x30C /* R RSSI Readback Register */ 57 #define REG_LRB 0x30D /* R Link Quality Readback Register */ 58 #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */ 59 #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */ 60 #define REG_PRAMPG 0x313 /* RW RESERVED */ 61 #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */ 62 #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */ 63 #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */ 64 #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */ 65 #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */ 66 #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */ 67 #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */ 68 #define REG_PD_AUX 0x31E /* RW Battmon enable */ 69 #define REG_GP_CFG 0x32C /* RW GPIO Configuration */ 70 #define REG_GP_OUT 0x32D /* RW GPIO Configuration */ 71 #define REG_GP_IN 0x32E /* R GPIO Configuration */ 72 #define REG_SYNT 0x335 /* RW bandwidth calibration timers */ 73 #define REG_CAL_CFG 0x33D /* RW Calibration Settings */ 74 #define REG_PA_BIAS 0x36E /* RW PA BIAS */ 75 #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */ 76 #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */ 77 #define REG_CDR_CFG 0x38A /* RW CDR kVCO */ 78 #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */ 79 #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */ 80 #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */ 81 #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */ 82 #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */ 83 #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */ 84 #define REG_PA_CFG 0x3A8 /* RW PA enable */ 85 #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */ 86 #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */ 87 #define REG_ADC_RBK 0x3AE /* R Readback temp */ 88 #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */ 89 #define REG_AGC_MAX 0x3B4 /* RW Slew rate */ 90 #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */ 91 #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */ 92 #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */ 93 #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */ 94 #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */ 95 #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */ 96 #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */ 97 #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */ 98 #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */ 99 #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */ 100 #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */ 101 #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */ 102 #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */ 103 #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */ 104 #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */ 105 #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */ 106 #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */ 107 #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */ 108 #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */ 109 #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */ 110 #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */ 111 #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */ 112 #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */ 113 #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */ 114 #define REG_AFC_RANGE 0x3F9 /* RW AFC range */ 115 #define REG_AFC_READ 0x3FA /* RW Readback frequency error */ 116 117 /* REG_EXTPA_MSC */ 118 #define PA_PWR(x) (((x) & 0xF) << 4) 119 #define EXTPA_BIAS_SRC BIT(3) 120 #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0) 121 122 /* REG_PA_CFG */ 123 #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0) 124 #define PA_DBIAS_HIGH_POWER 21 125 #define PA_DBIAS_LOW_POWER 13 126 127 /* REG_PA_BIAS */ 128 #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1) 129 #define REG_PA_BIAS_DFL BIT(0) 130 #define PA_BIAS_HIGH_POWER 63 131 #define PA_BIAS_LOW_POWER 55 132 133 #define REG_PAN_ID0 0x112 134 #define REG_PAN_ID1 0x113 135 #define REG_SHORT_ADDR_0 0x114 136 #define REG_SHORT_ADDR_1 0x115 137 #define REG_IEEE_ADDR_0 0x116 138 #define REG_IEEE_ADDR_1 0x117 139 #define REG_IEEE_ADDR_2 0x118 140 #define REG_IEEE_ADDR_3 0x119 141 #define REG_IEEE_ADDR_4 0x11A 142 #define REG_IEEE_ADDR_5 0x11B 143 #define REG_IEEE_ADDR_6 0x11C 144 #define REG_IEEE_ADDR_7 0x11D 145 #define REG_FFILT_CFG 0x11E 146 #define REG_AUTO_CFG 0x11F 147 #define REG_AUTO_TX1 0x120 148 #define REG_AUTO_TX2 0x121 149 #define REG_AUTO_STATUS 0x122 150 151 /* REG_FFILT_CFG */ 152 #define ACCEPT_BEACON_FRAMES BIT(0) 153 #define ACCEPT_DATA_FRAMES BIT(1) 154 #define ACCEPT_ACK_FRAMES BIT(2) 155 #define ACCEPT_MACCMD_FRAMES BIT(3) 156 #define ACCEPT_RESERVED_FRAMES BIT(4) 157 #define ACCEPT_ALL_ADDRESS BIT(5) 158 159 /* REG_AUTO_CFG */ 160 #define AUTO_ACK_FRAMEPEND BIT(0) 161 #define IS_PANCOORD BIT(1) 162 #define RX_AUTO_ACK_EN BIT(3) 163 #define CSMA_CA_RX_TURNAROUND BIT(4) 164 165 /* REG_AUTO_TX1 */ 166 #define MAX_FRAME_RETRIES(x) ((x) & 0xF) 167 #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4) 168 169 /* REG_AUTO_TX2 */ 170 #define CSMA_MAX_BE(x) ((x) & 0xF) 171 #define CSMA_MIN_BE(x) (((x) & 0xF) << 4) 172 173 #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */ 174 #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM 175 * starting from the TX packet base address 176 * pointer tx_packet_base 177 */ 178 #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM 179 * starting from RX packet base address 180 * pointer rxpb.rx_packet_base 181 */ 182 #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or 183 * Packet RAM sequentially 184 */ 185 #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or 186 * Packet RAM sequentially 187 */ 188 #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet 189 * RAM as random block 190 */ 191 #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or 192 * Packet RAM random block 193 */ 194 #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current 195 * PRAM page selected 196 */ 197 #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current 198 * PRAM page selected 199 */ 200 #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller 201 * into SLEEP state 202 */ 203 #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller 204 * into IDLE state 205 */ 206 #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller 207 * into PHY_RDY state 208 */ 209 #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller 210 * into RX state 211 */ 212 #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller 213 * into TX state 214 */ 215 #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller 216 * into MEAS state 217 */ 218 #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */ 219 #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access 220 * sequence and frame transmission 221 */ 222 #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */ 223 #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in 224 * the sleep state 225 */ 226 #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31)) 227 228 /* STATUS */ 229 230 #define STAT_SPI_READY BIT(7) 231 #define STAT_IRQ_STATUS BIT(6) 232 #define STAT_RC_READY BIT(5) 233 #define STAT_CCA_RESULT BIT(4) 234 #define RC_STATUS_IDLE 1 235 #define RC_STATUS_MEAS 2 236 #define RC_STATUS_PHY_RDY 3 237 #define RC_STATUS_RX 4 238 #define RC_STATUS_TX 5 239 #define RC_STATUS_MASK 0xF 240 241 /* AUTO_STATUS */ 242 243 #define SUCCESS 0 244 #define SUCCESS_DATPEND 1 245 #define FAILURE_CSMACA 2 246 #define FAILURE_NOACK 3 247 #define AUTO_STATUS_MASK 0x3 248 249 #define PRAM_PAGESIZE 256 250 251 /* IRQ1 */ 252 253 #define IRQ_CCA_COMPLETE BIT(0) 254 #define IRQ_SFD_RX BIT(1) 255 #define IRQ_SFD_TX BIT(2) 256 #define IRQ_RX_PKT_RCVD BIT(3) 257 #define IRQ_TX_PKT_SENT BIT(4) 258 #define IRQ_FRAME_VALID BIT(5) 259 #define IRQ_ADDRESS_VALID BIT(6) 260 #define IRQ_CSMA_CA BIT(7) 261 262 #define AUTO_TX_TURNAROUND BIT(3) 263 #define ADDON_EN BIT(4) 264 265 #define FLAG_XMIT 0 266 #define FLAG_START 1 267 268 #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */ 269 270 struct adf7242_local { 271 struct spi_device *spi; 272 struct completion tx_complete; 273 struct ieee802154_hw *hw; 274 struct mutex bmux; /* protect SPI messages */ 275 struct spi_message stat_msg; 276 struct spi_transfer stat_xfer; 277 struct dentry *debugfs_root; 278 unsigned long flags; 279 int tx_stat; 280 bool promiscuous; 281 s8 rssi; 282 u8 max_frame_retries; 283 u8 max_cca_retries; 284 u8 max_be; 285 u8 min_be; 286 287 /* DMA (thus cache coherency maintenance) requires the 288 * transfer buffers to live in their own cache lines. 289 */ 290 291 u8 buf[3] ____cacheline_aligned; 292 u8 buf_reg_tx[3]; 293 u8 buf_read_tx[4]; 294 u8 buf_read_rx[4]; 295 u8 buf_stat_rx; 296 u8 buf_stat_tx; 297 u8 buf_cmd; 298 }; 299 300 static int adf7242_soft_reset(struct adf7242_local *lp, int line); 301 302 static int adf7242_status(struct adf7242_local *lp, u8 *stat) 303 { 304 int status; 305 306 mutex_lock(&lp->bmux); 307 status = spi_sync(lp->spi, &lp->stat_msg); 308 *stat = lp->buf_stat_rx; 309 mutex_unlock(&lp->bmux); 310 311 return status; 312 } 313 314 static int adf7242_wait_status(struct adf7242_local *lp, unsigned status, 315 unsigned mask, int line) 316 { 317 int cnt = 0, ret = 0; 318 u8 stat; 319 320 do { 321 adf7242_status(lp, &stat); 322 cnt++; 323 } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS)); 324 325 if (cnt >= MAX_POLL_LOOPS) { 326 ret = -ETIMEDOUT; 327 328 if (!(stat & STAT_RC_READY)) { 329 adf7242_soft_reset(lp, line); 330 adf7242_status(lp, &stat); 331 332 if ((stat & mask) == status) 333 ret = 0; 334 } 335 336 if (ret < 0) 337 dev_warn(&lp->spi->dev, 338 "%s:line %d Timeout status 0x%x (%d)\n", 339 __func__, line, stat, cnt); 340 } 341 342 dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line); 343 344 return ret; 345 } 346 347 static int adf7242_wait_ready(struct adf7242_local *lp, int line) 348 { 349 return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY, 350 STAT_RC_READY | STAT_SPI_READY, line); 351 } 352 353 static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len) 354 { 355 u8 *buf = lp->buf; 356 int status; 357 struct spi_message msg; 358 struct spi_transfer xfer_head = { 359 .len = 2, 360 .tx_buf = buf, 361 362 }; 363 struct spi_transfer xfer_buf = { 364 .len = len, 365 .tx_buf = data, 366 }; 367 368 spi_message_init(&msg); 369 spi_message_add_tail(&xfer_head, &msg); 370 spi_message_add_tail(&xfer_buf, &msg); 371 372 adf7242_wait_ready(lp, __LINE__); 373 374 mutex_lock(&lp->bmux); 375 buf[0] = CMD_SPI_PKT_WR; 376 buf[1] = len + 2; 377 378 status = spi_sync(lp->spi, &msg); 379 mutex_unlock(&lp->bmux); 380 381 return status; 382 } 383 384 static int adf7242_read_fbuf(struct adf7242_local *lp, 385 u8 *data, size_t len, bool packet_read) 386 { 387 u8 *buf = lp->buf; 388 int status; 389 struct spi_message msg; 390 struct spi_transfer xfer_head = { 391 .len = 3, 392 .tx_buf = buf, 393 .rx_buf = buf, 394 }; 395 struct spi_transfer xfer_buf = { 396 .len = len, 397 .rx_buf = data, 398 }; 399 400 spi_message_init(&msg); 401 spi_message_add_tail(&xfer_head, &msg); 402 spi_message_add_tail(&xfer_buf, &msg); 403 404 adf7242_wait_ready(lp, __LINE__); 405 406 mutex_lock(&lp->bmux); 407 if (packet_read) { 408 buf[0] = CMD_SPI_PKT_RD; 409 buf[1] = CMD_SPI_NOP; 410 buf[2] = 0; /* PHR */ 411 } else { 412 buf[0] = CMD_SPI_PRAM_RD; 413 buf[1] = 0; 414 buf[2] = CMD_SPI_NOP; 415 } 416 417 status = spi_sync(lp->spi, &msg); 418 419 mutex_unlock(&lp->bmux); 420 421 return status; 422 } 423 424 static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data) 425 { 426 int status; 427 struct spi_message msg; 428 429 struct spi_transfer xfer = { 430 .len = 4, 431 .tx_buf = lp->buf_read_tx, 432 .rx_buf = lp->buf_read_rx, 433 }; 434 435 adf7242_wait_ready(lp, __LINE__); 436 437 mutex_lock(&lp->bmux); 438 lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr); 439 lp->buf_read_tx[1] = addr; 440 lp->buf_read_tx[2] = CMD_SPI_NOP; 441 lp->buf_read_tx[3] = CMD_SPI_NOP; 442 443 spi_message_init(&msg); 444 spi_message_add_tail(&xfer, &msg); 445 446 status = spi_sync(lp->spi, &msg); 447 if (msg.status) 448 status = msg.status; 449 450 if (!status) 451 *data = lp->buf_read_rx[3]; 452 453 mutex_unlock(&lp->bmux); 454 455 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__, 456 addr, *data); 457 458 return status; 459 } 460 461 static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data) 462 { 463 int status; 464 465 adf7242_wait_ready(lp, __LINE__); 466 467 mutex_lock(&lp->bmux); 468 lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr); 469 lp->buf_reg_tx[1] = addr; 470 lp->buf_reg_tx[2] = data; 471 status = spi_write(lp->spi, lp->buf_reg_tx, 3); 472 mutex_unlock(&lp->bmux); 473 474 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", 475 __func__, addr, data); 476 477 return status; 478 } 479 480 static int adf7242_cmd(struct adf7242_local *lp, unsigned cmd) 481 { 482 int status; 483 484 dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd); 485 486 if (cmd != CMD_RC_PC_RESET_NO_WAIT) 487 adf7242_wait_ready(lp, __LINE__); 488 489 mutex_lock(&lp->bmux); 490 lp->buf_cmd = cmd; 491 status = spi_write(lp->spi, &lp->buf_cmd, 1); 492 mutex_unlock(&lp->bmux); 493 494 return status; 495 } 496 497 static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len) 498 { 499 struct spi_message msg; 500 struct spi_transfer xfer_buf = { }; 501 int status, i, page = 0; 502 u8 *buf = lp->buf; 503 504 struct spi_transfer xfer_head = { 505 .len = 2, 506 .tx_buf = buf, 507 }; 508 509 buf[0] = CMD_SPI_PRAM_WR; 510 buf[1] = 0; 511 512 spi_message_init(&msg); 513 spi_message_add_tail(&xfer_head, &msg); 514 spi_message_add_tail(&xfer_buf, &msg); 515 516 for (i = len; i >= 0; i -= PRAM_PAGESIZE) { 517 adf7242_write_reg(lp, REG_PRAMPG, page); 518 519 xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 520 xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE]; 521 522 mutex_lock(&lp->bmux); 523 status = spi_sync(lp->spi, &msg); 524 mutex_unlock(&lp->bmux); 525 page++; 526 } 527 528 return status; 529 } 530 531 static int adf7242_verify_firmware(struct adf7242_local *lp, 532 const u8 *data, size_t len) 533 { 534 #ifdef DEBUG 535 int i, j; 536 unsigned int page; 537 u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL); 538 539 if (!buf) 540 return -ENOMEM; 541 542 for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) { 543 size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 544 545 adf7242_write_reg(lp, REG_PRAMPG, page); 546 adf7242_read_fbuf(lp, buf, nb, false); 547 548 for (j = 0; j < nb; j++) { 549 if (buf[j] != data[page * PRAM_PAGESIZE + j]) { 550 kfree(buf); 551 return -EIO; 552 } 553 } 554 } 555 kfree(buf); 556 #endif 557 return 0; 558 } 559 560 static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm) 561 { 562 struct adf7242_local *lp = hw->priv; 563 u8 pwr, bias_ctrl, dbias, tmp; 564 int db = mbm / 100; 565 566 dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db); 567 568 if (db > 5 || db < -26) 569 return -EINVAL; 570 571 db = DIV_ROUND_CLOSEST(db + 29, 2); 572 573 if (db > 15) { 574 dbias = PA_DBIAS_HIGH_POWER; 575 bias_ctrl = PA_BIAS_HIGH_POWER; 576 } else { 577 dbias = PA_DBIAS_LOW_POWER; 578 bias_ctrl = PA_BIAS_LOW_POWER; 579 } 580 581 pwr = clamp_t(u8, db, 3, 15); 582 583 adf7242_read_reg(lp, REG_PA_CFG, &tmp); 584 tmp &= ~PA_BRIDGE_DBIAS(~0); 585 tmp |= PA_BRIDGE_DBIAS(dbias); 586 adf7242_write_reg(lp, REG_PA_CFG, tmp); 587 588 adf7242_read_reg(lp, REG_PA_BIAS, &tmp); 589 tmp &= ~PA_BIAS_CTRL(~0); 590 tmp |= PA_BIAS_CTRL(bias_ctrl); 591 adf7242_write_reg(lp, REG_PA_BIAS, tmp); 592 593 adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp); 594 tmp &= ~PA_PWR(~0); 595 tmp |= PA_PWR(pwr); 596 597 return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp); 598 } 599 600 static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be, 601 u8 max_be, u8 retries) 602 { 603 struct adf7242_local *lp = hw->priv; 604 int ret; 605 606 dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n", 607 __func__, min_be, max_be, retries); 608 609 if (min_be > max_be || max_be > 8 || retries > 5) 610 return -EINVAL; 611 612 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 613 MAX_FRAME_RETRIES(lp->max_frame_retries) | 614 MAX_CCA_RETRIES(retries)); 615 if (ret) 616 return ret; 617 618 lp->max_cca_retries = retries; 619 lp->max_be = max_be; 620 lp->min_be = min_be; 621 622 return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) | 623 CSMA_MIN_BE(min_be)); 624 } 625 626 static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries) 627 { 628 struct adf7242_local *lp = hw->priv; 629 int ret = 0; 630 631 dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries); 632 633 if (retries < -1 || retries > 15) 634 return -EINVAL; 635 636 if (retries >= 0) 637 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 638 MAX_FRAME_RETRIES(retries) | 639 MAX_CCA_RETRIES(lp->max_cca_retries)); 640 641 lp->max_frame_retries = retries; 642 643 return ret; 644 } 645 646 static int adf7242_ed(struct ieee802154_hw *hw, u8 *level) 647 { 648 struct adf7242_local *lp = hw->priv; 649 650 *level = lp->rssi; 651 652 dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n", 653 __func__, *level); 654 655 return 0; 656 } 657 658 static int adf7242_start(struct ieee802154_hw *hw) 659 { 660 struct adf7242_local *lp = hw->priv; 661 662 adf7242_cmd(lp, CMD_RC_PHY_RDY); 663 adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); 664 enable_irq(lp->spi->irq); 665 set_bit(FLAG_START, &lp->flags); 666 667 return adf7242_cmd(lp, CMD_RC_RX); 668 } 669 670 static void adf7242_stop(struct ieee802154_hw *hw) 671 { 672 struct adf7242_local *lp = hw->priv; 673 674 adf7242_cmd(lp, CMD_RC_IDLE); 675 clear_bit(FLAG_START, &lp->flags); 676 disable_irq(lp->spi->irq); 677 adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); 678 } 679 680 static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel) 681 { 682 struct adf7242_local *lp = hw->priv; 683 unsigned long freq; 684 685 dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel); 686 687 might_sleep(); 688 689 WARN_ON(page != 0); 690 WARN_ON(channel < 11); 691 WARN_ON(channel > 26); 692 693 freq = (2405 + 5 * (channel - 11)) * 100; 694 adf7242_cmd(lp, CMD_RC_PHY_RDY); 695 696 adf7242_write_reg(lp, REG_CH_FREQ0, freq); 697 adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8); 698 adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16); 699 700 return adf7242_cmd(lp, CMD_RC_RX); 701 } 702 703 static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw, 704 struct ieee802154_hw_addr_filt *filt, 705 unsigned long changed) 706 { 707 struct adf7242_local *lp = hw->priv; 708 u8 reg; 709 710 dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed); 711 712 might_sleep(); 713 714 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { 715 u8 addr[8], i; 716 717 memcpy(addr, &filt->ieee_addr, 8); 718 719 for (i = 0; i < 8; i++) 720 adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]); 721 } 722 723 if (changed & IEEE802154_AFILT_SADDR_CHANGED) { 724 u16 saddr = le16_to_cpu(filt->short_addr); 725 726 adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr); 727 adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8); 728 } 729 730 if (changed & IEEE802154_AFILT_PANID_CHANGED) { 731 u16 pan_id = le16_to_cpu(filt->pan_id); 732 733 adf7242_write_reg(lp, REG_PAN_ID0, pan_id); 734 adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8); 735 } 736 737 if (changed & IEEE802154_AFILT_PANC_CHANGED) { 738 adf7242_read_reg(lp, REG_AUTO_CFG, ®); 739 if (filt->pan_coord) 740 reg |= IS_PANCOORD; 741 else 742 reg &= ~IS_PANCOORD; 743 adf7242_write_reg(lp, REG_AUTO_CFG, reg); 744 } 745 746 return 0; 747 } 748 749 static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) 750 { 751 struct adf7242_local *lp = hw->priv; 752 753 dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on); 754 755 lp->promiscuous = on; 756 757 if (on) { 758 adf7242_write_reg(lp, REG_AUTO_CFG, 0); 759 return adf7242_write_reg(lp, REG_FFILT_CFG, 760 ACCEPT_BEACON_FRAMES | 761 ACCEPT_DATA_FRAMES | 762 ACCEPT_MACCMD_FRAMES | 763 ACCEPT_ALL_ADDRESS | 764 ACCEPT_ACK_FRAMES | 765 ACCEPT_RESERVED_FRAMES); 766 } else { 767 adf7242_write_reg(lp, REG_FFILT_CFG, 768 ACCEPT_BEACON_FRAMES | 769 ACCEPT_DATA_FRAMES | 770 ACCEPT_MACCMD_FRAMES | 771 ACCEPT_RESERVED_FRAMES); 772 773 return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 774 } 775 } 776 777 static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) 778 { 779 struct adf7242_local *lp = hw->priv; 780 s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX); 781 782 dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level); 783 784 return adf7242_write_reg(lp, REG_CCA1, level); 785 } 786 787 static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) 788 { 789 struct adf7242_local *lp = hw->priv; 790 int ret; 791 792 set_bit(FLAG_XMIT, &lp->flags); 793 reinit_completion(&lp->tx_complete); 794 adf7242_cmd(lp, CMD_RC_PHY_RDY); 795 796 ret = adf7242_write_fbuf(lp, skb->data, skb->len); 797 if (ret) 798 goto err; 799 800 ret = adf7242_cmd(lp, CMD_RC_CSMACA); 801 if (ret) 802 goto err; 803 804 ret = wait_for_completion_interruptible_timeout(&lp->tx_complete, 805 HZ / 10); 806 if (ret < 0) 807 goto err; 808 if (ret == 0) { 809 dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n"); 810 ret = -ETIMEDOUT; 811 goto err; 812 } 813 814 if (lp->tx_stat != SUCCESS) { 815 dev_dbg(&lp->spi->dev, 816 "Error xmit: Retry count exceeded Status=0x%x\n", 817 lp->tx_stat); 818 ret = -ECOMM; 819 } else { 820 ret = 0; 821 } 822 823 err: 824 clear_bit(FLAG_XMIT, &lp->flags); 825 adf7242_cmd(lp, CMD_RC_RX); 826 827 return ret; 828 } 829 830 static int adf7242_rx(struct adf7242_local *lp) 831 { 832 struct sk_buff *skb; 833 size_t len; 834 int ret; 835 u8 lqi, len_u8, *data; 836 837 adf7242_read_reg(lp, 0, &len_u8); 838 839 len = len_u8; 840 841 if (!ieee802154_is_valid_psdu_len(len)) { 842 dev_dbg(&lp->spi->dev, 843 "corrupted frame received len %d\n", (int)len); 844 len = IEEE802154_MTU; 845 } 846 847 skb = dev_alloc_skb(len); 848 if (!skb) { 849 adf7242_cmd(lp, CMD_RC_RX); 850 return -ENOMEM; 851 } 852 853 data = skb_put(skb, len); 854 ret = adf7242_read_fbuf(lp, data, len, true); 855 if (ret < 0) { 856 kfree_skb(skb); 857 adf7242_cmd(lp, CMD_RC_RX); 858 return ret; 859 } 860 861 lqi = data[len - 2]; 862 lp->rssi = data[len - 1]; 863 864 adf7242_cmd(lp, CMD_RC_RX); 865 866 skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */ 867 868 ieee802154_rx_irqsafe(lp->hw, skb, lqi); 869 870 dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n", 871 __func__, ret, (int)len, (int)lqi, lp->rssi); 872 873 return 0; 874 } 875 876 static const struct ieee802154_ops adf7242_ops = { 877 .owner = THIS_MODULE, 878 .xmit_sync = adf7242_xmit, 879 .ed = adf7242_ed, 880 .set_channel = adf7242_channel, 881 .set_hw_addr_filt = adf7242_set_hw_addr_filt, 882 .start = adf7242_start, 883 .stop = adf7242_stop, 884 .set_csma_params = adf7242_set_csma_params, 885 .set_frame_retries = adf7242_set_frame_retries, 886 .set_txpower = adf7242_set_txpower, 887 .set_promiscuous_mode = adf7242_set_promiscuous_mode, 888 .set_cca_ed_level = adf7242_set_cca_ed_level, 889 }; 890 891 static void adf7242_debug(u8 irq1) 892 { 893 #ifdef DEBUG 894 u8 stat; 895 896 adf7242_status(lp, &stat); 897 898 dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", 899 __func__, irq1, 900 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 901 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 902 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 903 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 904 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 905 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 906 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 907 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 908 909 dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s%s%s%s%s\n", 910 __func__, stat, 911 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 912 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 913 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 914 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 915 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 916 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 917 #endif 918 } 919 920 static irqreturn_t adf7242_isr(int irq, void *data) 921 { 922 struct adf7242_local *lp = data; 923 unsigned xmit; 924 u8 irq1; 925 926 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__); 927 928 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 929 adf7242_write_reg(lp, REG_IRQ1_SRC1, irq1); 930 931 if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA))) 932 dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n", 933 __func__, irq1); 934 935 adf7242_debug(irq1); 936 937 xmit = test_bit(FLAG_XMIT, &lp->flags); 938 939 if (xmit && (irq1 & IRQ_CSMA_CA)) { 940 if (ADF7242_REPORT_CSMA_CA_STAT) { 941 u8 astat; 942 943 adf7242_read_reg(lp, REG_AUTO_STATUS, &astat); 944 astat &= AUTO_STATUS_MASK; 945 946 dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n", 947 astat, 948 astat == SUCCESS ? "SUCCESS" : "", 949 astat == 950 SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "", 951 astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "", 952 astat == FAILURE_NOACK ? "FAILURE_NOACK" : ""); 953 954 /* save CSMA-CA completion status */ 955 lp->tx_stat = astat; 956 } else { 957 lp->tx_stat = SUCCESS; 958 } 959 complete(&lp->tx_complete); 960 } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) && 961 (irq1 & IRQ_FRAME_VALID)) { 962 adf7242_rx(lp); 963 } else if (!xmit && test_bit(FLAG_START, &lp->flags)) { 964 /* Invalid packet received - drop it and restart */ 965 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n", 966 __func__, __LINE__, irq1); 967 adf7242_cmd(lp, CMD_RC_PHY_RDY); 968 adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); 969 adf7242_cmd(lp, CMD_RC_RX); 970 } else { 971 /* This can only be xmit without IRQ, likely a RX packet. 972 * we get an TX IRQ shortly - do nothing or let the xmit 973 * timeout handle this 974 */ 975 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n", 976 __func__, __LINE__, irq1, xmit); 977 complete(&lp->tx_complete); 978 } 979 980 return IRQ_HANDLED; 981 } 982 983 static int adf7242_soft_reset(struct adf7242_local *lp, int line) 984 { 985 dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line); 986 987 if (test_bit(FLAG_START, &lp->flags)) 988 disable_irq_nosync(lp->spi->irq); 989 990 adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT); 991 usleep_range(200, 250); 992 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 993 adf7242_cmd(lp, CMD_RC_PHY_RDY); 994 adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous); 995 adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be, 996 lp->max_cca_retries); 997 adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); 998 999 if (test_bit(FLAG_START, &lp->flags)) { 1000 enable_irq(lp->spi->irq); 1001 return adf7242_cmd(lp, CMD_RC_RX); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int adf7242_hw_init(struct adf7242_local *lp) 1008 { 1009 int ret; 1010 const struct firmware *fw; 1011 1012 adf7242_cmd(lp, CMD_RC_RESET); 1013 adf7242_cmd(lp, CMD_RC_IDLE); 1014 1015 /* get ADF7242 addon firmware 1016 * build this driver as module 1017 * and place under /lib/firmware/adf7242_firmware.bin 1018 * or compile firmware into the kernel. 1019 */ 1020 ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev); 1021 if (ret) { 1022 dev_err(&lp->spi->dev, 1023 "request_firmware() failed with %d\n", ret); 1024 return ret; 1025 } 1026 1027 ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size); 1028 if (ret) { 1029 dev_err(&lp->spi->dev, 1030 "upload firmware failed with %d\n", ret); 1031 release_firmware(fw); 1032 return ret; 1033 } 1034 1035 ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size); 1036 if (ret) { 1037 dev_err(&lp->spi->dev, 1038 "verify firmware failed with %d\n", ret); 1039 release_firmware(fw); 1040 return ret; 1041 } 1042 1043 adf7242_cmd(lp, CMD_RC_PC_RESET); 1044 1045 release_firmware(fw); 1046 1047 adf7242_write_reg(lp, REG_FFILT_CFG, 1048 ACCEPT_BEACON_FRAMES | 1049 ACCEPT_DATA_FRAMES | 1050 ACCEPT_MACCMD_FRAMES | 1051 ACCEPT_RESERVED_FRAMES); 1052 1053 adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 1054 1055 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 1056 1057 adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1); 1058 adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D); 1059 1060 adf7242_write_reg(lp, REG_IRQ1_EN0, 0); 1061 adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA); 1062 1063 adf7242_write_reg(lp, REG_IRQ1_SRC1, 0xFF); 1064 adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF); 1065 1066 adf7242_cmd(lp, CMD_RC_IDLE); 1067 1068 return 0; 1069 } 1070 1071 static int adf7242_stats_show(struct seq_file *file, void *offset) 1072 { 1073 struct adf7242_local *lp = spi_get_drvdata(file->private); 1074 u8 stat, irq1; 1075 1076 adf7242_status(lp, &stat); 1077 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 1078 1079 seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1, 1080 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 1081 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 1082 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 1083 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 1084 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 1085 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 1086 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 1087 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 1088 1089 seq_printf(file, "STATUS = %X:\n%s\n%s%s%s%s%s\n", stat, 1090 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 1091 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 1092 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 1093 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 1094 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 1095 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 1096 1097 seq_printf(file, "RSSI = %d\n", lp->rssi); 1098 1099 return 0; 1100 } 1101 1102 static int adf7242_debugfs_init(struct adf7242_local *lp) 1103 { 1104 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-"; 1105 struct dentry *stats; 1106 1107 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN); 1108 1109 lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1110 if (IS_ERR_OR_NULL(lp->debugfs_root)) 1111 return PTR_ERR_OR_ZERO(lp->debugfs_root); 1112 1113 stats = debugfs_create_devm_seqfile(&lp->spi->dev, "status", 1114 lp->debugfs_root, 1115 adf7242_stats_show); 1116 return PTR_ERR_OR_ZERO(stats); 1117 1118 return 0; 1119 } 1120 1121 static const s32 adf7242_powers[] = { 1122 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700, 1123 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700, 1124 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600, 1125 }; 1126 1127 static const s32 adf7242_ed_levels[] = { 1128 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, 1129 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, 1130 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, 1131 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, 1132 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, 1133 -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000 1134 }; 1135 1136 static int adf7242_probe(struct spi_device *spi) 1137 { 1138 struct ieee802154_hw *hw; 1139 struct adf7242_local *lp; 1140 int ret, irq_type; 1141 1142 if (!spi->irq) { 1143 dev_err(&spi->dev, "no IRQ specified\n"); 1144 return -EINVAL; 1145 } 1146 1147 hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops); 1148 if (!hw) 1149 return -ENOMEM; 1150 1151 lp = hw->priv; 1152 lp->hw = hw; 1153 lp->spi = spi; 1154 1155 hw->priv = lp; 1156 hw->parent = &spi->dev; 1157 hw->extra_tx_headroom = 0; 1158 1159 /* We support only 2.4 Ghz */ 1160 hw->phy->supported.channels[0] = 0x7FFF800; 1161 1162 hw->flags = IEEE802154_HW_OMIT_CKSUM | 1163 IEEE802154_HW_CSMA_PARAMS | 1164 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT | 1165 IEEE802154_HW_PROMISCUOUS; 1166 1167 hw->phy->flags = WPAN_PHY_FLAG_TXPOWER | 1168 WPAN_PHY_FLAG_CCA_ED_LEVEL | 1169 WPAN_PHY_FLAG_CCA_MODE; 1170 1171 hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY); 1172 1173 hw->phy->supported.cca_ed_levels = adf7242_ed_levels; 1174 hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels); 1175 1176 hw->phy->cca.mode = NL802154_CCA_ENERGY; 1177 1178 hw->phy->supported.tx_powers = adf7242_powers; 1179 hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers); 1180 1181 hw->phy->supported.min_minbe = 0; 1182 hw->phy->supported.max_minbe = 8; 1183 1184 hw->phy->supported.min_maxbe = 3; 1185 hw->phy->supported.max_maxbe = 8; 1186 1187 hw->phy->supported.min_frame_retries = 0; 1188 hw->phy->supported.max_frame_retries = 15; 1189 1190 hw->phy->supported.min_csma_backoffs = 0; 1191 hw->phy->supported.max_csma_backoffs = 5; 1192 1193 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); 1194 1195 mutex_init(&lp->bmux); 1196 init_completion(&lp->tx_complete); 1197 1198 /* Setup Status Message */ 1199 lp->stat_xfer.len = 1; 1200 lp->stat_xfer.tx_buf = &lp->buf_stat_tx; 1201 lp->stat_xfer.rx_buf = &lp->buf_stat_rx; 1202 lp->buf_stat_tx = CMD_SPI_NOP; 1203 1204 spi_message_init(&lp->stat_msg); 1205 spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg); 1206 1207 spi_set_drvdata(spi, lp); 1208 1209 ret = adf7242_hw_init(lp); 1210 if (ret) 1211 goto err_hw_init; 1212 1213 irq_type = irq_get_trigger_type(spi->irq); 1214 if (!irq_type) 1215 irq_type = IRQF_TRIGGER_HIGH; 1216 1217 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr, 1218 irq_type | IRQF_ONESHOT, 1219 dev_name(&spi->dev), lp); 1220 if (ret) 1221 goto err_hw_init; 1222 1223 disable_irq(spi->irq); 1224 1225 ret = ieee802154_register_hw(lp->hw); 1226 if (ret) 1227 goto err_hw_init; 1228 1229 dev_set_drvdata(&spi->dev, lp); 1230 1231 adf7242_debugfs_init(lp); 1232 1233 dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq); 1234 1235 return ret; 1236 1237 err_hw_init: 1238 mutex_destroy(&lp->bmux); 1239 ieee802154_free_hw(lp->hw); 1240 1241 return ret; 1242 } 1243 1244 static int adf7242_remove(struct spi_device *spi) 1245 { 1246 struct adf7242_local *lp = spi_get_drvdata(spi); 1247 1248 if (!IS_ERR_OR_NULL(lp->debugfs_root)) 1249 debugfs_remove_recursive(lp->debugfs_root); 1250 1251 ieee802154_unregister_hw(lp->hw); 1252 mutex_destroy(&lp->bmux); 1253 ieee802154_free_hw(lp->hw); 1254 1255 return 0; 1256 } 1257 1258 static const struct of_device_id adf7242_of_match[] = { 1259 { .compatible = "adi,adf7242", }, 1260 { }, 1261 }; 1262 MODULE_DEVICE_TABLE(of, adf7242_of_match); 1263 1264 static const struct spi_device_id adf7242_device_id[] = { 1265 { .name = "adf7242", }, 1266 { }, 1267 }; 1268 MODULE_DEVICE_TABLE(spi, adf7242_device_id); 1269 1270 static struct spi_driver adf7242_driver = { 1271 .id_table = adf7242_device_id, 1272 .driver = { 1273 .of_match_table = of_match_ptr(adf7242_of_match), 1274 .name = "adf7242", 1275 .owner = THIS_MODULE, 1276 }, 1277 .probe = adf7242_probe, 1278 .remove = adf7242_remove, 1279 }; 1280 1281 module_spi_driver(adf7242_driver); 1282 1283 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1284 MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver"); 1285 MODULE_LICENSE("GPL"); 1286