1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver 4 * 5 * Copyright 2009-2017 Analog Devices Inc. 6 * 7 * https://www.analog.com/ADF7242 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/mutex.h> 15 #include <linux/workqueue.h> 16 #include <linux/spinlock.h> 17 #include <linux/firmware.h> 18 #include <linux/spi/spi.h> 19 #include <linux/skbuff.h> 20 #include <linux/of.h> 21 #include <linux/irq.h> 22 #include <linux/debugfs.h> 23 #include <linux/bitops.h> 24 #include <linux/ieee802154.h> 25 #include <net/mac802154.h> 26 #include <net/cfg802154.h> 27 28 #define FIRMWARE "adf7242_firmware.bin" 29 #define MAX_POLL_LOOPS 200 30 31 /* All Registers */ 32 33 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */ 34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */ 35 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */ 36 #define REG_CCA2 0x106 /* RW CCA mode configuration */ 37 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */ 38 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */ 39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */ 40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */ 41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */ 42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */ 43 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */ 44 #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */ 45 #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */ 46 #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */ 47 #define REG_RC_VAR44 0x13F /* RW RESERVED */ 48 #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */ 49 #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */ 50 #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */ 51 #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */ 52 #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */ 53 #define REG_TX_M 0x306 /* RW TX Mode Register */ 54 #define REG_RX_M 0x307 /* RW RX Mode Register */ 55 #define REG_RRB 0x30C /* R RSSI Readback Register */ 56 #define REG_LRB 0x30D /* R Link Quality Readback Register */ 57 #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */ 58 #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */ 59 #define REG_PRAMPG 0x313 /* RW RESERVED */ 60 #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */ 61 #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */ 62 #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */ 63 #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */ 64 #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */ 65 #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */ 66 #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */ 67 #define REG_PD_AUX 0x31E /* RW Battmon enable */ 68 #define REG_GP_CFG 0x32C /* RW GPIO Configuration */ 69 #define REG_GP_OUT 0x32D /* RW GPIO Configuration */ 70 #define REG_GP_IN 0x32E /* R GPIO Configuration */ 71 #define REG_SYNT 0x335 /* RW bandwidth calibration timers */ 72 #define REG_CAL_CFG 0x33D /* RW Calibration Settings */ 73 #define REG_PA_BIAS 0x36E /* RW PA BIAS */ 74 #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */ 75 #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */ 76 #define REG_CDR_CFG 0x38A /* RW CDR kVCO */ 77 #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */ 78 #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */ 79 #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */ 80 #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */ 81 #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */ 82 #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */ 83 #define REG_PA_CFG 0x3A8 /* RW PA enable */ 84 #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */ 85 #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */ 86 #define REG_ADC_RBK 0x3AE /* R Readback temp */ 87 #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */ 88 #define REG_AGC_MAX 0x3B4 /* RW Slew rate */ 89 #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */ 90 #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */ 91 #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */ 92 #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */ 93 #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */ 94 #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */ 95 #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */ 96 #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */ 97 #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */ 98 #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */ 99 #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */ 100 #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */ 101 #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */ 102 #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */ 103 #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */ 104 #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */ 105 #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */ 106 #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */ 107 #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */ 108 #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */ 109 #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */ 110 #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */ 111 #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */ 112 #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */ 113 #define REG_AFC_RANGE 0x3F9 /* RW AFC range */ 114 #define REG_AFC_READ 0x3FA /* RW Readback frequency error */ 115 116 /* REG_EXTPA_MSC */ 117 #define PA_PWR(x) (((x) & 0xF) << 4) 118 #define EXTPA_BIAS_SRC BIT(3) 119 #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0) 120 121 /* REG_PA_CFG */ 122 #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0) 123 #define PA_DBIAS_HIGH_POWER 21 124 #define PA_DBIAS_LOW_POWER 13 125 126 /* REG_PA_BIAS */ 127 #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1) 128 #define REG_PA_BIAS_DFL BIT(0) 129 #define PA_BIAS_HIGH_POWER 63 130 #define PA_BIAS_LOW_POWER 55 131 132 #define REG_PAN_ID0 0x112 133 #define REG_PAN_ID1 0x113 134 #define REG_SHORT_ADDR_0 0x114 135 #define REG_SHORT_ADDR_1 0x115 136 #define REG_IEEE_ADDR_0 0x116 137 #define REG_IEEE_ADDR_1 0x117 138 #define REG_IEEE_ADDR_2 0x118 139 #define REG_IEEE_ADDR_3 0x119 140 #define REG_IEEE_ADDR_4 0x11A 141 #define REG_IEEE_ADDR_5 0x11B 142 #define REG_IEEE_ADDR_6 0x11C 143 #define REG_IEEE_ADDR_7 0x11D 144 #define REG_FFILT_CFG 0x11E 145 #define REG_AUTO_CFG 0x11F 146 #define REG_AUTO_TX1 0x120 147 #define REG_AUTO_TX2 0x121 148 #define REG_AUTO_STATUS 0x122 149 150 /* REG_FFILT_CFG */ 151 #define ACCEPT_BEACON_FRAMES BIT(0) 152 #define ACCEPT_DATA_FRAMES BIT(1) 153 #define ACCEPT_ACK_FRAMES BIT(2) 154 #define ACCEPT_MACCMD_FRAMES BIT(3) 155 #define ACCEPT_RESERVED_FRAMES BIT(4) 156 #define ACCEPT_ALL_ADDRESS BIT(5) 157 158 /* REG_AUTO_CFG */ 159 #define AUTO_ACK_FRAMEPEND BIT(0) 160 #define IS_PANCOORD BIT(1) 161 #define RX_AUTO_ACK_EN BIT(3) 162 #define CSMA_CA_RX_TURNAROUND BIT(4) 163 164 /* REG_AUTO_TX1 */ 165 #define MAX_FRAME_RETRIES(x) ((x) & 0xF) 166 #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4) 167 168 /* REG_AUTO_TX2 */ 169 #define CSMA_MAX_BE(x) ((x) & 0xF) 170 #define CSMA_MIN_BE(x) (((x) & 0xF) << 4) 171 172 #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */ 173 #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM 174 * starting from the TX packet base address 175 * pointer tx_packet_base 176 */ 177 #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM 178 * starting from RX packet base address 179 * pointer rxpb.rx_packet_base 180 */ 181 #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or 182 * Packet RAM sequentially 183 */ 184 #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or 185 * Packet RAM sequentially 186 */ 187 #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet 188 * RAM as random block 189 */ 190 #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or 191 * Packet RAM random block 192 */ 193 #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current 194 * PRAM page selected 195 */ 196 #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current 197 * PRAM page selected 198 */ 199 #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller 200 * into SLEEP state 201 */ 202 #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller 203 * into IDLE state 204 */ 205 #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller 206 * into PHY_RDY state 207 */ 208 #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller 209 * into RX state 210 */ 211 #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller 212 * into TX state 213 */ 214 #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller 215 * into MEAS state 216 */ 217 #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */ 218 #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access 219 * sequence and frame transmission 220 */ 221 #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */ 222 #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in 223 * the sleep state 224 */ 225 #define CMD_RC_PC_RESET_NO_WAIT (CMD_RC_PC_RESET | BIT(31)) 226 227 /* STATUS */ 228 229 #define STAT_SPI_READY BIT(7) 230 #define STAT_IRQ_STATUS BIT(6) 231 #define STAT_RC_READY BIT(5) 232 #define STAT_CCA_RESULT BIT(4) 233 #define RC_STATUS_IDLE 1 234 #define RC_STATUS_MEAS 2 235 #define RC_STATUS_PHY_RDY 3 236 #define RC_STATUS_RX 4 237 #define RC_STATUS_TX 5 238 #define RC_STATUS_MASK 0xF 239 240 /* AUTO_STATUS */ 241 242 #define SUCCESS 0 243 #define SUCCESS_DATPEND 1 244 #define FAILURE_CSMACA 2 245 #define FAILURE_NOACK 3 246 #define AUTO_STATUS_MASK 0x3 247 248 #define PRAM_PAGESIZE 256 249 250 /* IRQ1 */ 251 252 #define IRQ_CCA_COMPLETE BIT(0) 253 #define IRQ_SFD_RX BIT(1) 254 #define IRQ_SFD_TX BIT(2) 255 #define IRQ_RX_PKT_RCVD BIT(3) 256 #define IRQ_TX_PKT_SENT BIT(4) 257 #define IRQ_FRAME_VALID BIT(5) 258 #define IRQ_ADDRESS_VALID BIT(6) 259 #define IRQ_CSMA_CA BIT(7) 260 261 #define AUTO_TX_TURNAROUND BIT(3) 262 #define ADDON_EN BIT(4) 263 264 #define FLAG_XMIT 0 265 #define FLAG_START 1 266 267 #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */ 268 269 struct adf7242_local { 270 struct spi_device *spi; 271 struct completion tx_complete; 272 struct ieee802154_hw *hw; 273 struct mutex bmux; /* protect SPI messages */ 274 struct spi_message stat_msg; 275 struct spi_transfer stat_xfer; 276 struct dentry *debugfs_root; 277 struct delayed_work work; 278 struct workqueue_struct *wqueue; 279 unsigned long flags; 280 int tx_stat; 281 bool promiscuous; 282 s8 rssi; 283 u8 max_frame_retries; 284 u8 max_cca_retries; 285 u8 max_be; 286 u8 min_be; 287 288 /* DMA (thus cache coherency maintenance) requires the 289 * transfer buffers to live in their own cache lines. 290 */ 291 292 u8 buf[3] ____cacheline_aligned; 293 u8 buf_reg_tx[3]; 294 u8 buf_read_tx[4]; 295 u8 buf_read_rx[4]; 296 u8 buf_stat_rx; 297 u8 buf_stat_tx; 298 u8 buf_cmd; 299 }; 300 301 static int adf7242_soft_reset(struct adf7242_local *lp, int line); 302 303 static int adf7242_status(struct adf7242_local *lp, u8 *stat) 304 { 305 int status; 306 307 mutex_lock(&lp->bmux); 308 status = spi_sync(lp->spi, &lp->stat_msg); 309 *stat = lp->buf_stat_rx; 310 mutex_unlock(&lp->bmux); 311 312 return status; 313 } 314 315 static int adf7242_wait_status(struct adf7242_local *lp, unsigned int status, 316 unsigned int mask, int line) 317 { 318 int cnt = 0, ret = 0; 319 u8 stat; 320 321 do { 322 adf7242_status(lp, &stat); 323 cnt++; 324 } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS)); 325 326 if (cnt >= MAX_POLL_LOOPS) { 327 ret = -ETIMEDOUT; 328 329 if (!(stat & STAT_RC_READY)) { 330 adf7242_soft_reset(lp, line); 331 adf7242_status(lp, &stat); 332 333 if ((stat & mask) == status) 334 ret = 0; 335 } 336 337 if (ret < 0) 338 dev_warn(&lp->spi->dev, 339 "%s:line %d Timeout status 0x%x (%d)\n", 340 __func__, line, stat, cnt); 341 } 342 343 dev_vdbg(&lp->spi->dev, "%s : loops=%d line %d\n", __func__, cnt, line); 344 345 return ret; 346 } 347 348 static int adf7242_wait_rc_ready(struct adf7242_local *lp, int line) 349 { 350 return adf7242_wait_status(lp, STAT_RC_READY | STAT_SPI_READY, 351 STAT_RC_READY | STAT_SPI_READY, line); 352 } 353 354 static int adf7242_wait_spi_ready(struct adf7242_local *lp, int line) 355 { 356 return adf7242_wait_status(lp, STAT_SPI_READY, 357 STAT_SPI_READY, line); 358 } 359 360 static int adf7242_write_fbuf(struct adf7242_local *lp, u8 *data, u8 len) 361 { 362 u8 *buf = lp->buf; 363 int status; 364 struct spi_message msg; 365 struct spi_transfer xfer_head = { 366 .len = 2, 367 .tx_buf = buf, 368 369 }; 370 struct spi_transfer xfer_buf = { 371 .len = len, 372 .tx_buf = data, 373 }; 374 375 spi_message_init(&msg); 376 spi_message_add_tail(&xfer_head, &msg); 377 spi_message_add_tail(&xfer_buf, &msg); 378 379 adf7242_wait_spi_ready(lp, __LINE__); 380 381 mutex_lock(&lp->bmux); 382 buf[0] = CMD_SPI_PKT_WR; 383 buf[1] = len + 2; 384 385 status = spi_sync(lp->spi, &msg); 386 mutex_unlock(&lp->bmux); 387 388 return status; 389 } 390 391 static int adf7242_read_fbuf(struct adf7242_local *lp, 392 u8 *data, size_t len, bool packet_read) 393 { 394 u8 *buf = lp->buf; 395 int status; 396 struct spi_message msg; 397 struct spi_transfer xfer_head = { 398 .len = 3, 399 .tx_buf = buf, 400 .rx_buf = buf, 401 }; 402 struct spi_transfer xfer_buf = { 403 .len = len, 404 .rx_buf = data, 405 }; 406 407 spi_message_init(&msg); 408 spi_message_add_tail(&xfer_head, &msg); 409 spi_message_add_tail(&xfer_buf, &msg); 410 411 adf7242_wait_spi_ready(lp, __LINE__); 412 413 mutex_lock(&lp->bmux); 414 if (packet_read) { 415 buf[0] = CMD_SPI_PKT_RD; 416 buf[1] = CMD_SPI_NOP; 417 buf[2] = 0; /* PHR */ 418 } else { 419 buf[0] = CMD_SPI_PRAM_RD; 420 buf[1] = 0; 421 buf[2] = CMD_SPI_NOP; 422 } 423 424 status = spi_sync(lp->spi, &msg); 425 426 mutex_unlock(&lp->bmux); 427 428 return status; 429 } 430 431 static int adf7242_read_reg(struct adf7242_local *lp, u16 addr, u8 *data) 432 { 433 int status; 434 struct spi_message msg; 435 436 struct spi_transfer xfer = { 437 .len = 4, 438 .tx_buf = lp->buf_read_tx, 439 .rx_buf = lp->buf_read_rx, 440 }; 441 442 adf7242_wait_spi_ready(lp, __LINE__); 443 444 mutex_lock(&lp->bmux); 445 lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr); 446 lp->buf_read_tx[1] = addr; 447 lp->buf_read_tx[2] = CMD_SPI_NOP; 448 lp->buf_read_tx[3] = CMD_SPI_NOP; 449 450 spi_message_init(&msg); 451 spi_message_add_tail(&xfer, &msg); 452 453 status = spi_sync(lp->spi, &msg); 454 if (msg.status) 455 status = msg.status; 456 457 if (!status) 458 *data = lp->buf_read_rx[3]; 459 460 mutex_unlock(&lp->bmux); 461 462 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__, 463 addr, *data); 464 465 return status; 466 } 467 468 static int adf7242_write_reg(struct adf7242_local *lp, u16 addr, u8 data) 469 { 470 int status; 471 472 adf7242_wait_spi_ready(lp, __LINE__); 473 474 mutex_lock(&lp->bmux); 475 lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr); 476 lp->buf_reg_tx[1] = addr; 477 lp->buf_reg_tx[2] = data; 478 status = spi_write(lp->spi, lp->buf_reg_tx, 3); 479 mutex_unlock(&lp->bmux); 480 481 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", 482 __func__, addr, data); 483 484 return status; 485 } 486 487 static int adf7242_cmd(struct adf7242_local *lp, unsigned int cmd) 488 { 489 int status; 490 491 dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd); 492 493 if (cmd != CMD_RC_PC_RESET_NO_WAIT) 494 adf7242_wait_rc_ready(lp, __LINE__); 495 496 mutex_lock(&lp->bmux); 497 lp->buf_cmd = cmd; 498 status = spi_write(lp->spi, &lp->buf_cmd, 1); 499 mutex_unlock(&lp->bmux); 500 501 return status; 502 } 503 504 static int adf7242_upload_firmware(struct adf7242_local *lp, u8 *data, u16 len) 505 { 506 struct spi_message msg; 507 struct spi_transfer xfer_buf = { }; 508 int status, i, page = 0; 509 u8 *buf = lp->buf; 510 511 struct spi_transfer xfer_head = { 512 .len = 2, 513 .tx_buf = buf, 514 }; 515 516 buf[0] = CMD_SPI_PRAM_WR; 517 buf[1] = 0; 518 519 spi_message_init(&msg); 520 spi_message_add_tail(&xfer_head, &msg); 521 spi_message_add_tail(&xfer_buf, &msg); 522 523 for (i = len; i >= 0; i -= PRAM_PAGESIZE) { 524 adf7242_write_reg(lp, REG_PRAMPG, page); 525 526 xfer_buf.len = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 527 xfer_buf.tx_buf = &data[page * PRAM_PAGESIZE]; 528 529 mutex_lock(&lp->bmux); 530 status = spi_sync(lp->spi, &msg); 531 mutex_unlock(&lp->bmux); 532 page++; 533 } 534 535 return status; 536 } 537 538 static int adf7242_verify_firmware(struct adf7242_local *lp, 539 const u8 *data, size_t len) 540 { 541 #ifdef DEBUG 542 int i, j; 543 unsigned int page; 544 u8 *buf = kmalloc(PRAM_PAGESIZE, GFP_KERNEL); 545 546 if (!buf) 547 return -ENOMEM; 548 549 for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) { 550 size_t nb = (i >= PRAM_PAGESIZE) ? PRAM_PAGESIZE : i; 551 552 adf7242_write_reg(lp, REG_PRAMPG, page); 553 adf7242_read_fbuf(lp, buf, nb, false); 554 555 for (j = 0; j < nb; j++) { 556 if (buf[j] != data[page * PRAM_PAGESIZE + j]) { 557 kfree(buf); 558 return -EIO; 559 } 560 } 561 } 562 kfree(buf); 563 #endif 564 return 0; 565 } 566 567 static void adf7242_clear_irqstat(struct adf7242_local *lp) 568 { 569 adf7242_write_reg(lp, REG_IRQ1_SRC1, IRQ_CCA_COMPLETE | IRQ_SFD_RX | 570 IRQ_SFD_TX | IRQ_RX_PKT_RCVD | IRQ_TX_PKT_SENT | 571 IRQ_FRAME_VALID | IRQ_ADDRESS_VALID | IRQ_CSMA_CA); 572 } 573 574 static int adf7242_cmd_rx(struct adf7242_local *lp) 575 { 576 /* Wait until the ACK is sent */ 577 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, RC_STATUS_MASK, __LINE__); 578 adf7242_clear_irqstat(lp); 579 mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400)); 580 581 return adf7242_cmd(lp, CMD_RC_RX); 582 } 583 584 static void adf7242_rx_cal_work(struct work_struct *work) 585 { 586 struct adf7242_local *lp = 587 container_of(work, struct adf7242_local, work.work); 588 589 /* Reissuing RC_RX every 400ms - to adjust for offset 590 * drift in receiver (datasheet page 61, OCL section) 591 */ 592 593 if (!test_bit(FLAG_XMIT, &lp->flags)) { 594 adf7242_cmd(lp, CMD_RC_PHY_RDY); 595 adf7242_cmd_rx(lp); 596 } 597 } 598 599 static int adf7242_set_txpower(struct ieee802154_hw *hw, int mbm) 600 { 601 struct adf7242_local *lp = hw->priv; 602 u8 pwr, bias_ctrl, dbias, tmp; 603 int db = mbm / 100; 604 605 dev_vdbg(&lp->spi->dev, "%s : Power %d dB\n", __func__, db); 606 607 if (db > 5 || db < -26) 608 return -EINVAL; 609 610 db = DIV_ROUND_CLOSEST(db + 29, 2); 611 612 if (db > 15) { 613 dbias = PA_DBIAS_HIGH_POWER; 614 bias_ctrl = PA_BIAS_HIGH_POWER; 615 } else { 616 dbias = PA_DBIAS_LOW_POWER; 617 bias_ctrl = PA_BIAS_LOW_POWER; 618 } 619 620 pwr = clamp_t(u8, db, 3, 15); 621 622 adf7242_read_reg(lp, REG_PA_CFG, &tmp); 623 tmp &= ~PA_BRIDGE_DBIAS(~0); 624 tmp |= PA_BRIDGE_DBIAS(dbias); 625 adf7242_write_reg(lp, REG_PA_CFG, tmp); 626 627 adf7242_read_reg(lp, REG_PA_BIAS, &tmp); 628 tmp &= ~PA_BIAS_CTRL(~0); 629 tmp |= PA_BIAS_CTRL(bias_ctrl); 630 adf7242_write_reg(lp, REG_PA_BIAS, tmp); 631 632 adf7242_read_reg(lp, REG_EXTPA_MSC, &tmp); 633 tmp &= ~PA_PWR(~0); 634 tmp |= PA_PWR(pwr); 635 636 return adf7242_write_reg(lp, REG_EXTPA_MSC, tmp); 637 } 638 639 static int adf7242_set_csma_params(struct ieee802154_hw *hw, u8 min_be, 640 u8 max_be, u8 retries) 641 { 642 struct adf7242_local *lp = hw->priv; 643 int ret; 644 645 dev_vdbg(&lp->spi->dev, "%s : min_be=%d max_be=%d retries=%d\n", 646 __func__, min_be, max_be, retries); 647 648 if (min_be > max_be || max_be > 8 || retries > 5) 649 return -EINVAL; 650 651 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 652 MAX_FRAME_RETRIES(lp->max_frame_retries) | 653 MAX_CCA_RETRIES(retries)); 654 if (ret) 655 return ret; 656 657 lp->max_cca_retries = retries; 658 lp->max_be = max_be; 659 lp->min_be = min_be; 660 661 return adf7242_write_reg(lp, REG_AUTO_TX2, CSMA_MAX_BE(max_be) | 662 CSMA_MIN_BE(min_be)); 663 } 664 665 static int adf7242_set_frame_retries(struct ieee802154_hw *hw, s8 retries) 666 { 667 struct adf7242_local *lp = hw->priv; 668 int ret = 0; 669 670 dev_vdbg(&lp->spi->dev, "%s : Retries = %d\n", __func__, retries); 671 672 if (retries < -1 || retries > 15) 673 return -EINVAL; 674 675 if (retries >= 0) 676 ret = adf7242_write_reg(lp, REG_AUTO_TX1, 677 MAX_FRAME_RETRIES(retries) | 678 MAX_CCA_RETRIES(lp->max_cca_retries)); 679 680 lp->max_frame_retries = retries; 681 682 return ret; 683 } 684 685 static int adf7242_ed(struct ieee802154_hw *hw, u8 *level) 686 { 687 struct adf7242_local *lp = hw->priv; 688 689 *level = lp->rssi; 690 691 dev_vdbg(&lp->spi->dev, "%s :Exit level=%d\n", 692 __func__, *level); 693 694 return 0; 695 } 696 697 static int adf7242_start(struct ieee802154_hw *hw) 698 { 699 struct adf7242_local *lp = hw->priv; 700 701 adf7242_cmd(lp, CMD_RC_PHY_RDY); 702 adf7242_clear_irqstat(lp); 703 enable_irq(lp->spi->irq); 704 set_bit(FLAG_START, &lp->flags); 705 706 return adf7242_cmd_rx(lp); 707 } 708 709 static void adf7242_stop(struct ieee802154_hw *hw) 710 { 711 struct adf7242_local *lp = hw->priv; 712 713 disable_irq(lp->spi->irq); 714 cancel_delayed_work_sync(&lp->work); 715 adf7242_cmd(lp, CMD_RC_IDLE); 716 clear_bit(FLAG_START, &lp->flags); 717 adf7242_clear_irqstat(lp); 718 } 719 720 static int adf7242_channel(struct ieee802154_hw *hw, u8 page, u8 channel) 721 { 722 struct adf7242_local *lp = hw->priv; 723 unsigned long freq; 724 725 dev_dbg(&lp->spi->dev, "%s :Channel=%d\n", __func__, channel); 726 727 might_sleep(); 728 729 WARN_ON(page != 0); 730 WARN_ON(channel < 11); 731 WARN_ON(channel > 26); 732 733 freq = (2405 + 5 * (channel - 11)) * 100; 734 adf7242_cmd(lp, CMD_RC_PHY_RDY); 735 736 adf7242_write_reg(lp, REG_CH_FREQ0, freq); 737 adf7242_write_reg(lp, REG_CH_FREQ1, freq >> 8); 738 adf7242_write_reg(lp, REG_CH_FREQ2, freq >> 16); 739 740 if (test_bit(FLAG_START, &lp->flags)) 741 return adf7242_cmd_rx(lp); 742 else 743 return adf7242_cmd(lp, CMD_RC_PHY_RDY); 744 } 745 746 static int adf7242_set_hw_addr_filt(struct ieee802154_hw *hw, 747 struct ieee802154_hw_addr_filt *filt, 748 unsigned long changed) 749 { 750 struct adf7242_local *lp = hw->priv; 751 u8 reg; 752 753 dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed); 754 755 might_sleep(); 756 757 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { 758 u8 addr[8], i; 759 760 memcpy(addr, &filt->ieee_addr, 8); 761 762 for (i = 0; i < 8; i++) 763 adf7242_write_reg(lp, REG_IEEE_ADDR_0 + i, addr[i]); 764 } 765 766 if (changed & IEEE802154_AFILT_SADDR_CHANGED) { 767 u16 saddr = le16_to_cpu(filt->short_addr); 768 769 adf7242_write_reg(lp, REG_SHORT_ADDR_0, saddr); 770 adf7242_write_reg(lp, REG_SHORT_ADDR_1, saddr >> 8); 771 } 772 773 if (changed & IEEE802154_AFILT_PANID_CHANGED) { 774 u16 pan_id = le16_to_cpu(filt->pan_id); 775 776 adf7242_write_reg(lp, REG_PAN_ID0, pan_id); 777 adf7242_write_reg(lp, REG_PAN_ID1, pan_id >> 8); 778 } 779 780 if (changed & IEEE802154_AFILT_PANC_CHANGED) { 781 adf7242_read_reg(lp, REG_AUTO_CFG, ®); 782 if (filt->pan_coord) 783 reg |= IS_PANCOORD; 784 else 785 reg &= ~IS_PANCOORD; 786 adf7242_write_reg(lp, REG_AUTO_CFG, reg); 787 } 788 789 return 0; 790 } 791 792 static int adf7242_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) 793 { 794 struct adf7242_local *lp = hw->priv; 795 796 dev_dbg(&lp->spi->dev, "%s : mode %d\n", __func__, on); 797 798 lp->promiscuous = on; 799 800 if (on) { 801 adf7242_write_reg(lp, REG_AUTO_CFG, 0); 802 return adf7242_write_reg(lp, REG_FFILT_CFG, 803 ACCEPT_BEACON_FRAMES | 804 ACCEPT_DATA_FRAMES | 805 ACCEPT_MACCMD_FRAMES | 806 ACCEPT_ALL_ADDRESS | 807 ACCEPT_ACK_FRAMES | 808 ACCEPT_RESERVED_FRAMES); 809 } else { 810 adf7242_write_reg(lp, REG_FFILT_CFG, 811 ACCEPT_BEACON_FRAMES | 812 ACCEPT_DATA_FRAMES | 813 ACCEPT_MACCMD_FRAMES | 814 ACCEPT_RESERVED_FRAMES); 815 816 return adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 817 } 818 } 819 820 static int adf7242_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) 821 { 822 struct adf7242_local *lp = hw->priv; 823 s8 level = clamp_t(s8, mbm / 100, S8_MIN, S8_MAX); 824 825 dev_dbg(&lp->spi->dev, "%s : level %d\n", __func__, level); 826 827 return adf7242_write_reg(lp, REG_CCA1, level); 828 } 829 830 static int adf7242_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) 831 { 832 struct adf7242_local *lp = hw->priv; 833 int ret; 834 835 /* ensure existing instances of the IRQ handler have completed */ 836 disable_irq(lp->spi->irq); 837 set_bit(FLAG_XMIT, &lp->flags); 838 cancel_delayed_work_sync(&lp->work); 839 reinit_completion(&lp->tx_complete); 840 adf7242_cmd(lp, CMD_RC_PHY_RDY); 841 adf7242_clear_irqstat(lp); 842 843 ret = adf7242_write_fbuf(lp, skb->data, skb->len); 844 if (ret) 845 goto err; 846 847 ret = adf7242_cmd(lp, CMD_RC_CSMACA); 848 if (ret) 849 goto err; 850 enable_irq(lp->spi->irq); 851 852 ret = wait_for_completion_interruptible_timeout(&lp->tx_complete, 853 HZ / 10); 854 if (ret < 0) 855 goto err; 856 if (ret == 0) { 857 dev_dbg(&lp->spi->dev, "Timeout waiting for TX interrupt\n"); 858 ret = -ETIMEDOUT; 859 goto err; 860 } 861 862 if (lp->tx_stat != SUCCESS) { 863 dev_dbg(&lp->spi->dev, 864 "Error xmit: Retry count exceeded Status=0x%x\n", 865 lp->tx_stat); 866 ret = -ECOMM; 867 } else { 868 ret = 0; 869 } 870 871 err: 872 clear_bit(FLAG_XMIT, &lp->flags); 873 adf7242_cmd_rx(lp); 874 875 return ret; 876 } 877 878 static int adf7242_rx(struct adf7242_local *lp) 879 { 880 struct sk_buff *skb; 881 size_t len; 882 int ret; 883 u8 lqi, len_u8, *data; 884 885 ret = adf7242_read_reg(lp, 0, &len_u8); 886 if (ret) 887 return ret; 888 889 len = len_u8; 890 891 if (!ieee802154_is_valid_psdu_len(len)) { 892 dev_dbg(&lp->spi->dev, 893 "corrupted frame received len %d\n", (int)len); 894 len = IEEE802154_MTU; 895 } 896 897 skb = dev_alloc_skb(len); 898 if (!skb) { 899 adf7242_cmd_rx(lp); 900 return -ENOMEM; 901 } 902 903 data = skb_put(skb, len); 904 ret = adf7242_read_fbuf(lp, data, len, true); 905 if (ret < 0) { 906 kfree_skb(skb); 907 adf7242_cmd_rx(lp); 908 return ret; 909 } 910 911 lqi = data[len - 2]; 912 lp->rssi = data[len - 1]; 913 914 ret = adf7242_cmd_rx(lp); 915 916 skb_trim(skb, len - 2); /* Don't put RSSI/LQI or CRC into the frame */ 917 918 ieee802154_rx_irqsafe(lp->hw, skb, lqi); 919 920 dev_dbg(&lp->spi->dev, "%s: ret=%d len=%d lqi=%d rssi=%d\n", 921 __func__, ret, (int)len, (int)lqi, lp->rssi); 922 923 return ret; 924 } 925 926 static const struct ieee802154_ops adf7242_ops = { 927 .owner = THIS_MODULE, 928 .xmit_sync = adf7242_xmit, 929 .ed = adf7242_ed, 930 .set_channel = adf7242_channel, 931 .set_hw_addr_filt = adf7242_set_hw_addr_filt, 932 .start = adf7242_start, 933 .stop = adf7242_stop, 934 .set_csma_params = adf7242_set_csma_params, 935 .set_frame_retries = adf7242_set_frame_retries, 936 .set_txpower = adf7242_set_txpower, 937 .set_promiscuous_mode = adf7242_set_promiscuous_mode, 938 .set_cca_ed_level = adf7242_set_cca_ed_level, 939 }; 940 941 static void adf7242_debug(struct adf7242_local *lp, u8 irq1) 942 { 943 #ifdef DEBUG 944 u8 stat; 945 946 adf7242_status(lp, &stat); 947 948 dev_dbg(&lp->spi->dev, "%s IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", 949 __func__, irq1, 950 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 951 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 952 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 953 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 954 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 955 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 956 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 957 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 958 959 dev_dbg(&lp->spi->dev, "%s STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", 960 __func__, stat, 961 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY", 962 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR", 963 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 964 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY", 965 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 966 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 967 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 968 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 969 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 970 #endif 971 } 972 973 static irqreturn_t adf7242_isr(int irq, void *data) 974 { 975 struct adf7242_local *lp = data; 976 unsigned int xmit; 977 u8 irq1; 978 979 mod_delayed_work(lp->wqueue, &lp->work, msecs_to_jiffies(400)); 980 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 981 982 if (!(irq1 & (IRQ_RX_PKT_RCVD | IRQ_CSMA_CA))) 983 dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n", 984 __func__, irq1); 985 986 adf7242_debug(lp, irq1); 987 988 xmit = test_bit(FLAG_XMIT, &lp->flags); 989 990 if (xmit && (irq1 & IRQ_CSMA_CA)) { 991 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, 992 RC_STATUS_MASK, __LINE__); 993 994 if (ADF7242_REPORT_CSMA_CA_STAT) { 995 u8 astat; 996 997 adf7242_read_reg(lp, REG_AUTO_STATUS, &astat); 998 astat &= AUTO_STATUS_MASK; 999 1000 dev_dbg(&lp->spi->dev, "AUTO_STATUS = %X:\n%s%s%s%s\n", 1001 astat, 1002 astat == SUCCESS ? "SUCCESS" : "", 1003 astat == 1004 SUCCESS_DATPEND ? "SUCCESS_DATPEND" : "", 1005 astat == FAILURE_CSMACA ? "FAILURE_CSMACA" : "", 1006 astat == FAILURE_NOACK ? "FAILURE_NOACK" : ""); 1007 1008 /* save CSMA-CA completion status */ 1009 lp->tx_stat = astat; 1010 } else { 1011 lp->tx_stat = SUCCESS; 1012 } 1013 complete(&lp->tx_complete); 1014 adf7242_clear_irqstat(lp); 1015 } else if (!xmit && (irq1 & IRQ_RX_PKT_RCVD) && 1016 (irq1 & IRQ_FRAME_VALID)) { 1017 adf7242_rx(lp); 1018 } else if (!xmit && test_bit(FLAG_START, &lp->flags)) { 1019 /* Invalid packet received - drop it and restart */ 1020 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n", 1021 __func__, __LINE__, irq1); 1022 adf7242_cmd(lp, CMD_RC_PHY_RDY); 1023 adf7242_cmd_rx(lp); 1024 } else { 1025 /* This can only be xmit without IRQ, likely a RX packet. 1026 * we get an TX IRQ shortly - do nothing or let the xmit 1027 * timeout handle this 1028 */ 1029 1030 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n", 1031 __func__, __LINE__, irq1, xmit); 1032 adf7242_wait_status(lp, RC_STATUS_PHY_RDY, 1033 RC_STATUS_MASK, __LINE__); 1034 complete(&lp->tx_complete); 1035 adf7242_clear_irqstat(lp); 1036 } 1037 1038 return IRQ_HANDLED; 1039 } 1040 1041 static int adf7242_soft_reset(struct adf7242_local *lp, int line) 1042 { 1043 dev_warn(&lp->spi->dev, "%s (line %d)\n", __func__, line); 1044 1045 if (test_bit(FLAG_START, &lp->flags)) 1046 disable_irq_nosync(lp->spi->irq); 1047 1048 adf7242_cmd(lp, CMD_RC_PC_RESET_NO_WAIT); 1049 usleep_range(200, 250); 1050 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 1051 adf7242_cmd(lp, CMD_RC_PHY_RDY); 1052 adf7242_set_promiscuous_mode(lp->hw, lp->promiscuous); 1053 adf7242_set_csma_params(lp->hw, lp->min_be, lp->max_be, 1054 lp->max_cca_retries); 1055 adf7242_clear_irqstat(lp); 1056 1057 if (test_bit(FLAG_START, &lp->flags)) { 1058 enable_irq(lp->spi->irq); 1059 return adf7242_cmd(lp, CMD_RC_RX); 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int adf7242_hw_init(struct adf7242_local *lp) 1066 { 1067 int ret; 1068 const struct firmware *fw; 1069 1070 adf7242_cmd(lp, CMD_RC_RESET); 1071 adf7242_cmd(lp, CMD_RC_IDLE); 1072 1073 /* get ADF7242 addon firmware 1074 * build this driver as module 1075 * and place under /lib/firmware/adf7242_firmware.bin 1076 * or compile firmware into the kernel. 1077 */ 1078 ret = request_firmware(&fw, FIRMWARE, &lp->spi->dev); 1079 if (ret) { 1080 dev_err(&lp->spi->dev, 1081 "request_firmware() failed with %d\n", ret); 1082 return ret; 1083 } 1084 1085 ret = adf7242_upload_firmware(lp, (u8 *)fw->data, fw->size); 1086 if (ret) { 1087 dev_err(&lp->spi->dev, 1088 "upload firmware failed with %d\n", ret); 1089 release_firmware(fw); 1090 return ret; 1091 } 1092 1093 ret = adf7242_verify_firmware(lp, (u8 *)fw->data, fw->size); 1094 if (ret) { 1095 dev_err(&lp->spi->dev, 1096 "verify firmware failed with %d\n", ret); 1097 release_firmware(fw); 1098 return ret; 1099 } 1100 1101 adf7242_cmd(lp, CMD_RC_PC_RESET); 1102 1103 release_firmware(fw); 1104 1105 adf7242_write_reg(lp, REG_FFILT_CFG, 1106 ACCEPT_BEACON_FRAMES | 1107 ACCEPT_DATA_FRAMES | 1108 ACCEPT_MACCMD_FRAMES | 1109 ACCEPT_RESERVED_FRAMES); 1110 1111 adf7242_write_reg(lp, REG_AUTO_CFG, RX_AUTO_ACK_EN); 1112 1113 adf7242_write_reg(lp, REG_PKT_CFG, ADDON_EN | BIT(2)); 1114 1115 adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1); 1116 adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D); 1117 1118 adf7242_write_reg(lp, REG_IRQ1_EN0, 0); 1119 adf7242_write_reg(lp, REG_IRQ1_EN1, IRQ_RX_PKT_RCVD | IRQ_CSMA_CA); 1120 1121 adf7242_clear_irqstat(lp); 1122 adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF); 1123 1124 adf7242_cmd(lp, CMD_RC_IDLE); 1125 1126 return 0; 1127 } 1128 1129 static int adf7242_stats_show(struct seq_file *file, void *offset) 1130 { 1131 struct adf7242_local *lp = spi_get_drvdata(file->private); 1132 u8 stat, irq1; 1133 1134 adf7242_status(lp, &stat); 1135 adf7242_read_reg(lp, REG_IRQ1_SRC1, &irq1); 1136 1137 seq_printf(file, "IRQ1 = %X:\n%s%s%s%s%s%s%s%s\n", irq1, 1138 irq1 & IRQ_CCA_COMPLETE ? "IRQ_CCA_COMPLETE\n" : "", 1139 irq1 & IRQ_SFD_RX ? "IRQ_SFD_RX\n" : "", 1140 irq1 & IRQ_SFD_TX ? "IRQ_SFD_TX\n" : "", 1141 irq1 & IRQ_RX_PKT_RCVD ? "IRQ_RX_PKT_RCVD\n" : "", 1142 irq1 & IRQ_TX_PKT_SENT ? "IRQ_TX_PKT_SENT\n" : "", 1143 irq1 & IRQ_CSMA_CA ? "IRQ_CSMA_CA\n" : "", 1144 irq1 & IRQ_FRAME_VALID ? "IRQ_FRAME_VALID\n" : "", 1145 irq1 & IRQ_ADDRESS_VALID ? "IRQ_ADDRESS_VALID\n" : ""); 1146 1147 seq_printf(file, "STATUS = %X:\n%s\n%s\n%s\n%s\n%s%s%s%s%s\n", stat, 1148 stat & STAT_SPI_READY ? "SPI_READY" : "SPI_BUSY", 1149 stat & STAT_IRQ_STATUS ? "IRQ_PENDING" : "IRQ_CLEAR", 1150 stat & STAT_RC_READY ? "RC_READY" : "RC_BUSY", 1151 stat & STAT_CCA_RESULT ? "CHAN_IDLE" : "CHAN_BUSY", 1152 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", 1153 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", 1154 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", 1155 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", 1156 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); 1157 1158 seq_printf(file, "RSSI = %d\n", lp->rssi); 1159 1160 return 0; 1161 } 1162 1163 static void adf7242_debugfs_init(struct adf7242_local *lp) 1164 { 1165 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "adf7242-"; 1166 1167 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN); 1168 1169 lp->debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1170 1171 debugfs_create_devm_seqfile(&lp->spi->dev, "status", lp->debugfs_root, 1172 adf7242_stats_show); 1173 } 1174 1175 static const s32 adf7242_powers[] = { 1176 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700, 1177 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700, 1178 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600, 1179 }; 1180 1181 static const s32 adf7242_ed_levels[] = { 1182 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, 1183 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, 1184 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, 1185 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, 1186 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, 1187 -4000, -3900, -3800, -3700, -3600, -3500, -3400, -3200, -3100, -3000 1188 }; 1189 1190 static int adf7242_probe(struct spi_device *spi) 1191 { 1192 struct ieee802154_hw *hw; 1193 struct adf7242_local *lp; 1194 int ret, irq_type; 1195 1196 if (!spi->irq) { 1197 dev_err(&spi->dev, "no IRQ specified\n"); 1198 return -EINVAL; 1199 } 1200 1201 hw = ieee802154_alloc_hw(sizeof(*lp), &adf7242_ops); 1202 if (!hw) 1203 return -ENOMEM; 1204 1205 lp = hw->priv; 1206 lp->hw = hw; 1207 lp->spi = spi; 1208 1209 hw->priv = lp; 1210 hw->parent = &spi->dev; 1211 hw->extra_tx_headroom = 0; 1212 1213 /* We support only 2.4 Ghz */ 1214 hw->phy->supported.channels[0] = 0x7FFF800; 1215 1216 hw->flags = IEEE802154_HW_OMIT_CKSUM | 1217 IEEE802154_HW_CSMA_PARAMS | 1218 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT | 1219 IEEE802154_HW_PROMISCUOUS; 1220 1221 hw->phy->flags = WPAN_PHY_FLAG_TXPOWER | 1222 WPAN_PHY_FLAG_CCA_ED_LEVEL | 1223 WPAN_PHY_FLAG_CCA_MODE; 1224 1225 hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY); 1226 1227 hw->phy->supported.cca_ed_levels = adf7242_ed_levels; 1228 hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(adf7242_ed_levels); 1229 1230 hw->phy->cca.mode = NL802154_CCA_ENERGY; 1231 1232 hw->phy->supported.tx_powers = adf7242_powers; 1233 hw->phy->supported.tx_powers_size = ARRAY_SIZE(adf7242_powers); 1234 1235 hw->phy->supported.min_minbe = 0; 1236 hw->phy->supported.max_minbe = 8; 1237 1238 hw->phy->supported.min_maxbe = 3; 1239 hw->phy->supported.max_maxbe = 8; 1240 1241 hw->phy->supported.min_frame_retries = 0; 1242 hw->phy->supported.max_frame_retries = 15; 1243 1244 hw->phy->supported.min_csma_backoffs = 0; 1245 hw->phy->supported.max_csma_backoffs = 5; 1246 1247 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); 1248 1249 mutex_init(&lp->bmux); 1250 init_completion(&lp->tx_complete); 1251 1252 /* Setup Status Message */ 1253 lp->stat_xfer.len = 1; 1254 lp->stat_xfer.tx_buf = &lp->buf_stat_tx; 1255 lp->stat_xfer.rx_buf = &lp->buf_stat_rx; 1256 lp->buf_stat_tx = CMD_SPI_NOP; 1257 1258 spi_message_init(&lp->stat_msg); 1259 spi_message_add_tail(&lp->stat_xfer, &lp->stat_msg); 1260 1261 spi_set_drvdata(spi, lp); 1262 INIT_DELAYED_WORK(&lp->work, adf7242_rx_cal_work); 1263 lp->wqueue = alloc_ordered_workqueue(dev_name(&spi->dev), 1264 WQ_MEM_RECLAIM); 1265 if (unlikely(!lp->wqueue)) { 1266 ret = -ENOMEM; 1267 goto err_alloc_wq; 1268 } 1269 1270 ret = adf7242_hw_init(lp); 1271 if (ret) 1272 goto err_hw_init; 1273 1274 irq_type = irq_get_trigger_type(spi->irq); 1275 if (!irq_type) 1276 irq_type = IRQF_TRIGGER_HIGH; 1277 1278 ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, adf7242_isr, 1279 irq_type | IRQF_ONESHOT, 1280 dev_name(&spi->dev), lp); 1281 if (ret) 1282 goto err_hw_init; 1283 1284 disable_irq(spi->irq); 1285 1286 ret = ieee802154_register_hw(lp->hw); 1287 if (ret) 1288 goto err_hw_init; 1289 1290 dev_set_drvdata(&spi->dev, lp); 1291 1292 adf7242_debugfs_init(lp); 1293 1294 dev_info(&spi->dev, "mac802154 IRQ-%d registered\n", spi->irq); 1295 1296 return ret; 1297 1298 err_hw_init: 1299 destroy_workqueue(lp->wqueue); 1300 err_alloc_wq: 1301 mutex_destroy(&lp->bmux); 1302 ieee802154_free_hw(lp->hw); 1303 1304 return ret; 1305 } 1306 1307 static void adf7242_remove(struct spi_device *spi) 1308 { 1309 struct adf7242_local *lp = spi_get_drvdata(spi); 1310 1311 debugfs_remove_recursive(lp->debugfs_root); 1312 1313 ieee802154_unregister_hw(lp->hw); 1314 1315 cancel_delayed_work_sync(&lp->work); 1316 destroy_workqueue(lp->wqueue); 1317 1318 mutex_destroy(&lp->bmux); 1319 ieee802154_free_hw(lp->hw); 1320 } 1321 1322 static const struct of_device_id adf7242_of_match[] = { 1323 { .compatible = "adi,adf7242", }, 1324 { .compatible = "adi,adf7241", }, 1325 { }, 1326 }; 1327 MODULE_DEVICE_TABLE(of, adf7242_of_match); 1328 1329 static const struct spi_device_id adf7242_device_id[] = { 1330 { .name = "adf7242", }, 1331 { .name = "adf7241", }, 1332 { }, 1333 }; 1334 MODULE_DEVICE_TABLE(spi, adf7242_device_id); 1335 1336 static struct spi_driver adf7242_driver = { 1337 .id_table = adf7242_device_id, 1338 .driver = { 1339 .of_match_table = adf7242_of_match, 1340 .name = "adf7242", 1341 }, 1342 .probe = adf7242_probe, 1343 .remove = adf7242_remove, 1344 }; 1345 1346 module_spi_driver(adf7242_driver); 1347 1348 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1349 MODULE_DESCRIPTION("ADF7242 IEEE802.15.4 Transceiver Driver"); 1350 MODULE_LICENSE("GPL"); 1351 1352 MODULE_FIRMWARE(FIRMWARE); 1353