xref: /openbmc/linux/drivers/net/fddi/defxx.h (revision 799fb82aa132fa3a3886b7872997a5a84e820062)
1  /*
2   * File Name:
3   *   defxx.h
4   *
5   * Copyright Information:
6   *   Copyright Digital Equipment Corporation 1996.
7   *
8   *   This software may be used and distributed according to the terms of
9   *   the GNU General Public License, incorporated herein by reference.
10   *
11   * Abstract:
12   *   Contains all definitions specified by port specification and required
13   *   by the defxx.c driver.
14   *
15   * The original author:
16   *   LVS	Lawrence V. Stefani <lstefani@yahoo.com>
17   *
18   * Maintainers:
19   *   macro	Maciej W. Rozycki <macro@orcam.me.uk>
20   *
21   * Modification History:
22   *		Date		Name	Description
23   *		16-Aug-96	LVS		Created.
24   *		09-Sep-96	LVS		Added group_prom field.  Moved read/write I/O
25   *							macros to DEFXX.C.
26   *		12-Sep-96	LVS		Removed packet request header pointers.
27   *		04 Aug 2003	macro		Converted to the DMA API.
28   *		23 Oct 2006	macro		Big-endian host support.
29   *		14 Dec 2006	macro		TURBOchannel support.
30   *		10 Mar 2021	macro		Dynamic MMIO vs port I/O.
31   */
32  
33  #ifndef _DEFXX_H_
34  #define _DEFXX_H_
35  
36  /* Define basic types for unsigned chars, shorts, longs */
37  
38  typedef u8	PI_UINT8;
39  typedef u16	PI_UINT16;
40  typedef u32	PI_UINT32;
41  
42  /* Define general structures */
43  
44  typedef struct							/* 64-bit counter */
45  	{
46  	PI_UINT32  ms;
47  	PI_UINT32  ls;
48  	} PI_CNTR;
49  
50  typedef struct							/* LAN address */
51  	{
52  	PI_UINT32  lwrd_0;
53  	PI_UINT32  lwrd_1;
54  	} PI_LAN_ADDR;
55  
56  typedef struct							/* Station ID address */
57  	{
58  	PI_UINT32  octet_7_4;
59  	PI_UINT32  octet_3_0;
60  	} PI_STATION_ID;
61  
62  
63  /* Define general constants */
64  
65  #define PI_ALIGN_K_DESC_BLK	  			8192	/* Descriptor block boundary		*/
66  #define PI_ALIGN_K_CONS_BLK	  	 		64		/* Consumer block boundary		  	*/
67  #define PI_ALIGN_K_CMD_REQ_BUFF  		128	 	/* Xmt Command que buffer alignment */
68  #define PI_ALIGN_K_CMD_RSP_BUFF	 		128	 	/* Rcv Command que buffer alignment */
69  #define PI_ALIGN_K_UNSOL_BUFF	 		128	 	/* Unsol que buffer alignment	   	*/
70  #define PI_ALIGN_K_XMT_DATA_BUFF 		0	   	/* Xmt data que buffer alignment	*/
71  #define PI_ALIGN_K_RCV_DATA_BUFF 		128	 	/* Rcv que buffer alignment			*/
72  
73  /* Define PHY index values */
74  
75  #define PI_PHY_K_S						0		/* Index to S phy */
76  #define PI_PHY_K_A						0		/* Index to A phy */
77  #define PI_PHY_K_B						1		/* Index to B phy */
78  #define PI_PHY_K_MAX					2		/* Max number of phys */
79  
80  /* Define FMC descriptor fields */
81  
82  #define PI_FMC_DESCR_V_SOP				31
83  #define PI_FMC_DESCR_V_EOP				30
84  #define PI_FMC_DESCR_V_FSC				27
85  #define PI_FMC_DESCR_V_FSB_ERROR		26
86  #define PI_FMC_DESCR_V_FSB_ADDR_RECOG	25
87  #define PI_FMC_DESCR_V_FSB_ADDR_COPIED	24
88  #define PI_FMC_DESCR_V_FSB				22
89  #define PI_FMC_DESCR_V_RCC_FLUSH		21
90  #define PI_FMC_DESCR_V_RCC_CRC			20
91  #define PI_FMC_DESCR_V_RCC_RRR			17
92  #define PI_FMC_DESCR_V_RCC_DD			15
93  #define PI_FMC_DESCR_V_RCC_SS			13
94  #define PI_FMC_DESCR_V_RCC				13
95  #define PI_FMC_DESCR_V_LEN				0
96  
97  #define PI_FMC_DESCR_M_SOP				0x80000000
98  #define PI_FMC_DESCR_M_EOP				0x40000000
99  #define PI_FMC_DESCR_M_FSC				0x38000000
100  #define PI_FMC_DESCR_M_FSB_ERROR		0x04000000
101  #define PI_FMC_DESCR_M_FSB_ADDR_RECOG	0x02000000
102  #define PI_FMC_DESCR_M_FSB_ADDR_COPIED	0x01000000
103  #define PI_FMC_DESCR_M_FSB				0x07C00000
104  #define PI_FMC_DESCR_M_RCC_FLUSH		0x00200000
105  #define PI_FMC_DESCR_M_RCC_CRC			0x00100000
106  #define PI_FMC_DESCR_M_RCC_RRR			0x000E0000
107  #define PI_FMC_DESCR_M_RCC_DD			0x00018000
108  #define PI_FMC_DESCR_M_RCC_SS			0x00006000
109  #define PI_FMC_DESCR_M_RCC				0x003FE000
110  #define PI_FMC_DESCR_M_LEN				0x00001FFF
111  
112  #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR	0x01AA
113  
114  #define PI_FMC_DESCR_K_RRR_SUCCESS		0x00
115  #define PI_FMC_DESCR_K_RRR_SA_MATCH		0x01
116  #define PI_FMC_DESCR_K_RRR_DA_MATCH		0x02
117  #define PI_FMC_DESCR_K_RRR_FMC_ABORT	0x03
118  #define PI_FMC_DESCR_K_RRR_LENGTH_BAD	0x04
119  #define PI_FMC_DESCR_K_RRR_FRAGMENT		0x05
120  #define PI_FMC_DESCR_K_RRR_FORMAT_ERR	0x06
121  #define PI_FMC_DESCR_K_RRR_MAC_RESET	0x07
122  
123  #define PI_FMC_DESCR_K_DD_NO_MATCH		0x0
124  #define PI_FMC_DESCR_K_DD_PROMISCUOUS	0x1
125  #define PI_FMC_DESCR_K_DD_CAM_MATCH		0x2
126  #define PI_FMC_DESCR_K_DD_LOCAL_MATCH	0x3
127  
128  #define PI_FMC_DESCR_K_SS_NO_MATCH		0x0
129  #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH	0x1
130  #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE	0x2
131  #define PI_FMC_DESCR_K_SS_LOCAL_MATCH	0x3
132  
133  /* Define some max buffer sizes */
134  
135  #define PI_CMD_REQ_K_SIZE_MAX			512
136  #define PI_CMD_RSP_K_SIZE_MAX			512
137  #define PI_UNSOL_K_SIZE_MAX				512
138  #define PI_SMT_HOST_K_SIZE_MAX			4608		/* 4 1/2 K */
139  #define PI_RCV_DATA_K_SIZE_MAX			4608		/* 4 1/2 K */
140  #define PI_XMT_DATA_K_SIZE_MAX			4608		/* 4 1/2 K */
141  
142  /* Define adapter states */
143  
144  #define PI_STATE_K_RESET				0
145  #define PI_STATE_K_UPGRADE		  		1
146  #define PI_STATE_K_DMA_UNAVAIL			2
147  #define PI_STATE_K_DMA_AVAIL			3
148  #define PI_STATE_K_LINK_AVAIL			4
149  #define PI_STATE_K_LINK_UNAVAIL	 		5
150  #define PI_STATE_K_HALTED		   		6
151  #define PI_STATE_K_RING_MEMBER			7
152  #define PI_STATE_K_NUMBER				8
153  
154  /* Define codes for command type */
155  
156  #define PI_CMD_K_START					0x00
157  #define PI_CMD_K_FILTERS_SET			0x01
158  #define PI_CMD_K_FILTERS_GET			0x02
159  #define PI_CMD_K_CHARS_SET				0x03
160  #define PI_CMD_K_STATUS_CHARS_GET		0x04
161  #define PI_CMD_K_CNTRS_GET				0x05
162  #define PI_CMD_K_CNTRS_SET				0x06
163  #define PI_CMD_K_ADDR_FILTER_SET		0x07
164  #define PI_CMD_K_ADDR_FILTER_GET		0x08
165  #define PI_CMD_K_ERROR_LOG_CLEAR		0x09
166  #define PI_CMD_K_ERROR_LOG_GET			0x0A
167  #define PI_CMD_K_FDDI_MIB_GET			0x0B
168  #define PI_CMD_K_DEC_EXT_MIB_GET		0x0C
169  #define PI_CMD_K_DEVICE_SPECIFIC_GET	0x0D
170  #define PI_CMD_K_SNMP_SET				0x0E
171  #define PI_CMD_K_UNSOL_TEST				0x0F
172  #define PI_CMD_K_SMT_MIB_GET			0x10
173  #define PI_CMD_K_SMT_MIB_SET			0x11
174  #define PI_CMD_K_MAX					0x11	/* Must match last */
175  
176  /* Define item codes for Chars_Set and Filters_Set commands */
177  
178  #define PI_ITEM_K_EOL					0x00 	/* End-of-Item list 		  */
179  #define PI_ITEM_K_T_REQ					0x01 	/* DECnet T_REQ 			  */
180  #define PI_ITEM_K_TVX					0x02 	/* DECnet TVX 				  */
181  #define PI_ITEM_K_RESTRICTED_TOKEN		0x03 	/* DECnet Restricted Token 	  */
182  #define PI_ITEM_K_LEM_THRESHOLD			0x04 	/* DECnet LEM Threshold 	  */
183  #define PI_ITEM_K_RING_PURGER			0x05 	/* DECnet Ring Purger Enable  */
184  #define PI_ITEM_K_CNTR_INTERVAL			0x06 	/* Chars_Set 				  */
185  #define PI_ITEM_K_IND_GROUP_PROM		0x07 	/* Filters_Set 				  */
186  #define PI_ITEM_K_GROUP_PROM			0x08 	/* Filters_Set 				  */
187  #define PI_ITEM_K_BROADCAST				0x09 	/* Filters_Set 				  */
188  #define PI_ITEM_K_SMT_PROM				0x0A 	/* Filters_Set				  */
189  #define PI_ITEM_K_SMT_USER				0x0B 	/* Filters_Set 				  */
190  #define PI_ITEM_K_RESERVED				0x0C 	/* Filters_Set 				  */
191  #define PI_ITEM_K_IMPLEMENTOR			0x0D 	/* Filters_Set 				  */
192  #define PI_ITEM_K_LOOPBACK_MODE			0x0E 	/* Chars_Set 				  */
193  #define PI_ITEM_K_CONFIG_POLICY			0x10 	/* SMTConfigPolicy 			  */
194  #define PI_ITEM_K_CON_POLICY			0x11 	/* SMTConnectionPolicy 		  */
195  #define PI_ITEM_K_T_NOTIFY				0x12 	/* SMTTNotify 				  */
196  #define PI_ITEM_K_STATION_ACTION		0x13 	/* SMTStationAction			  */
197  #define PI_ITEM_K_MAC_PATHS_REQ	   		0x15 	/* MACPathsRequested 		  */
198  #define PI_ITEM_K_MAC_ACTION			0x17 	/* MACAction 				  */
199  #define PI_ITEM_K_CON_POLICIES			0x18 	/* PORTConnectionPolicies	  */
200  #define PI_ITEM_K_PORT_PATHS_REQ		0x19 	/* PORTPathsRequested 		  */
201  #define PI_ITEM_K_MAC_LOOP_TIME			0x1A 	/* PORTMACLoopTime 			  */
202  #define PI_ITEM_K_TB_MAX				0x1B 	/* PORTTBMax 				  */
203  #define PI_ITEM_K_LER_CUTOFF			0x1C 	/* PORTLerCutoff 			  */
204  #define PI_ITEM_K_LER_ALARM				0x1D 	/* PORTLerAlarm 			  */
205  #define PI_ITEM_K_PORT_ACTION			0x1E 	/* PORTAction 				  */
206  #define PI_ITEM_K_FLUSH_TIME			0x20 	/* Chars_Set 				  */
207  #define PI_ITEM_K_MAC_T_REQ				0x29 	/* MACTReq 					  */
208  #define PI_ITEM_K_EMAC_RING_PURGER		0x2A 	/* eMACRingPurgerEnable		  */
209  #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT	0x2B 	/* eMACRestrictedTokenTimeout */
210  #define PI_ITEM_K_FDX_ENB_DIS			0x2C 	/* eFDXEnable				  */
211  #define PI_ITEM_K_MAX					0x2C 	/* Must equal high item		  */
212  
213  /* Values for some of the items */
214  
215  #define PI_K_FALSE						0	   /* Generic false */
216  #define PI_K_TRUE						1	   /* Generic true  */
217  
218  #define PI_SNMP_K_TRUE					1	   /* SNMP true/false values */
219  #define PI_SNMP_K_FALSE					2
220  
221  #define PI_FSTATE_K_BLOCK				0	   /* Filter State */
222  #define PI_FSTATE_K_PASS				1
223  
224  /* Define command return codes */
225  
226  #define PI_RSP_K_SUCCESS				0x00
227  #define PI_RSP_K_FAILURE				0x01
228  #define PI_RSP_K_WARNING				0x02
229  #define PI_RSP_K_LOOP_MODE_BAD			0x03
230  #define PI_RSP_K_ITEM_CODE_BAD			0x04
231  #define PI_RSP_K_TVX_BAD				0x05
232  #define PI_RSP_K_TREQ_BAD				0x06
233  #define PI_RSP_K_TOKEN_BAD				0x07
234  #define PI_RSP_K_NO_EOL					0x0C
235  #define PI_RSP_K_FILTER_STATE_BAD		0x0D
236  #define PI_RSP_K_CMD_TYPE_BAD			0x0E
237  #define PI_RSP_K_ADAPTER_STATE_BAD		0x0F
238  #define PI_RSP_K_RING_PURGER_BAD		0x10
239  #define PI_RSP_K_LEM_THRESHOLD_BAD		0x11
240  #define PI_RSP_K_LOOP_NOT_SUPPORTED		0x12
241  #define PI_RSP_K_FLUSH_TIME_BAD			0x13
242  #define PI_RSP_K_NOT_IMPLEMENTED		0x14
243  #define PI_RSP_K_CONFIG_POLICY_BAD		0x15
244  #define PI_RSP_K_STATION_ACTION_BAD		0x16
245  #define PI_RSP_K_MAC_ACTION_BAD			0x17
246  #define PI_RSP_K_CON_POLICIES_BAD		0x18
247  #define PI_RSP_K_MAC_LOOP_TIME_BAD		0x19
248  #define PI_RSP_K_TB_MAX_BAD				0x1A
249  #define PI_RSP_K_LER_CUTOFF_BAD			0x1B
250  #define PI_RSP_K_LER_ALARM_BAD			0x1C
251  #define PI_RSP_K_MAC_PATHS_REQ_BAD		0x1D
252  #define PI_RSP_K_MAC_T_REQ_BAD			0x1E
253  #define PI_RSP_K_EMAC_RING_PURGER_BAD	0x1F
254  #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD	0x20
255  #define PI_RSP_K_NO_SUCH_ENTRY			0x21
256  #define PI_RSP_K_T_NOTIFY_BAD			0x22
257  #define PI_RSP_K_TR_MAX_EXP_BAD			0x23
258  #define PI_RSP_K_MAC_FRM_ERR_THR_BAD	0x24
259  #define PI_RSP_K_MAX_T_REQ_BAD			0x25
260  #define PI_RSP_K_FDX_ENB_DIS_BAD		0x26
261  #define PI_RSP_K_ITEM_INDEX_BAD			0x27
262  #define PI_RSP_K_PORT_ACTION_BAD		0x28
263  
264  /* Commonly used structures */
265  
266  typedef struct									/* Item list */
267  	{
268  	PI_UINT32  item_code;
269  	PI_UINT32  value;
270  	} PI_ITEM_LIST;
271  
272  typedef struct									/* Response header */
273  	{
274  	PI_UINT32  reserved;
275  	PI_UINT32  cmd_type;
276  	PI_UINT32  status;
277  	} PI_RSP_HEADER;
278  
279  
280  /* Start Command */
281  
282  typedef struct
283  	{
284  	PI_UINT32  cmd_type;
285  	} PI_CMD_START_REQ;
286  
287  /* Start Response */
288  
289  typedef struct
290  	{
291  	PI_RSP_HEADER   header;
292  	} PI_CMD_START_RSP;
293  
294  /* Filters_Set Request */
295  
296  #define PI_CMD_FILTERS_SET_K_ITEMS_MAX  63		/* Fits in a 512 byte buffer */
297  
298  typedef struct
299  	{
300  	PI_UINT32		cmd_type;
301  	PI_ITEM_LIST	item[PI_CMD_FILTERS_SET_K_ITEMS_MAX];
302  	} PI_CMD_FILTERS_SET_REQ;
303  
304  /* Filters_Set Response */
305  
306  typedef struct
307  	{
308  	PI_RSP_HEADER   header;
309  	} PI_CMD_FILTERS_SET_RSP;
310  
311  /* Filters_Get Request */
312  
313  typedef struct
314  	{
315  	PI_UINT32		cmd_type;
316  	} PI_CMD_FILTERS_GET_REQ;
317  
318  /* Filters_Get Response */
319  
320  typedef struct
321  	{
322  	PI_RSP_HEADER   header;
323  	PI_UINT32		ind_group_prom;
324  	PI_UINT32		group_prom;
325  	PI_UINT32		broadcast_all;
326  	PI_UINT32		smt_all;
327  	PI_UINT32		smt_user;
328  	PI_UINT32		reserved_all;
329  	PI_UINT32		implementor_all;
330  	} PI_CMD_FILTERS_GET_RSP;
331  
332  
333  /* Chars_Set Request */
334  
335  #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42		/* Fits in a 512 byte buffer */
336  
337  typedef struct
338  	{
339  	PI_UINT32		cmd_type;
340  	struct							  		/* Item list */
341  		{
342  		PI_UINT32	item_code;
343  		PI_UINT32	value;
344  		PI_UINT32	item_index;
345  		} item[PI_CMD_CHARS_SET_K_ITEMS_MAX];
346  	} PI_CMD_CHARS_SET_REQ;
347  
348  /* Chars_Set Response */
349  
350  typedef struct
351  	{
352  	PI_RSP_HEADER   header;
353  	} PI_CMD_CHARS_SET_RSP;
354  
355  
356  /* SNMP_Set Request */
357  
358  #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42	   	/* Fits in a 512 byte buffer */
359  
360  typedef struct
361  	{
362  	PI_UINT32		cmd_type;
363  	struct							   		/* Item list */
364  		{
365  		PI_UINT32	item_code;
366  		PI_UINT32	value;
367  		PI_UINT32	item_index;
368  		} item[PI_CMD_SNMP_SET_K_ITEMS_MAX];
369  	} PI_CMD_SNMP_SET_REQ;
370  
371  /* SNMP_Set Response */
372  
373  typedef struct
374  	{
375  	PI_RSP_HEADER   header;
376  	} PI_CMD_SNMP_SET_RSP;
377  
378  
379  /* SMT_MIB_Set Request */
380  
381  #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42	/* Max number of items */
382  
383  typedef struct
384  	{
385  	PI_UINT32	cmd_type;
386  	struct
387  		{
388  		PI_UINT32	item_code;
389  		PI_UINT32	value;
390  		PI_UINT32	item_index;
391  		} item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX];
392  	} PI_CMD_SMT_MIB_SET_REQ;
393  
394  /* SMT_MIB_Set Response */
395  
396  typedef struct
397  	{
398  	PI_RSP_HEADER   header;
399  	} PI_CMD_SMT_MIB_SET_RSP;
400  
401  /* SMT_MIB_Get Request */
402  
403  typedef struct
404  	{
405  	PI_UINT32  cmd_type;
406  	} PI_CMD_SMT_MIB_GET_REQ;
407  
408  /* SMT_MIB_Get Response */
409  
410  typedef struct						  /* Refer to ANSI FDDI SMT Rev. 7.3 */
411  	{
412  	PI_RSP_HEADER  header;
413  
414  	/* SMT GROUP */
415  
416  	PI_STATION_ID  	smt_station_id;
417  	PI_UINT32 		smt_op_version_id;
418  	PI_UINT32	   	smt_hi_version_id;
419  	PI_UINT32	   	smt_lo_version_id;
420  	PI_UINT32	   	smt_user_data[8];
421  	PI_UINT32	   	smt_mib_version_id;
422  	PI_UINT32	   	smt_mac_ct;
423  	PI_UINT32	   	smt_non_master_ct;
424  	PI_UINT32	   	smt_master_ct;
425  	PI_UINT32	   	smt_available_paths;
426  	PI_UINT32	   	smt_config_capabilities;
427  	PI_UINT32	   	smt_config_policy;
428  	PI_UINT32	   	smt_connection_policy;
429  	PI_UINT32	   	smt_t_notify;
430  	PI_UINT32	   	smt_stat_rpt_policy;
431  	PI_UINT32	   	smt_trace_max_expiration;
432  	PI_UINT32	   	smt_bypass_present;
433  	PI_UINT32	  	smt_ecm_state;
434  	PI_UINT32	   	smt_cf_state;
435  	PI_UINT32	   	smt_remote_disconnect_flag;
436  	PI_UINT32	   	smt_station_status;
437  	PI_UINT32	   	smt_peer_wrap_flag;
438  	PI_CNTR	   		smt_msg_time_stamp;
439  	PI_CNTR	  		smt_transition_time_stamp;
440  
441  	/* MAC GROUP */
442  
443  	PI_UINT32		mac_frame_status_functions;
444  	PI_UINT32		mac_t_max_capability;
445  	PI_UINT32		mac_tvx_capability;
446  	PI_UINT32		mac_available_paths;
447  	PI_UINT32		mac_current_path;
448  	PI_LAN_ADDR		mac_upstream_nbr;
449  	PI_LAN_ADDR		mac_downstream_nbr;
450  	PI_LAN_ADDR		mac_old_upstream_nbr;
451  	PI_LAN_ADDR		mac_old_downstream_nbr;
452  	PI_UINT32	   	mac_dup_address_test;
453  	PI_UINT32	   	mac_requested_paths;
454  	PI_UINT32	   	mac_downstream_port_type;
455  	PI_LAN_ADDR		mac_smt_address;
456  	PI_UINT32		mac_t_req;
457  	PI_UINT32		mac_t_neg;
458  	PI_UINT32		mac_t_max;
459  	PI_UINT32		mac_tvx_value;
460  	PI_UINT32		mac_frame_error_threshold;
461  	PI_UINT32		mac_frame_error_ratio;
462  	PI_UINT32		mac_rmt_state;
463  	PI_UINT32		mac_da_flag;
464  	PI_UINT32		mac_unda_flag;
465  	PI_UINT32		mac_frame_error_flag;
466  	PI_UINT32		mac_ma_unitdata_available;
467  	PI_UINT32		mac_hardware_present;
468  	PI_UINT32		mac_ma_unitdata_enable;
469  
470  	/* PATH GROUP */
471  
472  	PI_UINT32		path_configuration[8];
473  	PI_UINT32		path_tvx_lower_bound;
474  	PI_UINT32		path_t_max_lower_bound;
475  	PI_UINT32		path_max_t_req;
476  
477  	/* PORT GROUP */
478  
479  	PI_UINT32		port_my_type[PI_PHY_K_MAX];
480  	PI_UINT32		port_neighbor_type[PI_PHY_K_MAX];
481  	PI_UINT32		port_connection_policies[PI_PHY_K_MAX];
482  	PI_UINT32		port_mac_indicated[PI_PHY_K_MAX];
483  	PI_UINT32		port_current_path[PI_PHY_K_MAX];
484  	PI_UINT32		port_requested_paths[PI_PHY_K_MAX];
485  	PI_UINT32		port_mac_placement[PI_PHY_K_MAX];
486  	PI_UINT32		port_available_paths[PI_PHY_K_MAX];
487  	PI_UINT32		port_pmd_class[PI_PHY_K_MAX];
488  	PI_UINT32		port_connection_capabilities[PI_PHY_K_MAX];
489  	PI_UINT32		port_bs_flag[PI_PHY_K_MAX];
490  	PI_UINT32		port_ler_estimate[PI_PHY_K_MAX];
491  	PI_UINT32		port_ler_cutoff[PI_PHY_K_MAX];
492  	PI_UINT32		port_ler_alarm[PI_PHY_K_MAX];
493  	PI_UINT32		port_connect_state[PI_PHY_K_MAX];
494  	PI_UINT32		port_pcm_state[PI_PHY_K_MAX];
495  	PI_UINT32		port_pc_withhold[PI_PHY_K_MAX];
496  	PI_UINT32		port_ler_flag[PI_PHY_K_MAX];
497  	PI_UINT32		port_hardware_present[PI_PHY_K_MAX];
498  
499  	/* GROUP for things that were added later, so must be at the end. */
500  
501  	PI_CNTR	   		path_ring_latency;
502  
503  	} PI_CMD_SMT_MIB_GET_RSP;
504  
505  
506  /*
507   *  Item and group code definitions for SMT 7.3 mandatory objects.  These
508   *  definitions are to be used as appropriate in SMT_MIB_SET commands and
509   *  certain host-sent SMT frames such as PMF Get and Set requests.  The
510   *  codes have been taken from the MIB summary section of ANSI SMT 7.3.
511   */
512  
513  #define PI_GRP_K_SMT_STATION_ID			0x100A
514  #define PI_ITEM_K_SMT_STATION_ID		0x100B
515  #define PI_ITEM_K_SMT_OP_VERS_ID		0x100D
516  #define PI_ITEM_K_SMT_HI_VERS_ID		0x100E
517  #define PI_ITEM_K_SMT_LO_VERS_ID		0x100F
518  #define PI_ITEM_K_SMT_USER_DATA			0x1011
519  #define PI_ITEM_K_SMT_MIB_VERS_ID	  	0x1012
520  
521  #define PI_GRP_K_SMT_STATION_CONFIG		0x1014
522  #define PI_ITEM_K_SMT_MAC_CT			0x1015
523  #define PI_ITEM_K_SMT_NON_MASTER_CT		0x1016
524  #define PI_ITEM_K_SMT_MASTER_CT			0x1017
525  #define PI_ITEM_K_SMT_AVAIL_PATHS		0x1018
526  #define PI_ITEM_K_SMT_CONFIG_CAPS		0x1019
527  #define PI_ITEM_K_SMT_CONFIG_POL		0x101A
528  #define PI_ITEM_K_SMT_CONN_POL			0x101B
529  #define PI_ITEM_K_SMT_T_NOTIFY			0x101D
530  #define PI_ITEM_K_SMT_STAT_POL			0x101E
531  #define PI_ITEM_K_SMT_TR_MAX_EXP		0x101F
532  #define PI_ITEM_K_SMT_PORT_INDEXES		0x1020
533  #define PI_ITEM_K_SMT_MAC_INDEXES		0x1021
534  #define PI_ITEM_K_SMT_BYPASS_PRESENT	0x1022
535  
536  #define PI_GRP_K_SMT_STATUS				0x1028
537  #define PI_ITEM_K_SMT_ECM_STATE			0x1029
538  #define PI_ITEM_K_SMT_CF_STATE		 	0x102A
539  #define PI_ITEM_K_SMT_REM_DISC_FLAG		0x102C
540  #define PI_ITEM_K_SMT_STATION_STATUS	0x102D
541  #define PI_ITEM_K_SMT_PEER_WRAP_FLAG	0x102E
542  
543  #define PI_GRP_K_SMT_MIB_OPERATION	 	0x1032
544  #define PI_ITEM_K_SMT_MSG_TIME_STAMP 	0x1033
545  #define PI_ITEM_K_SMT_TRN_TIME_STAMP 	0x1034
546  
547  #define PI_ITEM_K_SMT_STATION_ACT		0x103C
548  
549  #define PI_GRP_K_MAC_CAPABILITIES	  	0x200A
550  #define PI_ITEM_K_MAC_FRM_STAT_FUNC		0x200B
551  #define PI_ITEM_K_MAC_T_MAX_CAP			0x200D
552  #define PI_ITEM_K_MAC_TVX_CAP		  	0x200E
553  
554  #define PI_GRP_K_MAC_CONFIG				0x2014
555  #define PI_ITEM_K_MAC_AVAIL_PATHS	  	0x2016
556  #define PI_ITEM_K_MAC_CURRENT_PATH	 	0x2017
557  #define PI_ITEM_K_MAC_UP_NBR			0x2018
558  #define PI_ITEM_K_MAC_DOWN_NBR			0x2019
559  #define PI_ITEM_K_MAC_OLD_UP_NBR	 	0x201A
560  #define PI_ITEM_K_MAC_OLD_DOWN_NBR	 	0x201B
561  #define PI_ITEM_K_MAC_DUP_ADDR_TEST		0x201D
562  #define PI_ITEM_K_MAC_REQ_PATHS			0x2020
563  #define PI_ITEM_K_MAC_DOWN_PORT_TYPE   	0x2021
564  #define PI_ITEM_K_MAC_INDEX				0x2022
565  
566  #define PI_GRP_K_MAC_ADDRESS			0x2028
567  #define PI_ITEM_K_MAC_SMT_ADDRESS		0x2029
568  
569  #define PI_GRP_K_MAC_OPERATION			0x2032
570  #define PI_ITEM_K_MAC_TREQ				0x2033
571  #define PI_ITEM_K_MAC_TNEG				0x2034
572  #define PI_ITEM_K_MAC_TMAX				0x2035
573  #define PI_ITEM_K_MAC_TVX_VALUE			0x2036
574  
575  #define PI_GRP_K_MAC_COUNTERS			0x2046
576  #define PI_ITEM_K_MAC_FRAME_CT			0x2047
577  #define PI_ITEM_K_MAC_COPIED_CT			0x2048
578  #define PI_ITEM_K_MAC_TRANSMIT_CT		0x2049
579  #define PI_ITEM_K_MAC_ERROR_CT			0x2051
580  #define PI_ITEM_K_MAC_LOST_CT			0x2052
581  
582  #define PI_GRP_K_MAC_FRM_ERR_COND		0x205A
583  #define PI_ITEM_K_MAC_FRM_ERR_THR		0x205F
584  #define PI_ITEM_K_MAC_FRM_ERR_RAT		0x2060
585  
586  #define PI_GRP_K_MAC_STATUS				0x206E
587  #define PI_ITEM_K_MAC_RMT_STATE			0x206F
588  #define PI_ITEM_K_MAC_DA_FLAG			0x2070
589  #define PI_ITEM_K_MAC_UNDA_FLAG			0x2071
590  #define PI_ITEM_K_MAC_FRM_ERR_FLAG		0x2072
591  #define PI_ITEM_K_MAC_MA_UNIT_AVAIL		0x2074
592  #define PI_ITEM_K_MAC_HW_PRESENT		0x2075
593  #define PI_ITEM_K_MAC_MA_UNIT_ENAB		0x2076
594  
595  #define PI_GRP_K_PATH_CONFIG			0x320A
596  #define PI_ITEM_K_PATH_INDEX			0x320B
597  #define PI_ITEM_K_PATH_CONFIGURATION 	0x3212
598  #define PI_ITEM_K_PATH_TVX_LB			0x3215
599  #define PI_ITEM_K_PATH_T_MAX_LB			0x3216
600  #define PI_ITEM_K_PATH_MAX_T_REQ		0x3217
601  
602  #define PI_GRP_K_PORT_CONFIG			0x400A
603  #define PI_ITEM_K_PORT_MY_TYPE			0x400C
604  #define PI_ITEM_K_PORT_NBR_TYPE			0x400D
605  #define PI_ITEM_K_PORT_CONN_POLS		0x400E
606  #define PI_ITEM_K_PORT_MAC_INDICATED  	0x400F
607  #define PI_ITEM_K_PORT_CURRENT_PATH		0x4010
608  #define PI_ITEM_K_PORT_REQ_PATHS		0x4011
609  #define PI_ITEM_K_PORT_MAC_PLACEMENT 	0x4012
610  #define PI_ITEM_K_PORT_AVAIL_PATHS		0x4013
611  #define PI_ITEM_K_PORT_PMD_CLASS		0x4016
612  #define PI_ITEM_K_PORT_CONN_CAPS		0x4017
613  #define PI_ITEM_K_PORT_INDEX			0x401D
614  
615  #define PI_GRP_K_PORT_OPERATION			0x401E
616  #define PI_ITEM_K_PORT_BS_FLAG		 	0x4021
617  
618  #define PI_GRP_K_PORT_ERR_CNTRS			0x4028
619  #define PI_ITEM_K_PORT_LCT_FAIL_CT	 	0x402A
620  
621  #define PI_GRP_K_PORT_LER			  	0x4032
622  #define PI_ITEM_K_PORT_LER_ESTIMATE		0x4033
623  #define PI_ITEM_K_PORT_LEM_REJ_CT		0x4034
624  #define PI_ITEM_K_PORT_LEM_CT			0x4035
625  #define PI_ITEM_K_PORT_LER_CUTOFF		0x403A
626  #define PI_ITEM_K_PORT_LER_ALARM		0x403B
627  
628  #define PI_GRP_K_PORT_STATUS			0x403C
629  #define PI_ITEM_K_PORT_CONNECT_STATE	0x403D
630  #define PI_ITEM_K_PORT_PCM_STATE		0x403E
631  #define PI_ITEM_K_PORT_PC_WITHHOLD		0x403F
632  #define PI_ITEM_K_PORT_LER_FLAG			0x4040
633  #define PI_ITEM_K_PORT_HW_PRESENT		0x4041
634  
635  #define PI_ITEM_K_PORT_ACT				0x4046
636  
637  /* Addr_Filter_Set Request */
638  
639  #define PI_CMD_ADDR_FILTER_K_SIZE   62
640  
641  typedef struct
642  	{
643  	PI_UINT32	cmd_type;
644  	PI_LAN_ADDR	entry[PI_CMD_ADDR_FILTER_K_SIZE];
645  	} PI_CMD_ADDR_FILTER_SET_REQ;
646  
647  /* Addr_Filter_Set Response */
648  
649  typedef struct
650  	{
651  	PI_RSP_HEADER   header;
652  	} PI_CMD_ADDR_FILTER_SET_RSP;
653  
654  /* Addr_Filter_Get Request */
655  
656  typedef struct
657  	{
658  	PI_UINT32	cmd_type;
659  	} PI_CMD_ADDR_FILTER_GET_REQ;
660  
661  /* Addr_Filter_Get Response */
662  
663  typedef struct
664  	{
665  	PI_RSP_HEADER   header;
666  	PI_LAN_ADDR		entry[PI_CMD_ADDR_FILTER_K_SIZE];
667  	} PI_CMD_ADDR_FILTER_GET_RSP;
668  
669  /* Status_Chars_Get Request */
670  
671  typedef struct
672  	{
673  	PI_UINT32  cmd_type;
674  	} PI_CMD_STATUS_CHARS_GET_REQ;
675  
676  /* Status_Chars_Get Response */
677  
678  typedef struct
679  	{
680  	PI_RSP_HEADER   header;
681  	PI_STATION_ID   station_id;						/* Station */
682  	PI_UINT32		station_type;
683  	PI_UINT32		smt_ver_id;
684  	PI_UINT32		smt_ver_id_max;
685  	PI_UINT32		smt_ver_id_min;
686  	PI_UINT32		station_state;
687  	PI_LAN_ADDR		link_addr;						/* Link */
688  	PI_UINT32		t_req;
689  	PI_UINT32		tvx;
690  	PI_UINT32		token_timeout;
691  	PI_UINT32		purger_enb;
692  	PI_UINT32		link_state;
693  	PI_UINT32		tneg;
694  	PI_UINT32		dup_addr_flag;
695  	PI_LAN_ADDR		una;
696  	PI_LAN_ADDR		una_old;
697  	PI_UINT32		un_dup_addr_flag;
698  	PI_LAN_ADDR		dna;
699  	PI_LAN_ADDR		dna_old;
700  	PI_UINT32		purger_state;
701  	PI_UINT32		fci_mode;
702  	PI_UINT32		error_reason;
703  	PI_UINT32		loopback;
704  	PI_UINT32		ring_latency;
705  	PI_LAN_ADDR		last_dir_beacon_sa;
706  	PI_LAN_ADDR		last_dir_beacon_una;
707  	PI_UINT32		phy_type[PI_PHY_K_MAX];			/* Phy */
708  	PI_UINT32		pmd_type[PI_PHY_K_MAX];
709  	PI_UINT32		lem_threshold[PI_PHY_K_MAX];
710  	PI_UINT32		phy_state[PI_PHY_K_MAX];
711  	PI_UINT32		nbor_phy_type[PI_PHY_K_MAX];
712  	PI_UINT32		link_error_est[PI_PHY_K_MAX];
713  	PI_UINT32		broken_reason[PI_PHY_K_MAX];
714  	PI_UINT32		reject_reason[PI_PHY_K_MAX];
715  	PI_UINT32		cntr_interval;					/* Miscellaneous */
716  	PI_UINT32		module_rev;
717  	PI_UINT32		firmware_rev;
718  	PI_UINT32		mop_device_type;
719  	PI_UINT32		phy_led[PI_PHY_K_MAX];
720  	PI_UINT32		flush_time;
721  	} PI_CMD_STATUS_CHARS_GET_RSP;
722  
723  /* FDDI_MIB_Get Request */
724  
725  typedef struct
726  	{
727  	PI_UINT32  cmd_type;
728  	} PI_CMD_FDDI_MIB_GET_REQ;
729  
730  /* FDDI_MIB_Get Response */
731  
732  typedef struct
733  	{
734  	PI_RSP_HEADER   header;
735  
736  	/* SMT GROUP */
737  
738  	PI_STATION_ID   smt_station_id;
739  	PI_UINT32		smt_op_version_id;
740  	PI_UINT32		smt_hi_version_id;
741  	PI_UINT32		smt_lo_version_id;
742  	PI_UINT32		smt_mac_ct;
743  	PI_UINT32		smt_non_master_ct;
744  	PI_UINT32		smt_master_ct;
745  	PI_UINT32		smt_paths_available;
746  	PI_UINT32		smt_config_capabilities;
747  	PI_UINT32		smt_config_policy;
748  	PI_UINT32		smt_connection_policy;
749  	PI_UINT32		smt_t_notify;
750  	PI_UINT32		smt_status_reporting;
751  	PI_UINT32		smt_ecm_state;
752  	PI_UINT32		smt_cf_state;
753  	PI_UINT32		smt_hold_state;
754  	PI_UINT32		smt_remote_disconnect_flag;
755  	PI_UINT32		smt_station_action;
756  
757  	/* MAC GROUP */
758  
759  	PI_UINT32		mac_frame_status_capabilities;
760  	PI_UINT32		mac_t_max_greatest_lower_bound;
761  	PI_UINT32		mac_tvx_greatest_lower_bound;
762  	PI_UINT32		mac_paths_available;
763  	PI_UINT32		mac_current_path;
764  	PI_LAN_ADDR		mac_upstream_nbr;
765  	PI_LAN_ADDR		mac_old_upstream_nbr;
766  	PI_UINT32		mac_dup_addr_test;
767  	PI_UINT32		mac_paths_requested;
768  	PI_UINT32		mac_downstream_port_type;
769  	PI_LAN_ADDR		mac_smt_address;
770  	PI_UINT32		mac_t_req;
771  	PI_UINT32		mac_t_neg;
772  	PI_UINT32		mac_t_max;
773  	PI_UINT32		mac_tvx_value;
774  	PI_UINT32		mac_t_min;
775  	PI_UINT32		mac_current_frame_status;
776  	/*			  	mac_frame_cts 			*/
777  	/* 				mac_error_cts 			*/
778  	/* 		   		mac_lost_cts 			*/
779  	PI_UINT32		mac_frame_error_threshold;
780  	PI_UINT32		mac_frame_error_ratio;
781  	PI_UINT32		mac_rmt_state;
782  	PI_UINT32		mac_da_flag;
783  	PI_UINT32		mac_una_da_flag;
784  	PI_UINT32		mac_frame_condition;
785  	PI_UINT32		mac_chip_set;
786  	PI_UINT32		mac_action;
787  
788  	/* PATH GROUP => Does not need to be implemented */
789  
790  	/* PORT GROUP */
791  
792  	PI_UINT32		port_pc_type[PI_PHY_K_MAX];
793  	PI_UINT32		port_pc_neighbor[PI_PHY_K_MAX];
794  	PI_UINT32		port_connection_policies[PI_PHY_K_MAX];
795  	PI_UINT32		port_remote_mac_indicated[PI_PHY_K_MAX];
796  	PI_UINT32		port_ce_state[PI_PHY_K_MAX];
797  	PI_UINT32		port_paths_requested[PI_PHY_K_MAX];
798  	PI_UINT32		port_mac_placement[PI_PHY_K_MAX];
799  	PI_UINT32		port_available_paths[PI_PHY_K_MAX];
800  	PI_UINT32		port_mac_loop_time[PI_PHY_K_MAX];
801  	PI_UINT32		port_tb_max[PI_PHY_K_MAX];
802  	PI_UINT32		port_bs_flag[PI_PHY_K_MAX];
803  	/*				port_lct_fail_cts[PI_PHY_K_MAX];	*/
804  	PI_UINT32		port_ler_estimate[PI_PHY_K_MAX];
805  	/*				port_lem_reject_cts[PI_PHY_K_MAX];	*/
806  	/*				port_lem_cts[PI_PHY_K_MAX];		*/
807  	PI_UINT32		port_ler_cutoff[PI_PHY_K_MAX];
808  	PI_UINT32		port_ler_alarm[PI_PHY_K_MAX];
809  	PI_UINT32		port_connect_state[PI_PHY_K_MAX];
810  	PI_UINT32		port_pcm_state[PI_PHY_K_MAX];
811  	PI_UINT32		port_pc_withhold[PI_PHY_K_MAX];
812  	PI_UINT32		port_ler_condition[PI_PHY_K_MAX];
813  	PI_UINT32		port_chip_set[PI_PHY_K_MAX];
814  	PI_UINT32		port_action[PI_PHY_K_MAX];
815  
816  	/* ATTACHMENT GROUP */
817  
818  	PI_UINT32		attachment_class;
819  	PI_UINT32		attachment_ob_present;
820  	PI_UINT32		attachment_imax_expiration;
821  	PI_UINT32		attachment_inserted_status;
822  	PI_UINT32		attachment_insert_policy;
823  
824  	/* CHIP SET GROUP => Does not need to be implemented */
825  
826  	} PI_CMD_FDDI_MIB_GET_RSP;
827  
828  /* DEC_Ext_MIB_Get Request */
829  
830  typedef struct
831  	{
832  	PI_UINT32  cmd_type;
833  	} PI_CMD_DEC_EXT_MIB_GET_REQ;
834  
835  /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */
836  
837  typedef struct
838  	{
839  	PI_RSP_HEADER   header;
840  
841  	/* SMT GROUP */
842  
843  	PI_UINT32		esmt_station_type;
844  
845  	/* MAC GROUP */
846  
847  	PI_UINT32		emac_link_state;
848  	PI_UINT32		emac_ring_purger_state;
849  	PI_UINT32		emac_ring_purger_enable;
850  	PI_UINT32		emac_frame_strip_mode;
851  	PI_UINT32		emac_ring_error_reason;
852  	PI_UINT32		emac_up_nbr_dup_addr_flag;
853  	PI_UINT32		emac_restricted_token_timeout;
854  
855  	/* PORT GROUP */
856  
857  	PI_UINT32		eport_pmd_type[PI_PHY_K_MAX];
858  	PI_UINT32		eport_phy_state[PI_PHY_K_MAX];
859  	PI_UINT32		eport_reject_reason[PI_PHY_K_MAX];
860  
861  	/* FDX (Full-Duplex) GROUP */
862  
863  	PI_UINT32		efdx_enable;				/* Valid only in SMT 7.3 */
864  	PI_UINT32		efdx_op;					/* Valid only in SMT 7.3 */
865  	PI_UINT32		efdx_state;					/* Valid only in SMT 7.3 */
866  
867  	} PI_CMD_DEC_EXT_MIB_GET_RSP;
868  
869  typedef struct
870  	{
871  	PI_CNTR		traces_rcvd;					/* Station */
872  	PI_CNTR		frame_cnt;						/* Link */
873  	PI_CNTR		error_cnt;
874  	PI_CNTR		lost_cnt;
875  	PI_CNTR		octets_rcvd;
876  	PI_CNTR		octets_sent;
877  	PI_CNTR		pdus_rcvd;
878  	PI_CNTR		pdus_sent;
879  	PI_CNTR		mcast_octets_rcvd;
880  	PI_CNTR		mcast_octets_sent;
881  	PI_CNTR		mcast_pdus_rcvd;
882  	PI_CNTR		mcast_pdus_sent;
883  	PI_CNTR		xmt_underruns;
884  	PI_CNTR		xmt_failures;
885  	PI_CNTR		block_check_errors;
886  	PI_CNTR		frame_status_errors;
887  	PI_CNTR		pdu_length_errors;
888  	PI_CNTR		rcv_overruns;
889  	PI_CNTR		user_buff_unavailable;
890  	PI_CNTR		inits_initiated;
891  	PI_CNTR		inits_rcvd;
892  	PI_CNTR		beacons_initiated;
893  	PI_CNTR		dup_addrs;
894  	PI_CNTR		dup_tokens;
895  	PI_CNTR		purge_errors;
896  	PI_CNTR		fci_strip_errors;
897  	PI_CNTR		traces_initiated;
898  	PI_CNTR		directed_beacons_rcvd;
899  	PI_CNTR		emac_frame_alignment_errors;
900  	PI_CNTR		ebuff_errors[PI_PHY_K_MAX];		/* Phy */
901  	PI_CNTR		lct_rejects[PI_PHY_K_MAX];
902  	PI_CNTR		lem_rejects[PI_PHY_K_MAX];
903  	PI_CNTR		link_errors[PI_PHY_K_MAX];
904  	PI_CNTR		connections[PI_PHY_K_MAX];
905  	PI_CNTR		copied_cnt;			 			/* Valid only if using SMT 7.3 */
906  	PI_CNTR		transmit_cnt;					/* Valid only if using SMT 7.3 */
907  	PI_CNTR		tokens;
908  	} PI_CNTR_BLK;
909  
910  /* Counters_Get Request */
911  
912  typedef struct
913  	{
914  	PI_UINT32  cmd_type;
915  	} PI_CMD_CNTRS_GET_REQ;
916  
917  /* Counters_Get Response */
918  
919  typedef struct
920  	{
921  	PI_RSP_HEADER   header;
922  	PI_CNTR		time_since_reset;
923  	PI_CNTR_BLK		cntrs;
924  	} PI_CMD_CNTRS_GET_RSP;
925  
926  /* Counters_Set Request */
927  
928  typedef struct
929  	{
930  	PI_UINT32	cmd_type;
931  	PI_CNTR_BLK	cntrs;
932  	} PI_CMD_CNTRS_SET_REQ;
933  
934  /* Counters_Set Response */
935  
936  typedef struct
937  	{
938  	PI_RSP_HEADER   header;
939  	} PI_CMD_CNTRS_SET_RSP;
940  
941  /* Error_Log_Clear Request */
942  
943  typedef struct
944  	{
945  	PI_UINT32  cmd_type;
946  	} PI_CMD_ERROR_LOG_CLEAR_REQ;
947  
948  /* Error_Log_Clear Response */
949  
950  typedef struct
951  	{
952  	PI_RSP_HEADER   header;
953  	} PI_CMD_ERROR_LOG_CLEAR_RSP;
954  
955  /* Error_Log_Get Request */
956  
957  #define PI_LOG_ENTRY_K_INDEX_MIN	0		/* Minimum index for entry */
958  
959  typedef struct
960  	{
961  	PI_UINT32  cmd_type;
962  	PI_UINT32  entry_index;
963  	} PI_CMD_ERROR_LOG_GET_REQ;
964  
965  /* Error_Log_Get Response */
966  
967  #define PI_K_LOG_FW_SIZE			111		/* Max number of fw longwords */
968  #define PI_K_LOG_DIAG_SIZE	 		6		/* Max number of diag longwords */
969  
970  typedef struct
971  	{
972  	struct
973  		{
974  		PI_UINT32	fru_imp_mask;
975  		PI_UINT32	test_id;
976  		PI_UINT32	reserved[PI_K_LOG_DIAG_SIZE];
977  		} diag;
978  	PI_UINT32		fw[PI_K_LOG_FW_SIZE];
979  	} PI_LOG_ENTRY;
980  
981  typedef struct
982  	{
983  	PI_RSP_HEADER   header;
984  	PI_UINT32		event_status;
985  	PI_UINT32		caller_id;
986  	PI_UINT32		timestamp_l;
987  	PI_UINT32		timestamp_h;
988  	PI_UINT32		write_count;
989  	PI_LOG_ENTRY	entry_info;
990  	} PI_CMD_ERROR_LOG_GET_RSP;
991  
992  /* Define error log related constants and types.					*/
993  /*   Not all of the caller id's can occur.  The only ones currently */
994  /*   implemented are: none, selftest, mfg, fw, console				*/
995  
996  #define PI_LOG_EVENT_STATUS_K_VALID		0	/* Valid Event Status 		*/
997  #define PI_LOG_EVENT_STATUS_K_INVALID	1	/* Invalid Event Status 	*/
998  #define PI_LOG_CALLER_ID_K_NONE		 	0	/* No caller 				*/
999  #define PI_LOG_CALLER_ID_K_SELFTEST	 	1	/* Normal power-up selftest */
1000  #define PI_LOG_CALLER_ID_K_MFG		 	2	/* Mfg power-up selftest 	*/
1001  #define PI_LOG_CALLER_ID_K_ONLINE		3	/* On-line diagnostics 		*/
1002  #define PI_LOG_CALLER_ID_K_HW			4	/* Hardware 				*/
1003  #define PI_LOG_CALLER_ID_K_FW			5	/* Firmware 				*/
1004  #define PI_LOG_CALLER_ID_K_CNS_HW		6	/* CNS firmware 			*/
1005  #define PI_LOG_CALLER_ID_K_CNS_FW		7	/* CNS hardware 			*/
1006  #define PI_LOG_CALLER_ID_K_CONSOLE	 	8   /* Console Caller Id 		*/
1007  
1008  /*
1009   *  Place all DMA commands in the following request and response structures
1010   *  to simplify code.
1011   */
1012  
1013  typedef union
1014  	{
1015  	PI_UINT32					cmd_type;
1016  	PI_CMD_START_REQ			start;
1017  	PI_CMD_FILTERS_SET_REQ		filter_set;
1018  	PI_CMD_FILTERS_GET_REQ		filter_get;
1019  	PI_CMD_CHARS_SET_REQ		char_set;
1020  	PI_CMD_ADDR_FILTER_SET_REQ	addr_filter_set;
1021  	PI_CMD_ADDR_FILTER_GET_REQ	addr_filter_get;
1022  	PI_CMD_STATUS_CHARS_GET_REQ	stat_char_get;
1023  	PI_CMD_CNTRS_GET_REQ		cntrs_get;
1024  	PI_CMD_CNTRS_SET_REQ		cntrs_set;
1025  	PI_CMD_ERROR_LOG_CLEAR_REQ	error_log_clear;
1026  	PI_CMD_ERROR_LOG_GET_REQ	error_log_read;
1027  	PI_CMD_SNMP_SET_REQ			snmp_set;
1028  	PI_CMD_FDDI_MIB_GET_REQ		fddi_mib_get;
1029  	PI_CMD_DEC_EXT_MIB_GET_REQ	dec_mib_get;
1030  	PI_CMD_SMT_MIB_SET_REQ		smt_mib_set;
1031  	PI_CMD_SMT_MIB_GET_REQ		smt_mib_get;
1032  	char						pad[PI_CMD_REQ_K_SIZE_MAX];
1033  	} PI_DMA_CMD_REQ;
1034  
1035  typedef union
1036  	{
1037  	PI_RSP_HEADER				header;
1038  	PI_CMD_START_RSP			start;
1039  	PI_CMD_FILTERS_SET_RSP		filter_set;
1040  	PI_CMD_FILTERS_GET_RSP		filter_get;
1041  	PI_CMD_CHARS_SET_RSP		char_set;
1042  	PI_CMD_ADDR_FILTER_SET_RSP	addr_filter_set;
1043  	PI_CMD_ADDR_FILTER_GET_RSP	addr_filter_get;
1044  	PI_CMD_STATUS_CHARS_GET_RSP	stat_char_get;
1045  	PI_CMD_CNTRS_GET_RSP		cntrs_get;
1046  	PI_CMD_CNTRS_SET_RSP		cntrs_set;
1047  	PI_CMD_ERROR_LOG_CLEAR_RSP	error_log_clear;
1048  	PI_CMD_ERROR_LOG_GET_RSP	error_log_get;
1049  	PI_CMD_SNMP_SET_RSP			snmp_set;
1050  	PI_CMD_FDDI_MIB_GET_RSP		fddi_mib_get;
1051  	PI_CMD_DEC_EXT_MIB_GET_RSP	dec_mib_get;
1052  	PI_CMD_SMT_MIB_SET_RSP		smt_mib_set;
1053  	PI_CMD_SMT_MIB_GET_RSP		smt_mib_get;
1054  	char						pad[PI_CMD_RSP_K_SIZE_MAX];
1055  	} PI_DMA_CMD_RSP;
1056  
1057  typedef union
1058  	{
1059  	PI_DMA_CMD_REQ	request;
1060  	PI_DMA_CMD_RSP	response;
1061  	} PI_DMA_CMD_BUFFER;
1062  
1063  
1064  /* Define format of Consumer Block (resident in host memory) */
1065  
1066  typedef struct
1067  	{
1068  	volatile PI_UINT32	xmt_rcv_data;
1069  	volatile PI_UINT32	reserved_1;
1070  	volatile PI_UINT32	smt_host;
1071  	volatile PI_UINT32	reserved_2;
1072  	volatile PI_UINT32	unsol;
1073  	volatile PI_UINT32	reserved_3;
1074  	volatile PI_UINT32	cmd_rsp;
1075  	volatile PI_UINT32	reserved_4;
1076  	volatile PI_UINT32	cmd_req;
1077  	volatile PI_UINT32	reserved_5;
1078  	} PI_CONSUMER_BLOCK;
1079  
1080  #define PI_CONS_M_RCV_INDEX			0x000000FF
1081  #define PI_CONS_M_XMT_INDEX			0x00FF0000
1082  #define PI_CONS_V_RCV_INDEX			0
1083  #define PI_CONS_V_XMT_INDEX			16
1084  
1085  /* Offsets into consumer block */
1086  
1087  #define PI_CONS_BLK_K_XMT_RCV		0x00
1088  #define PI_CONS_BLK_K_SMT_HOST		0x08
1089  #define PI_CONS_BLK_K_UNSOL			0x10
1090  #define PI_CONS_BLK_K_CMD_RSP		0x18
1091  #define PI_CONS_BLK_K_CMD_REQ		0x20
1092  
1093  /* Offsets into descriptor block */
1094  
1095  #define PI_DESCR_BLK_K_RCV_DATA		0x0000
1096  #define PI_DESCR_BLK_K_XMT_DATA		0x0800
1097  #define PI_DESCR_BLK_K_SMT_HOST 	0x1000
1098  #define PI_DESCR_BLK_K_UNSOL		0x1200
1099  #define PI_DESCR_BLK_K_CMD_RSP		0x1280
1100  #define PI_DESCR_BLK_K_CMD_REQ		0x1300
1101  
1102  /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host)   */
1103  /*   Note a field has been added for later versions of the PDQ to allow for  */
1104  /*   finer granularity of the rcv buffer alignment.  For backwards		 	 */
1105  /*   compatibility, the two bits (which allow the rcv buffer to be longword  */
1106  /*   aligned) have been added at the MBZ bits.  To support previous drivers, */
1107  /*   the MBZ definition is left intact.									  	 */
1108  
1109  typedef struct
1110  	{
1111  	PI_UINT32	long_0;
1112  	PI_UINT32	long_1;
1113  	} PI_RCV_DESCR;
1114  
1115  #define	PI_RCV_DESCR_M_SOP	  		0x80000000
1116  #define PI_RCV_DESCR_M_SEG_LEN_LO 	0x60000000
1117  #define PI_RCV_DESCR_M_MBZ	  		0x60000000
1118  #define PI_RCV_DESCR_M_SEG_LEN		0x1F800000
1119  #define PI_RCV_DESCR_M_SEG_LEN_HI	0x1FF00000
1120  #define PI_RCV_DESCR_M_SEG_CNT	  	0x000F0000
1121  #define PI_RCV_DESCR_M_BUFF_HI	  	0x0000FFFF
1122  
1123  #define	PI_RCV_DESCR_V_SOP	  		31
1124  #define PI_RCV_DESCR_V_SEG_LEN_LO 	29
1125  #define PI_RCV_DESCR_V_MBZ	  		29
1126  #define PI_RCV_DESCR_V_SEG_LEN	  	23
1127  #define PI_RCV_DESCR_V_SEG_LEN_HI 	20
1128  #define PI_RCV_DESCR_V_SEG_CNT	  	16
1129  #define PI_RCV_DESCR_V_BUFF_HI	 	0
1130  
1131  /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */
1132  
1133  typedef struct
1134  	{
1135  	PI_UINT32	long_0;
1136  	PI_UINT32	long_1;
1137  	} PI_XMT_DESCR;
1138  
1139  #define	PI_XMT_DESCR_M_SOP			0x80000000
1140  #define PI_XMT_DESCR_M_EOP			0x40000000
1141  #define PI_XMT_DESCR_M_MBZ			0x20000000
1142  #define PI_XMT_DESCR_M_SEG_LEN		0x1FFF0000
1143  #define PI_XMT_DESCR_M_BUFF_HI		0x0000FFFF
1144  
1145  #define	PI_XMT_DESCR_V_SOP			31
1146  #define	PI_XMT_DESCR_V_EOP			30
1147  #define PI_XMT_DESCR_V_MBZ			29
1148  #define PI_XMT_DESCR_V_SEG_LEN		16
1149  #define PI_XMT_DESCR_V_BUFF_HI		0
1150  
1151  /* Define format of the Descriptor Block (resident in host memory) */
1152  
1153  #define PI_RCV_DATA_K_NUM_ENTRIES			256
1154  #define PI_XMT_DATA_K_NUM_ENTRIES			256
1155  #define PI_SMT_HOST_K_NUM_ENTRIES			64
1156  #define PI_UNSOL_K_NUM_ENTRIES				16
1157  #define PI_CMD_RSP_K_NUM_ENTRIES			16
1158  #define PI_CMD_REQ_K_NUM_ENTRIES			16
1159  
1160  typedef struct
1161  	{
1162  	PI_RCV_DESCR  rcv_data[PI_RCV_DATA_K_NUM_ENTRIES];
1163  	PI_XMT_DESCR  xmt_data[PI_XMT_DATA_K_NUM_ENTRIES];
1164  	PI_RCV_DESCR  smt_host[PI_SMT_HOST_K_NUM_ENTRIES];
1165  	PI_RCV_DESCR  unsol[PI_UNSOL_K_NUM_ENTRIES];
1166  	PI_RCV_DESCR  cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES];
1167  	PI_XMT_DESCR  cmd_req[PI_CMD_REQ_K_NUM_ENTRIES];
1168  	} PI_DESCR_BLOCK;
1169  
1170  /* Define Port Registers - offsets from PDQ Base address */
1171  
1172  #define PI_PDQ_K_REG_PORT_RESET			0x00000000
1173  #define PI_PDQ_K_REG_HOST_DATA			0x00000004
1174  #define PI_PDQ_K_REG_PORT_CTRL			0x00000008
1175  #define PI_PDQ_K_REG_PORT_DATA_A		0x0000000C
1176  #define PI_PDQ_K_REG_PORT_DATA_B		0x00000010
1177  #define PI_PDQ_K_REG_PORT_STATUS		0x00000014
1178  #define PI_PDQ_K_REG_TYPE_0_STATUS 		0x00000018
1179  #define PI_PDQ_K_REG_HOST_INT_ENB	  	0x0000001C
1180  #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 	0x00000020
1181  #define PI_PDQ_K_REG_TYPE_2_PROD		0x00000024
1182  #define PI_PDQ_K_REG_CMD_RSP_PROD		0x00000028
1183  #define PI_PDQ_K_REG_CMD_REQ_PROD		0x0000002C
1184  #define PI_PDQ_K_REG_SMT_HOST_PROD   	0x00000030
1185  #define PI_PDQ_K_REG_UNSOL_PROD			0x00000034
1186  
1187  /* Port Control Register - Command codes for primary commands */
1188  
1189  #define PI_PCTRL_M_CMD_ERROR			0x8000
1190  #define PI_PCTRL_M_BLAST_FLASH			0x4000
1191  #define PI_PCTRL_M_HALT					0x2000
1192  #define PI_PCTRL_M_COPY_DATA			0x1000
1193  #define PI_PCTRL_M_ERROR_LOG_START		0x0800
1194  #define PI_PCTRL_M_ERROR_LOG_READ		0x0400
1195  #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE	0x0200
1196  #define PI_PCTRL_M_INIT					0x0100
1197  #define PI_PCTRL_M_INIT_START		    0x0080
1198  #define PI_PCTRL_M_CONS_BLOCK			0x0040
1199  #define PI_PCTRL_M_UNINIT				0x0020
1200  #define PI_PCTRL_M_RING_MEMBER			0x0010
1201  #define PI_PCTRL_M_MLA					0x0008
1202  #define PI_PCTRL_M_FW_REV_READ			0x0004
1203  #define PI_PCTRL_M_DEV_SPECIFIC			0x0002
1204  #define PI_PCTRL_M_SUB_CMD				0x0001
1205  
1206  /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */
1207  
1208  #define PI_SUB_CMD_K_LINK_UNINIT		0x0001
1209  #define PI_SUB_CMD_K_BURST_SIZE_SET		0x0002
1210  #define PI_SUB_CMD_K_PDQ_REV_GET		0x0004
1211  #define PI_SUB_CMD_K_HW_REV_GET			0x0008
1212  
1213  /* Define some Port Data B values */
1214  
1215  #define PI_PDATA_B_DMA_BURST_SIZE_4	 	0		/* valid values for command */
1216  #define PI_PDATA_B_DMA_BURST_SIZE_8	 	1
1217  #define PI_PDATA_B_DMA_BURST_SIZE_16	2
1218  #define PI_PDATA_B_DMA_BURST_SIZE_32	3		/* not supported on PCI */
1219  #define PI_PDATA_B_DMA_BURST_SIZE_DEF	PI_PDATA_B_DMA_BURST_SIZE_16
1220  
1221  /* Port Data A Reset state */
1222  
1223  #define PI_PDATA_A_RESET_M_UPGRADE		0x00000001
1224  #define PI_PDATA_A_RESET_M_SOFT_RESET	0x00000002
1225  #define PI_PDATA_A_RESET_M_SKIP_ST		0x00000004
1226  
1227  /* Read adapter MLA address port control command constants */
1228  
1229  #define PI_PDATA_A_MLA_K_LO				0
1230  #define PI_PDATA_A_MLA_K_HI				1
1231  
1232  /* Byte Swap values for init command */
1233  
1234  #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR			0x0FFFFE000
1235  #define PI_PDATA_A_INIT_M_RESERVED				0x000001FFC
1236  #define PI_PDATA_A_INIT_M_BSWAP_DATA			0x000000002
1237  #define PI_PDATA_A_INIT_M_BSWAP_LITERAL			0x000000001
1238  
1239  #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR			13
1240  #define PI_PDATA_A_INIT_V_RESERVED				3
1241  #define PI_PDATA_A_INIT_V_BSWAP_DATA			1
1242  #define PI_PDATA_A_INIT_V_BSWAP_LITERAL			0
1243  
1244  /* Port Reset Register */
1245  
1246  #define PI_RESET_M_ASSERT_RESET			1
1247  
1248  /* Port Status register */
1249  
1250  #define PI_PSTATUS_V_RCV_DATA_PENDING	31
1251  #define PI_PSTATUS_V_XMT_DATA_PENDING	30
1252  #define PI_PSTATUS_V_SMT_HOST_PENDING	29
1253  #define PI_PSTATUS_V_UNSOL_PENDING		28
1254  #define PI_PSTATUS_V_CMD_RSP_PENDING	27
1255  #define PI_PSTATUS_V_CMD_REQ_PENDING	26
1256  #define PI_PSTATUS_V_TYPE_0_PENDING		25
1257  #define PI_PSTATUS_V_RESERVED_1			16
1258  #define PI_PSTATUS_V_RESERVED_2			11
1259  #define PI_PSTATUS_V_STATE				8
1260  #define PI_PSTATUS_V_HALT_ID			0
1261  
1262  #define PI_PSTATUS_M_RCV_DATA_PENDING	0x80000000
1263  #define PI_PSTATUS_M_XMT_DATA_PENDING	0x40000000
1264  #define PI_PSTATUS_M_SMT_HOST_PENDING	0x20000000
1265  #define PI_PSTATUS_M_UNSOL_PENDING		0x10000000
1266  #define PI_PSTATUS_M_CMD_RSP_PENDING	0x08000000
1267  #define PI_PSTATUS_M_CMD_REQ_PENDING	0x04000000
1268  #define PI_PSTATUS_M_TYPE_0_PENDING		0x02000000
1269  #define PI_PSTATUS_M_RESERVED_1			0x01FF0000
1270  #define PI_PSTATUS_M_RESERVED_2			0x0000F800
1271  #define PI_PSTATUS_M_STATE				0x00000700
1272  #define PI_PSTATUS_M_HALT_ID			0x000000FF
1273  
1274  /* Define Halt Id's			 					*/
1275  /*   Do not insert into this list, only append. */
1276  
1277  #define PI_HALT_ID_K_SELFTEST_TIMEOUT	0
1278  #define PI_HALT_ID_K_PARITY_ERROR		1
1279  #define PI_HALT_ID_K_HOST_DIR_HALT		2
1280  #define PI_HALT_ID_K_SW_FAULT			3
1281  #define PI_HALT_ID_K_HW_FAULT			4
1282  #define PI_HALT_ID_K_PC_TRACE			5
1283  #define PI_HALT_ID_K_DMA_ERROR			6			/* Host Data has error reg */
1284  #define PI_HALT_ID_K_IMAGE_CRC_ERROR	7   		/* Image is bad, update it */
1285  #define PI_HALT_ID_K_BUS_EXCEPTION	 	8   		/* 68K bus exception	   */
1286  
1287  /* Host Interrupt Enable Register as seen by host */
1288  
1289  #define PI_HOST_INT_M_XMT_DATA_ENB		0x80000000	/* Type 2 Enables */
1290  #define PI_HOST_INT_M_RCV_DATA_ENB		0x40000000
1291  #define PI_HOST_INT_M_SMT_HOST_ENB		0x10000000	/* Type 1 Enables */
1292  #define PI_HOST_INT_M_UNSOL_ENB			0x20000000
1293  #define PI_HOST_INT_M_CMD_RSP_ENB		0x08000000
1294  #define PI_HOST_INT_M_CMD_REQ_ENB		0x04000000
1295  #define	PI_HOST_INT_M_TYPE_1_RESERVED	0x00FF0000
1296  #define	PI_HOST_INT_M_TYPE_0_RESERVED	0x0000FF00	/* Type 0 Enables */
1297  #define PI_HOST_INT_M_1MS				0x00000080
1298  #define PI_HOST_INT_M_20MS				0x00000040
1299  #define PI_HOST_INT_M_CSR_CMD_DONE		0x00000020
1300  #define PI_HOST_INT_M_STATE_CHANGE		0x00000010
1301  #define PI_HOST_INT_M_XMT_FLUSH			0x00000008
1302  #define PI_HOST_INT_M_NXM				0x00000004
1303  #define PI_HOST_INT_M_PM_PAR_ERR		0x00000002
1304  #define PI_HOST_INT_M_BUS_PAR_ERR		0x00000001
1305  
1306  #define PI_HOST_INT_V_XMT_DATA_ENB		31			/* Type 2 Enables */
1307  #define PI_HOST_INT_V_RCV_DATA_ENB		30
1308  #define PI_HOST_INT_V_SMT_HOST_ENB		29			/* Type 1 Enables */
1309  #define PI_HOST_INT_V_UNSOL_ENB			28
1310  #define PI_HOST_INT_V_CMD_RSP_ENB		27
1311  #define PI_HOST_INT_V_CMD_REQ_ENB		26
1312  #define	PI_HOST_INT_V_TYPE_1_RESERVED	16
1313  #define	PI_HOST_INT_V_TYPE_0_RESERVED   8			/* Type 0 Enables */
1314  #define PI_HOST_INT_V_1MS_ENB			7
1315  #define PI_HOST_INT_V_20MS_ENB			6
1316  #define PI_HOST_INT_V_CSR_CMD_DONE_ENB	5
1317  #define PI_HOST_INT_V_STATE_CHANGE_ENB	4
1318  #define PI_HOST_INT_V_XMT_FLUSH_ENB 	3
1319  #define PI_HOST_INT_V_NXM_ENB			2
1320  #define PI_HOST_INT_V_PM_PAR_ERR_ENB	1
1321  #define PI_HOST_INT_V_BUS_PAR_ERR_ENB	0
1322  
1323  #define PI_HOST_INT_K_ACK_ALL_TYPE_0	0x000000FF
1324  #define PI_HOST_INT_K_DISABLE_ALL_INTS	0x00000000
1325  #define PI_HOST_INT_K_ENABLE_ALL_INTS	0xFFFFFFFF
1326  #define PI_HOST_INT_K_ENABLE_DEF_INTS	0xC000001F
1327  
1328  /* Type 0 Interrupt Status Register */
1329  
1330  #define PI_TYPE_0_STAT_M_1MS			0x00000080
1331  #define PI_TYPE_0_STAT_M_20MS			0x00000040
1332  #define PI_TYPE_0_STAT_M_CSR_CMD_DONE	0x00000020
1333  #define PI_TYPE_0_STAT_M_STATE_CHANGE	0x00000010
1334  #define PI_TYPE_0_STAT_M_XMT_FLUSH		0x00000008
1335  #define PI_TYPE_0_STAT_M_NXM			0x00000004
1336  #define PI_TYPE_0_STAT_M_PM_PAR_ERR		0x00000002
1337  #define PI_TYPE_0_STAT_M_BUS_PAR_ERR	0x00000001
1338  
1339  #define PI_TYPE_0_STAT_V_1MS			7
1340  #define PI_TYPE_0_STAT_V_20MS			6
1341  #define PI_TYPE_0_STAT_V_CSR_CMD_DONE	5
1342  #define PI_TYPE_0_STAT_V_STATE_CHANGE	4
1343  #define PI_TYPE_0_STAT_V_XMT_FLUSH		3
1344  #define PI_TYPE_0_STAT_V_NXM			2
1345  #define PI_TYPE_0_STAT_V_PM_PAR_ERR		1
1346  #define PI_TYPE_0_STAT_V_BUS_PAR_ERR	0
1347  
1348  /* Register definition structures are defined for both big and little endian systems */
1349  
1350  #ifndef __BIG_ENDIAN
1351  
1352  /* Little endian format of Type 1 Producer register */
1353  
1354  typedef union
1355  	{
1356  	PI_UINT32	lword;
1357  	struct
1358  		{
1359  		PI_UINT8	prod;
1360  		PI_UINT8	comp;
1361  		PI_UINT8	mbz_1;
1362  		PI_UINT8	mbz_2;
1363  		} index;
1364  	} PI_TYPE_1_PROD_REG;
1365  
1366  /* Little endian format of Type 2 Producer register */
1367  
1368  typedef union
1369  	{
1370  	PI_UINT32	lword;
1371  	struct
1372  		{
1373  		PI_UINT8	rcv_prod;
1374  		PI_UINT8	xmt_prod;
1375  		PI_UINT8	rcv_comp;
1376  		PI_UINT8	xmt_comp;
1377  		} index;
1378  	} PI_TYPE_2_PROD_REG;
1379  
1380  /* Little endian format of Type 1 Consumer Block longword */
1381  
1382  typedef union
1383  	{
1384  	PI_UINT32	lword;
1385  	struct
1386  		{
1387  		PI_UINT8	cons;
1388  		PI_UINT8	res0;
1389  		PI_UINT8	res1;
1390  		PI_UINT8	res2;
1391  		} index;
1392  	} PI_TYPE_1_CONSUMER;
1393  
1394  /* Little endian format of Type 2 Consumer Block longword */
1395  
1396  typedef union
1397  	{
1398  	PI_UINT32	lword;
1399  	struct
1400  		{
1401  		PI_UINT8	rcv_cons;
1402  		PI_UINT8	res0;
1403  		PI_UINT8	xmt_cons;
1404  		PI_UINT8	res1;
1405  		} index;
1406  	} PI_TYPE_2_CONSUMER;
1407  
1408  /* Define swapping required by DMA transfers.  */
1409  #define PI_PDATA_A_INIT_M_BSWAP_INIT	\
1410  	(PI_PDATA_A_INIT_M_BSWAP_DATA)
1411  
1412  #else /* __BIG_ENDIAN */
1413  
1414  /* Big endian format of Type 1 Producer register */
1415  
1416  typedef union
1417  	{
1418  	PI_UINT32	lword;
1419  	struct
1420  		{
1421  		PI_UINT8	mbz_2;
1422  		PI_UINT8	mbz_1;
1423  		PI_UINT8	comp;
1424  		PI_UINT8	prod;
1425  		} index;
1426  	} PI_TYPE_1_PROD_REG;
1427  
1428  /* Big endian format of Type 2 Producer register */
1429  
1430  typedef union
1431  	{
1432  	PI_UINT32	lword;
1433  	struct
1434  		{
1435  		PI_UINT8	xmt_comp;
1436  		PI_UINT8	rcv_comp;
1437  		PI_UINT8	xmt_prod;
1438  		PI_UINT8	rcv_prod;
1439  		} index;
1440  	} PI_TYPE_2_PROD_REG;
1441  
1442  /* Big endian format of Type 1 Consumer Block longword */
1443  
1444  typedef union
1445  	{
1446  	PI_UINT32	lword;
1447  	struct
1448  		{
1449  		PI_UINT8	res2;
1450  		PI_UINT8	res1;
1451  		PI_UINT8	res0;
1452  		PI_UINT8	cons;
1453  		} index;
1454  	} PI_TYPE_1_CONSUMER;
1455  
1456  /* Big endian format of Type 2 Consumer Block longword */
1457  
1458  typedef union
1459  	{
1460  	PI_UINT32	lword;
1461  	struct
1462  		{
1463  		PI_UINT8	res1;
1464  		PI_UINT8	xmt_cons;
1465  		PI_UINT8	res0;
1466  		PI_UINT8	rcv_cons;
1467  		} index;
1468  	} PI_TYPE_2_CONSUMER;
1469  
1470  /* Define swapping required by DMA transfers.  */
1471  #define PI_PDATA_A_INIT_M_BSWAP_INIT	\
1472  	(PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
1473  
1474  #endif /* __BIG_ENDIAN */
1475  
1476  /* Define TC PDQ CSR offset and length */
1477  
1478  #define PI_TC_K_CSR_OFFSET		0x100000
1479  #define PI_TC_K_CSR_LEN			0x40		/* 64 bytes */
1480  
1481  /* Define EISA controller register offsets */
1482  
1483  #define PI_ESIC_K_CSR_IO_LEN		0x40		/* 64 bytes */
1484  #define PI_ESIC_K_BURST_HOLDOFF_LEN	0x04		/* 4 bytes */
1485  #define PI_ESIC_K_ESIC_CSR_LEN		0x40		/* 64 bytes */
1486  
1487  #define PI_DEFEA_K_CSR_IO		0x000
1488  #define PI_DEFEA_K_BURST_HOLDOFF	0x040
1489  #define PI_ESIC_K_ESIC_CSR		0xC80
1490  
1491  #define PI_ESIC_K_SLOT_ID            	0xC80
1492  #define PI_ESIC_K_SLOT_CNTRL		0xC84
1493  #define PI_ESIC_K_MEM_ADD_CMP_0     	0xC85
1494  #define PI_ESIC_K_MEM_ADD_CMP_1     	0xC86
1495  #define PI_ESIC_K_MEM_ADD_CMP_2     	0xC87
1496  #define PI_ESIC_K_MEM_ADD_HI_CMP_0  	0xC88
1497  #define PI_ESIC_K_MEM_ADD_HI_CMP_1  	0xC89
1498  #define PI_ESIC_K_MEM_ADD_HI_CMP_2  	0xC8A
1499  #define PI_ESIC_K_MEM_ADD_MASK_0     	0xC8B
1500  #define PI_ESIC_K_MEM_ADD_MASK_1     	0xC8C
1501  #define PI_ESIC_K_MEM_ADD_MASK_2     	0xC8D
1502  #define PI_ESIC_K_MEM_ADD_LO_CMP_0  	0xC8E
1503  #define PI_ESIC_K_MEM_ADD_LO_CMP_1  	0xC8F
1504  #define PI_ESIC_K_MEM_ADD_LO_CMP_2  	0xC90
1505  #define PI_ESIC_K_IO_ADD_CMP_0_0	0xC91
1506  #define PI_ESIC_K_IO_ADD_CMP_0_1	0xC92
1507  #define PI_ESIC_K_IO_ADD_CMP_1_0	0xC93
1508  #define PI_ESIC_K_IO_ADD_CMP_1_1	0xC94
1509  #define PI_ESIC_K_IO_ADD_CMP_2_0	0xC95
1510  #define PI_ESIC_K_IO_ADD_CMP_2_1	0xC96
1511  #define PI_ESIC_K_IO_ADD_CMP_3_0	0xC97
1512  #define PI_ESIC_K_IO_ADD_CMP_3_1	0xC98
1513  #define PI_ESIC_K_IO_ADD_MASK_0_0    	0xC99
1514  #define PI_ESIC_K_IO_ADD_MASK_0_1    	0xC9A
1515  #define PI_ESIC_K_IO_ADD_MASK_1_0    	0xC9B
1516  #define PI_ESIC_K_IO_ADD_MASK_1_1    	0xC9C
1517  #define PI_ESIC_K_IO_ADD_MASK_2_0    	0xC9D
1518  #define PI_ESIC_K_IO_ADD_MASK_2_1    	0xC9E
1519  #define PI_ESIC_K_IO_ADD_MASK_3_0    	0xC9F
1520  #define PI_ESIC_K_IO_ADD_MASK_3_1    	0xCA0
1521  #define PI_ESIC_K_MOD_CONFIG_1		0xCA1
1522  #define PI_ESIC_K_MOD_CONFIG_2		0xCA2
1523  #define PI_ESIC_K_MOD_CONFIG_3		0xCA3
1524  #define PI_ESIC_K_MOD_CONFIG_4		0xCA4
1525  #define PI_ESIC_K_MOD_CONFIG_5    	0xCA5
1526  #define PI_ESIC_K_MOD_CONFIG_6		0xCA6
1527  #define PI_ESIC_K_MOD_CONFIG_7		0xCA7
1528  #define PI_ESIC_K_DIP_SWITCH         	0xCA8
1529  #define PI_ESIC_K_IO_CONFIG_STAT_0   	0xCA9
1530  #define PI_ESIC_K_IO_CONFIG_STAT_1   	0xCAA
1531  #define PI_ESIC_K_DMA_CONFIG         	0xCAB
1532  #define PI_ESIC_K_INPUT_PORT         	0xCAC
1533  #define PI_ESIC_K_OUTPUT_PORT        	0xCAD
1534  #define PI_ESIC_K_FUNCTION_CNTRL	0xCAE
1535  
1536  /* Define the bits in the function control register. */
1537  
1538  #define PI_FUNCTION_CNTRL_M_IOCS0	0x01
1539  #define PI_FUNCTION_CNTRL_M_IOCS1	0x02
1540  #define PI_FUNCTION_CNTRL_M_IOCS2	0x04
1541  #define PI_FUNCTION_CNTRL_M_IOCS3	0x08
1542  #define PI_FUNCTION_CNTRL_M_MEMCS0	0x10
1543  #define PI_FUNCTION_CNTRL_M_MEMCS1	0x20
1544  #define PI_FUNCTION_CNTRL_M_DMA		0x80
1545  
1546  /* Define the bits in the slot control register. */
1547  
1548  #define PI_SLOT_CNTRL_M_RESET		0x04	/* Don't use.       */
1549  #define PI_SLOT_CNTRL_M_ERROR		0x02	/* Not implemented. */
1550  #define PI_SLOT_CNTRL_M_ENB		0x01	/* Must be set.     */
1551  
1552  /* Define the bits in the burst holdoff register. */
1553  
1554  #define PI_BURST_HOLDOFF_M_HOLDOFF	0xFC
1555  #define PI_BURST_HOLDOFF_M_RESERVED	0x02
1556  #define PI_BURST_HOLDOFF_M_MEM_MAP	0x01
1557  
1558  #define PI_BURST_HOLDOFF_V_HOLDOFF	2
1559  #define PI_BURST_HOLDOFF_V_RESERVED	1
1560  #define PI_BURST_HOLDOFF_V_MEM_MAP	0
1561  
1562  /* Define the implicit mask of the Memory Address Compare registers.  */
1563  
1564  #define PI_MEM_ADD_MASK_M		0x3ff
1565  
1566  /* Define the fields in the I/O Address Compare and Mask registers.  */
1567  
1568  #define PI_IO_CMP_M_SLOT		0xf0
1569  
1570  #define PI_IO_CMP_V_SLOT		4
1571  
1572  /* Define the fields in the Interrupt Channel Configuration and Status reg */
1573  
1574  #define PI_CONFIG_STAT_0_M_PEND			0x80
1575  #define PI_CONFIG_STAT_0_M_RES_1		0x40
1576  #define PI_CONFIG_STAT_0_M_IREQ_OUT		0x20
1577  #define PI_CONFIG_STAT_0_M_IREQ_IN		0x10
1578  #define PI_CONFIG_STAT_0_M_INT_ENB		0x08
1579  #define PI_CONFIG_STAT_0_M_RES_0		0x04
1580  #define PI_CONFIG_STAT_0_M_IRQ			0x03
1581  
1582  #define PI_CONFIG_STAT_0_V_PEND			7
1583  #define PI_CONFIG_STAT_0_V_RES_1		6
1584  #define PI_CONFIG_STAT_0_V_IREQ_OUT		5
1585  #define PI_CONFIG_STAT_0_V_IREQ_IN		4
1586  #define PI_CONFIG_STAT_0_V_INT_ENB		3
1587  #define PI_CONFIG_STAT_0_V_RES_0		2
1588  #define PI_CONFIG_STAT_0_V_IRQ			0
1589  
1590  #define PI_CONFIG_STAT_0_IRQ_K_9		0
1591  #define PI_CONFIG_STAT_0_IRQ_K_10		1
1592  #define PI_CONFIG_STAT_0_IRQ_K_11		2
1593  #define PI_CONFIG_STAT_0_IRQ_K_15		3
1594  
1595  /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */
1596  
1597  #define DEFEA_PRODUCT_ID	0x0030A310		/* DEC product 300 (no rev)	*/
1598  #define DEFEA_PROD_ID_1		0x0130A310		/* DEC product 300, rev 1	*/
1599  #define DEFEA_PROD_ID_2		0x0230A310		/* DEC product 300, rev 2	*/
1600  #define DEFEA_PROD_ID_3		0x0330A310		/* DEC product 300, rev 3	*/
1601  #define DEFEA_PROD_ID_4		0x0430A310		/* DEC product 300, rev 4	*/
1602  
1603  /**********************************************/
1604  /* Digital PFI Specification v1.0 Definitions */
1605  /**********************************************/
1606  
1607  /* PCI Configuration Space Constants */
1608  
1609  #define PFI_K_LAT_TIMER_DEF			0x88	/* def max master latency timer */
1610  #define PFI_K_LAT_TIMER_MIN			0x20	/* min max master latency timer */
1611  #define PFI_K_CSR_MEM_LEN			0x80	/* 128 bytes */
1612  #define PFI_K_CSR_IO_LEN			0x80	/* 128 bytes */
1613  #define PFI_K_PKT_MEM_LEN			0x10000	/* 64K bytes */
1614  
1615  /* PFI Register Offsets (starting at PDQ Register Base Address) */
1616  
1617  #define PFI_K_REG_RESERVED_0		 0X00000038
1618  #define PFI_K_REG_RESERVED_1		 0X0000003C
1619  #define PFI_K_REG_MODE_CTRL		 0X00000040
1620  #define PFI_K_REG_STATUS		 0X00000044
1621  #define PFI_K_REG_FIFO_WRITE		 0X00000048
1622  #define PFI_K_REG_FIFO_READ		 0X0000004C
1623  
1624  /* PFI Mode Control Register Constants */
1625  
1626  #define PFI_MODE_M_RESERVED		 0XFFFFFFF0
1627  #define PFI_MODE_M_TGT_ABORT_ENB	 0X00000008
1628  #define PFI_MODE_M_PDQ_INT_ENB		 0X00000004
1629  #define PFI_MODE_M_PFI_INT_ENB		 0X00000002
1630  #define PFI_MODE_M_DMA_ENB		 0X00000001
1631  
1632  #define PFI_MODE_V_RESERVED		 4
1633  #define PFI_MODE_V_TGT_ABORT_ENB	 3
1634  #define PFI_MODE_V_PDQ_INT_ENB		 2
1635  #define PFI_MODE_V_PFI_INT_ENB		 1
1636  #define PFI_MODE_V_DMA_ENB		 0
1637  
1638  #define PFI_MODE_K_ALL_DISABLE		 0X00000000
1639  
1640  /* PFI Status Register Constants */
1641  
1642  #define PFI_STATUS_M_RESERVED		 0XFFFFFFC0
1643  #define PFI_STATUS_M_PFI_ERROR		 0X00000020		/* only valid in rev 1 or later PFI */
1644  #define PFI_STATUS_M_PDQ_INT		 0X00000010
1645  #define PFI_STATUS_M_PDQ_DMA_ABORT	 0X00000008
1646  #define PFI_STATUS_M_FIFO_FULL		 0X00000004
1647  #define PFI_STATUS_M_FIFO_EMPTY		 0X00000002
1648  #define PFI_STATUS_M_DMA_IN_PROGRESS	 0X00000001
1649  
1650  #define PFI_STATUS_V_RESERVED		 6
1651  #define PFI_STATUS_V_PFI_ERROR		 5			/* only valid in rev 1 or later PFI */
1652  #define PFI_STATUS_V_PDQ_INT		 4
1653  #define PFI_STATUS_V_PDQ_DMA_ABORT	 3
1654  #define PFI_STATUS_V_FIFO_FULL		 2
1655  #define PFI_STATUS_V_FIFO_EMPTY		 1
1656  #define PFI_STATUS_V_DMA_IN_PROGRESS 0
1657  
1658  #define DFX_FC_PRH2_PRH1_PRH0		0x54003820	/* Packet Request Header bytes + FC */
1659  #define DFX_PRH0_BYTE			0x20		/* Packet Request Header byte 0 */
1660  #define DFX_PRH1_BYTE			0x38		/* Packet Request Header byte 1 */
1661  #define DFX_PRH2_BYTE			0x00		/* Packet Request Header byte 2 */
1662  
1663  /* Driver routine status (return) codes */
1664  
1665  #define DFX_K_SUCCESS			0			/* routine succeeded */
1666  #define DFX_K_FAILURE			1			/* routine failed */
1667  #define DFX_K_OUTSTATE			2			/* bad state for command */
1668  #define DFX_K_HW_TIMEOUT		3			/* command timed out */
1669  
1670  /* Define LLC host receive buffer min/max/default values */
1671  
1672  #define RCV_BUFS_MIN	2					/* minimum pre-allocated receive buffers */
1673  #define RCV_BUFS_MAX	32					/* maximum pre-allocated receive buffers */
1674  #define RCV_BUFS_DEF	8					/* default pre-allocated receive buffers */
1675  
1676  /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */
1677  
1678  #define RCV_BUFF_K_DESCR	0				/* four byte FMC descriptor */
1679  #define RCV_BUFF_K_PADDING	4				/* three null bytes */
1680  #define RCV_BUFF_K_FC		7				/* one byte frame control */
1681  #define RCV_BUFF_K_DA		8				/* six byte destination address */
1682  #define RCV_BUFF_K_SA		14				/* six byte source address */
1683  #define RCV_BUFF_K_DATA		20				/* offset to start of packet data */
1684  
1685  /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */
1686  
1687  #define XMT_BUFF_K_FC		0				/* one byte frame control */
1688  #define XMT_BUFF_K_DA		1				/* six byte destination address */
1689  #define XMT_BUFF_K_SA		7				/* six byte source address */
1690  #define XMT_BUFF_K_DATA		13				/* offset to start of packet data */
1691  
1692  /* Macro for checking a "value" is within a specific range */
1693  
1694  #define IN_RANGE(value,low,high) ((value >= low) && (value <= high))
1695  
1696  /* Only execute special print call when debug driver was built */
1697  
1698  #ifdef DEFXX_DEBUG
1699  #define DBG_printk(args...) printk(args)
1700  #else
1701  #define DBG_printk(args...)
1702  #endif
1703  
1704  /* Define constants for masking/unmasking interrupts */
1705  
1706  #define DFX_MASK_INTERRUPTS		1
1707  #define DFX_UNMASK_INTERRUPTS		0
1708  
1709  /* Define structure for driver transmit descriptor block */
1710  
1711  typedef struct
1712  	{
1713  	struct sk_buff	*p_skb;					/* ptr to skb */
1714  	} XMT_DRIVER_DESCR;
1715  
1716  typedef struct DFX_board_tag
1717  	{
1718  	/* Keep virtual and physical pointers to locked, physically contiguous memory */
1719  
1720  	char				*kmalloced;					/* pci_free_consistent this on unload */
1721  	dma_addr_t			kmalloced_dma;
1722  	/* DMA handle for the above */
1723  	PI_DESCR_BLOCK			*descr_block_virt;				/* PDQ descriptor block virt address */
1724  	dma_addr_t			descr_block_phys;				/* PDQ descriptor block phys address */
1725  	PI_DMA_CMD_REQ			*cmd_req_virt;					/* Command request buffer virt address */
1726  	dma_addr_t			cmd_req_phys;					/* Command request buffer phys address */
1727  	PI_DMA_CMD_RSP			*cmd_rsp_virt;					/* Command response buffer virt address */
1728  	dma_addr_t			cmd_rsp_phys;					/* Command response buffer phys address */
1729  	char				*rcv_block_virt;				/* LLC host receive queue buf blk virt */
1730  	dma_addr_t			rcv_block_phys;					/* LLC host receive queue buf blk phys */
1731  	PI_CONSUMER_BLOCK		*cons_block_virt;				/* PDQ consumer block virt address */
1732  	dma_addr_t			cons_block_phys;				/* PDQ consumer block phys address */
1733  
1734  	/* Keep local copies of Type 1 and Type 2 register data */
1735  
1736  	PI_TYPE_1_PROD_REG		cmd_req_reg;					/* Command Request register */
1737  	PI_TYPE_1_PROD_REG		cmd_rsp_reg;					/* Command Response register */
1738  	PI_TYPE_2_PROD_REG		rcv_xmt_reg;					/* Type 2 (RCV/XMT) register */
1739  
1740  	/* Storage for unicast and multicast address entries in adapter CAM */
1741  
1742  	u8				uc_table[1*FDDI_K_ALEN];
1743  	u32				uc_count;						/* number of unicast addresses */
1744  	u8				mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN];
1745  	u32				mc_count;						/* number of multicast addresses */
1746  
1747  	/* Current packet filter settings */
1748  
1749  	u32				ind_group_prom;					/* LLC individual & group frame prom mode */
1750  	u32				group_prom;					/* LLC group (multicast) frame prom mode */
1751  
1752  	/* Link available flag needed to determine whether to drop outgoing packet requests */
1753  
1754  	u32				link_available;					/* is link available? */
1755  
1756  	/* Resources to indicate reset type when resetting adapter */
1757  
1758  	u32				reset_type;					/* skip or rerun diagnostics */
1759  
1760  	/* Store pointers to receive buffers for queue processing code */
1761  
1762  	char				*p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES];
1763  
1764  	/* Store pointers to transmit buffers for transmit completion code */
1765  
1766  	XMT_DRIVER_DESCR		xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES];
1767  
1768  	/* Transmit spinlocks */
1769  
1770  	spinlock_t			lock;
1771  
1772  	/* Store device, bus-specific, and parameter information for this adapter */
1773  
1774  	struct net_device		*dev;						/* pointer to device structure */
1775  	union {
1776  		void __iomem *mem;
1777  		int port;
1778  	} base;										/* base address */
1779  	struct device			*bus_dev;
1780  	/* Whether to use MMIO or port I/O.  */
1781  	bool				mmio;
1782  	u32				full_duplex_enb;				/* FDDI Full Duplex enable (1 == on, 2 == off) */
1783  	u32				req_ttrt;					/* requested TTRT value (in 80ns units) */
1784  	u32				burst_size;					/* adapter burst size (enumerated) */
1785  	u32				rcv_bufs_to_post;				/* receive buffers to post for LLC host queue */
1786  	u8				factory_mac_addr[FDDI_K_ALEN];			/* factory (on-board) MAC address */
1787  
1788  	/* Common FDDI statistics structure and private counters */
1789  
1790  	struct fddi_statistics	stats;
1791  
1792  	u32				rcv_discards;
1793  	u32				rcv_crc_errors;
1794  	u32				rcv_frame_status_errors;
1795  	u32				rcv_length_errors;
1796  	u32				rcv_total_frames;
1797  	u32				rcv_multicast_frames;
1798  	u32				rcv_total_bytes;
1799  
1800  	u32				xmt_discards;
1801  	u32				xmt_length_errors;
1802  	u32				xmt_total_frames;
1803  	u32				xmt_total_bytes;
1804  	} DFX_board_t;
1805  
1806  #endif	/* #ifndef _DEFXX_H_ */
1807