133f810b2SJeff Kirsher /* 233f810b2SJeff Kirsher * File Name: 333f810b2SJeff Kirsher * defxx.h 433f810b2SJeff Kirsher * 533f810b2SJeff Kirsher * Copyright Information: 633f810b2SJeff Kirsher * Copyright Digital Equipment Corporation 1996. 733f810b2SJeff Kirsher * 833f810b2SJeff Kirsher * This software may be used and distributed according to the terms of 933f810b2SJeff Kirsher * the GNU General Public License, incorporated herein by reference. 1033f810b2SJeff Kirsher * 1133f810b2SJeff Kirsher * Abstract: 1233f810b2SJeff Kirsher * Contains all definitions specified by port specification and required 1333f810b2SJeff Kirsher * by the defxx.c driver. 1433f810b2SJeff Kirsher * 1533f810b2SJeff Kirsher * The original author: 1633f810b2SJeff Kirsher * LVS Lawrence V. Stefani <lstefani@yahoo.com> 1733f810b2SJeff Kirsher * 1833f810b2SJeff Kirsher * Maintainers: 194d248c0dSMaciej W. Rozycki * macro Maciej W. Rozycki <macro@orcam.me.uk> 2033f810b2SJeff Kirsher * 2133f810b2SJeff Kirsher * Modification History: 2233f810b2SJeff Kirsher * Date Name Description 2333f810b2SJeff Kirsher * 16-Aug-96 LVS Created. 2433f810b2SJeff Kirsher * 09-Sep-96 LVS Added group_prom field. Moved read/write I/O 2533f810b2SJeff Kirsher * macros to DEFXX.C. 2633f810b2SJeff Kirsher * 12-Sep-96 LVS Removed packet request header pointers. 2733f810b2SJeff Kirsher * 04 Aug 2003 macro Converted to the DMA API. 2833f810b2SJeff Kirsher * 23 Oct 2006 macro Big-endian host support. 2933f810b2SJeff Kirsher * 14 Dec 2006 macro TURBOchannel support. 30*795e272eSMaciej W. Rozycki * 10 Mar 2021 macro Dynamic MMIO vs port I/O. 3133f810b2SJeff Kirsher */ 3233f810b2SJeff Kirsher 3333f810b2SJeff Kirsher #ifndef _DEFXX_H_ 3433f810b2SJeff Kirsher #define _DEFXX_H_ 3533f810b2SJeff Kirsher 3633f810b2SJeff Kirsher /* Define basic types for unsigned chars, shorts, longs */ 3733f810b2SJeff Kirsher 3833f810b2SJeff Kirsher typedef u8 PI_UINT8; 3933f810b2SJeff Kirsher typedef u16 PI_UINT16; 4033f810b2SJeff Kirsher typedef u32 PI_UINT32; 4133f810b2SJeff Kirsher 4233f810b2SJeff Kirsher /* Define general structures */ 4333f810b2SJeff Kirsher 4433f810b2SJeff Kirsher typedef struct /* 64-bit counter */ 4533f810b2SJeff Kirsher { 4633f810b2SJeff Kirsher PI_UINT32 ms; 4733f810b2SJeff Kirsher PI_UINT32 ls; 4833f810b2SJeff Kirsher } PI_CNTR; 4933f810b2SJeff Kirsher 5033f810b2SJeff Kirsher typedef struct /* LAN address */ 5133f810b2SJeff Kirsher { 5233f810b2SJeff Kirsher PI_UINT32 lwrd_0; 5333f810b2SJeff Kirsher PI_UINT32 lwrd_1; 5433f810b2SJeff Kirsher } PI_LAN_ADDR; 5533f810b2SJeff Kirsher 5633f810b2SJeff Kirsher typedef struct /* Station ID address */ 5733f810b2SJeff Kirsher { 5833f810b2SJeff Kirsher PI_UINT32 octet_7_4; 5933f810b2SJeff Kirsher PI_UINT32 octet_3_0; 6033f810b2SJeff Kirsher } PI_STATION_ID; 6133f810b2SJeff Kirsher 6233f810b2SJeff Kirsher 6333f810b2SJeff Kirsher /* Define general constants */ 6433f810b2SJeff Kirsher 6533f810b2SJeff Kirsher #define PI_ALIGN_K_DESC_BLK 8192 /* Descriptor block boundary */ 6633f810b2SJeff Kirsher #define PI_ALIGN_K_CONS_BLK 64 /* Consumer block boundary */ 6733f810b2SJeff Kirsher #define PI_ALIGN_K_CMD_REQ_BUFF 128 /* Xmt Command que buffer alignment */ 6833f810b2SJeff Kirsher #define PI_ALIGN_K_CMD_RSP_BUFF 128 /* Rcv Command que buffer alignment */ 6933f810b2SJeff Kirsher #define PI_ALIGN_K_UNSOL_BUFF 128 /* Unsol que buffer alignment */ 7033f810b2SJeff Kirsher #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */ 7133f810b2SJeff Kirsher #define PI_ALIGN_K_RCV_DATA_BUFF 128 /* Rcv que buffer alignment */ 7233f810b2SJeff Kirsher 7333f810b2SJeff Kirsher /* Define PHY index values */ 7433f810b2SJeff Kirsher 7533f810b2SJeff Kirsher #define PI_PHY_K_S 0 /* Index to S phy */ 7633f810b2SJeff Kirsher #define PI_PHY_K_A 0 /* Index to A phy */ 7733f810b2SJeff Kirsher #define PI_PHY_K_B 1 /* Index to B phy */ 7833f810b2SJeff Kirsher #define PI_PHY_K_MAX 2 /* Max number of phys */ 7933f810b2SJeff Kirsher 8033f810b2SJeff Kirsher /* Define FMC descriptor fields */ 8133f810b2SJeff Kirsher 8233f810b2SJeff Kirsher #define PI_FMC_DESCR_V_SOP 31 8333f810b2SJeff Kirsher #define PI_FMC_DESCR_V_EOP 30 8433f810b2SJeff Kirsher #define PI_FMC_DESCR_V_FSC 27 8533f810b2SJeff Kirsher #define PI_FMC_DESCR_V_FSB_ERROR 26 8633f810b2SJeff Kirsher #define PI_FMC_DESCR_V_FSB_ADDR_RECOG 25 8733f810b2SJeff Kirsher #define PI_FMC_DESCR_V_FSB_ADDR_COPIED 24 8833f810b2SJeff Kirsher #define PI_FMC_DESCR_V_FSB 22 8933f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC_FLUSH 21 9033f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC_CRC 20 9133f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC_RRR 17 9233f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC_DD 15 9333f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC_SS 13 9433f810b2SJeff Kirsher #define PI_FMC_DESCR_V_RCC 13 9533f810b2SJeff Kirsher #define PI_FMC_DESCR_V_LEN 0 9633f810b2SJeff Kirsher 9733f810b2SJeff Kirsher #define PI_FMC_DESCR_M_SOP 0x80000000 9833f810b2SJeff Kirsher #define PI_FMC_DESCR_M_EOP 0x40000000 9933f810b2SJeff Kirsher #define PI_FMC_DESCR_M_FSC 0x38000000 10033f810b2SJeff Kirsher #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000 10133f810b2SJeff Kirsher #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000 10233f810b2SJeff Kirsher #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000 10333f810b2SJeff Kirsher #define PI_FMC_DESCR_M_FSB 0x07C00000 10433f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC_FLUSH 0x00200000 10533f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC_CRC 0x00100000 10633f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC_RRR 0x000E0000 10733f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC_DD 0x00018000 10833f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC_SS 0x00006000 10933f810b2SJeff Kirsher #define PI_FMC_DESCR_M_RCC 0x003FE000 11033f810b2SJeff Kirsher #define PI_FMC_DESCR_M_LEN 0x00001FFF 11133f810b2SJeff Kirsher 11233f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RCC_FMC_INT_ERR 0x01AA 11333f810b2SJeff Kirsher 11433f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_SUCCESS 0x00 11533f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_SA_MATCH 0x01 11633f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_DA_MATCH 0x02 11733f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_FMC_ABORT 0x03 11833f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_LENGTH_BAD 0x04 11933f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_FRAGMENT 0x05 12033f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_FORMAT_ERR 0x06 12133f810b2SJeff Kirsher #define PI_FMC_DESCR_K_RRR_MAC_RESET 0x07 12233f810b2SJeff Kirsher 12333f810b2SJeff Kirsher #define PI_FMC_DESCR_K_DD_NO_MATCH 0x0 12433f810b2SJeff Kirsher #define PI_FMC_DESCR_K_DD_PROMISCUOUS 0x1 12533f810b2SJeff Kirsher #define PI_FMC_DESCR_K_DD_CAM_MATCH 0x2 12633f810b2SJeff Kirsher #define PI_FMC_DESCR_K_DD_LOCAL_MATCH 0x3 12733f810b2SJeff Kirsher 12833f810b2SJeff Kirsher #define PI_FMC_DESCR_K_SS_NO_MATCH 0x0 12933f810b2SJeff Kirsher #define PI_FMC_DESCR_K_SS_BRIDGE_MATCH 0x1 13033f810b2SJeff Kirsher #define PI_FMC_DESCR_K_SS_NOT_POSSIBLE 0x2 13133f810b2SJeff Kirsher #define PI_FMC_DESCR_K_SS_LOCAL_MATCH 0x3 13233f810b2SJeff Kirsher 13333f810b2SJeff Kirsher /* Define some max buffer sizes */ 13433f810b2SJeff Kirsher 13533f810b2SJeff Kirsher #define PI_CMD_REQ_K_SIZE_MAX 512 13633f810b2SJeff Kirsher #define PI_CMD_RSP_K_SIZE_MAX 512 13733f810b2SJeff Kirsher #define PI_UNSOL_K_SIZE_MAX 512 13833f810b2SJeff Kirsher #define PI_SMT_HOST_K_SIZE_MAX 4608 /* 4 1/2 K */ 13933f810b2SJeff Kirsher #define PI_RCV_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */ 14033f810b2SJeff Kirsher #define PI_XMT_DATA_K_SIZE_MAX 4608 /* 4 1/2 K */ 14133f810b2SJeff Kirsher 14233f810b2SJeff Kirsher /* Define adapter states */ 14333f810b2SJeff Kirsher 14433f810b2SJeff Kirsher #define PI_STATE_K_RESET 0 14533f810b2SJeff Kirsher #define PI_STATE_K_UPGRADE 1 14633f810b2SJeff Kirsher #define PI_STATE_K_DMA_UNAVAIL 2 14733f810b2SJeff Kirsher #define PI_STATE_K_DMA_AVAIL 3 14833f810b2SJeff Kirsher #define PI_STATE_K_LINK_AVAIL 4 14933f810b2SJeff Kirsher #define PI_STATE_K_LINK_UNAVAIL 5 15033f810b2SJeff Kirsher #define PI_STATE_K_HALTED 6 15133f810b2SJeff Kirsher #define PI_STATE_K_RING_MEMBER 7 15233f810b2SJeff Kirsher #define PI_STATE_K_NUMBER 8 15333f810b2SJeff Kirsher 15433f810b2SJeff Kirsher /* Define codes for command type */ 15533f810b2SJeff Kirsher 15633f810b2SJeff Kirsher #define PI_CMD_K_START 0x00 15733f810b2SJeff Kirsher #define PI_CMD_K_FILTERS_SET 0x01 15833f810b2SJeff Kirsher #define PI_CMD_K_FILTERS_GET 0x02 15933f810b2SJeff Kirsher #define PI_CMD_K_CHARS_SET 0x03 16033f810b2SJeff Kirsher #define PI_CMD_K_STATUS_CHARS_GET 0x04 16133f810b2SJeff Kirsher #define PI_CMD_K_CNTRS_GET 0x05 16233f810b2SJeff Kirsher #define PI_CMD_K_CNTRS_SET 0x06 16333f810b2SJeff Kirsher #define PI_CMD_K_ADDR_FILTER_SET 0x07 16433f810b2SJeff Kirsher #define PI_CMD_K_ADDR_FILTER_GET 0x08 16533f810b2SJeff Kirsher #define PI_CMD_K_ERROR_LOG_CLEAR 0x09 16633f810b2SJeff Kirsher #define PI_CMD_K_ERROR_LOG_GET 0x0A 16733f810b2SJeff Kirsher #define PI_CMD_K_FDDI_MIB_GET 0x0B 16833f810b2SJeff Kirsher #define PI_CMD_K_DEC_EXT_MIB_GET 0x0C 16933f810b2SJeff Kirsher #define PI_CMD_K_DEVICE_SPECIFIC_GET 0x0D 17033f810b2SJeff Kirsher #define PI_CMD_K_SNMP_SET 0x0E 17133f810b2SJeff Kirsher #define PI_CMD_K_UNSOL_TEST 0x0F 17233f810b2SJeff Kirsher #define PI_CMD_K_SMT_MIB_GET 0x10 17333f810b2SJeff Kirsher #define PI_CMD_K_SMT_MIB_SET 0x11 17433f810b2SJeff Kirsher #define PI_CMD_K_MAX 0x11 /* Must match last */ 17533f810b2SJeff Kirsher 17633f810b2SJeff Kirsher /* Define item codes for Chars_Set and Filters_Set commands */ 17733f810b2SJeff Kirsher 17833f810b2SJeff Kirsher #define PI_ITEM_K_EOL 0x00 /* End-of-Item list */ 17933f810b2SJeff Kirsher #define PI_ITEM_K_T_REQ 0x01 /* DECnet T_REQ */ 18033f810b2SJeff Kirsher #define PI_ITEM_K_TVX 0x02 /* DECnet TVX */ 18133f810b2SJeff Kirsher #define PI_ITEM_K_RESTRICTED_TOKEN 0x03 /* DECnet Restricted Token */ 18233f810b2SJeff Kirsher #define PI_ITEM_K_LEM_THRESHOLD 0x04 /* DECnet LEM Threshold */ 18333f810b2SJeff Kirsher #define PI_ITEM_K_RING_PURGER 0x05 /* DECnet Ring Purger Enable */ 18433f810b2SJeff Kirsher #define PI_ITEM_K_CNTR_INTERVAL 0x06 /* Chars_Set */ 18533f810b2SJeff Kirsher #define PI_ITEM_K_IND_GROUP_PROM 0x07 /* Filters_Set */ 18633f810b2SJeff Kirsher #define PI_ITEM_K_GROUP_PROM 0x08 /* Filters_Set */ 18733f810b2SJeff Kirsher #define PI_ITEM_K_BROADCAST 0x09 /* Filters_Set */ 18833f810b2SJeff Kirsher #define PI_ITEM_K_SMT_PROM 0x0A /* Filters_Set */ 18933f810b2SJeff Kirsher #define PI_ITEM_K_SMT_USER 0x0B /* Filters_Set */ 19033f810b2SJeff Kirsher #define PI_ITEM_K_RESERVED 0x0C /* Filters_Set */ 19133f810b2SJeff Kirsher #define PI_ITEM_K_IMPLEMENTOR 0x0D /* Filters_Set */ 19233f810b2SJeff Kirsher #define PI_ITEM_K_LOOPBACK_MODE 0x0E /* Chars_Set */ 19333f810b2SJeff Kirsher #define PI_ITEM_K_CONFIG_POLICY 0x10 /* SMTConfigPolicy */ 19433f810b2SJeff Kirsher #define PI_ITEM_K_CON_POLICY 0x11 /* SMTConnectionPolicy */ 19533f810b2SJeff Kirsher #define PI_ITEM_K_T_NOTIFY 0x12 /* SMTTNotify */ 19633f810b2SJeff Kirsher #define PI_ITEM_K_STATION_ACTION 0x13 /* SMTStationAction */ 19733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_PATHS_REQ 0x15 /* MACPathsRequested */ 19833f810b2SJeff Kirsher #define PI_ITEM_K_MAC_ACTION 0x17 /* MACAction */ 19933f810b2SJeff Kirsher #define PI_ITEM_K_CON_POLICIES 0x18 /* PORTConnectionPolicies */ 20033f810b2SJeff Kirsher #define PI_ITEM_K_PORT_PATHS_REQ 0x19 /* PORTPathsRequested */ 20133f810b2SJeff Kirsher #define PI_ITEM_K_MAC_LOOP_TIME 0x1A /* PORTMACLoopTime */ 20233f810b2SJeff Kirsher #define PI_ITEM_K_TB_MAX 0x1B /* PORTTBMax */ 20333f810b2SJeff Kirsher #define PI_ITEM_K_LER_CUTOFF 0x1C /* PORTLerCutoff */ 20433f810b2SJeff Kirsher #define PI_ITEM_K_LER_ALARM 0x1D /* PORTLerAlarm */ 20533f810b2SJeff Kirsher #define PI_ITEM_K_PORT_ACTION 0x1E /* PORTAction */ 20633f810b2SJeff Kirsher #define PI_ITEM_K_FLUSH_TIME 0x20 /* Chars_Set */ 20733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_T_REQ 0x29 /* MACTReq */ 20833f810b2SJeff Kirsher #define PI_ITEM_K_EMAC_RING_PURGER 0x2A /* eMACRingPurgerEnable */ 20933f810b2SJeff Kirsher #define PI_ITEM_K_EMAC_RTOKEN_TIMEOUT 0x2B /* eMACRestrictedTokenTimeout */ 21033f810b2SJeff Kirsher #define PI_ITEM_K_FDX_ENB_DIS 0x2C /* eFDXEnable */ 21133f810b2SJeff Kirsher #define PI_ITEM_K_MAX 0x2C /* Must equal high item */ 21233f810b2SJeff Kirsher 21333f810b2SJeff Kirsher /* Values for some of the items */ 21433f810b2SJeff Kirsher 21533f810b2SJeff Kirsher #define PI_K_FALSE 0 /* Generic false */ 21633f810b2SJeff Kirsher #define PI_K_TRUE 1 /* Generic true */ 21733f810b2SJeff Kirsher 21833f810b2SJeff Kirsher #define PI_SNMP_K_TRUE 1 /* SNMP true/false values */ 21933f810b2SJeff Kirsher #define PI_SNMP_K_FALSE 2 22033f810b2SJeff Kirsher 22133f810b2SJeff Kirsher #define PI_FSTATE_K_BLOCK 0 /* Filter State */ 22233f810b2SJeff Kirsher #define PI_FSTATE_K_PASS 1 22333f810b2SJeff Kirsher 22433f810b2SJeff Kirsher /* Define command return codes */ 22533f810b2SJeff Kirsher 22633f810b2SJeff Kirsher #define PI_RSP_K_SUCCESS 0x00 22733f810b2SJeff Kirsher #define PI_RSP_K_FAILURE 0x01 22833f810b2SJeff Kirsher #define PI_RSP_K_WARNING 0x02 22933f810b2SJeff Kirsher #define PI_RSP_K_LOOP_MODE_BAD 0x03 23033f810b2SJeff Kirsher #define PI_RSP_K_ITEM_CODE_BAD 0x04 23133f810b2SJeff Kirsher #define PI_RSP_K_TVX_BAD 0x05 23233f810b2SJeff Kirsher #define PI_RSP_K_TREQ_BAD 0x06 23333f810b2SJeff Kirsher #define PI_RSP_K_TOKEN_BAD 0x07 23433f810b2SJeff Kirsher #define PI_RSP_K_NO_EOL 0x0C 23533f810b2SJeff Kirsher #define PI_RSP_K_FILTER_STATE_BAD 0x0D 23633f810b2SJeff Kirsher #define PI_RSP_K_CMD_TYPE_BAD 0x0E 23733f810b2SJeff Kirsher #define PI_RSP_K_ADAPTER_STATE_BAD 0x0F 23833f810b2SJeff Kirsher #define PI_RSP_K_RING_PURGER_BAD 0x10 23933f810b2SJeff Kirsher #define PI_RSP_K_LEM_THRESHOLD_BAD 0x11 24033f810b2SJeff Kirsher #define PI_RSP_K_LOOP_NOT_SUPPORTED 0x12 24133f810b2SJeff Kirsher #define PI_RSP_K_FLUSH_TIME_BAD 0x13 24233f810b2SJeff Kirsher #define PI_RSP_K_NOT_IMPLEMENTED 0x14 24333f810b2SJeff Kirsher #define PI_RSP_K_CONFIG_POLICY_BAD 0x15 24433f810b2SJeff Kirsher #define PI_RSP_K_STATION_ACTION_BAD 0x16 24533f810b2SJeff Kirsher #define PI_RSP_K_MAC_ACTION_BAD 0x17 24633f810b2SJeff Kirsher #define PI_RSP_K_CON_POLICIES_BAD 0x18 24733f810b2SJeff Kirsher #define PI_RSP_K_MAC_LOOP_TIME_BAD 0x19 24833f810b2SJeff Kirsher #define PI_RSP_K_TB_MAX_BAD 0x1A 24933f810b2SJeff Kirsher #define PI_RSP_K_LER_CUTOFF_BAD 0x1B 25033f810b2SJeff Kirsher #define PI_RSP_K_LER_ALARM_BAD 0x1C 25133f810b2SJeff Kirsher #define PI_RSP_K_MAC_PATHS_REQ_BAD 0x1D 25233f810b2SJeff Kirsher #define PI_RSP_K_MAC_T_REQ_BAD 0x1E 25333f810b2SJeff Kirsher #define PI_RSP_K_EMAC_RING_PURGER_BAD 0x1F 25433f810b2SJeff Kirsher #define PI_RSP_K_EMAC_RTOKEN_TIME_BAD 0x20 25533f810b2SJeff Kirsher #define PI_RSP_K_NO_SUCH_ENTRY 0x21 25633f810b2SJeff Kirsher #define PI_RSP_K_T_NOTIFY_BAD 0x22 25733f810b2SJeff Kirsher #define PI_RSP_K_TR_MAX_EXP_BAD 0x23 25833f810b2SJeff Kirsher #define PI_RSP_K_MAC_FRM_ERR_THR_BAD 0x24 25933f810b2SJeff Kirsher #define PI_RSP_K_MAX_T_REQ_BAD 0x25 26033f810b2SJeff Kirsher #define PI_RSP_K_FDX_ENB_DIS_BAD 0x26 26133f810b2SJeff Kirsher #define PI_RSP_K_ITEM_INDEX_BAD 0x27 26233f810b2SJeff Kirsher #define PI_RSP_K_PORT_ACTION_BAD 0x28 26333f810b2SJeff Kirsher 26433f810b2SJeff Kirsher /* Commonly used structures */ 26533f810b2SJeff Kirsher 26633f810b2SJeff Kirsher typedef struct /* Item list */ 26733f810b2SJeff Kirsher { 26833f810b2SJeff Kirsher PI_UINT32 item_code; 26933f810b2SJeff Kirsher PI_UINT32 value; 27033f810b2SJeff Kirsher } PI_ITEM_LIST; 27133f810b2SJeff Kirsher 27233f810b2SJeff Kirsher typedef struct /* Response header */ 27333f810b2SJeff Kirsher { 27433f810b2SJeff Kirsher PI_UINT32 reserved; 27533f810b2SJeff Kirsher PI_UINT32 cmd_type; 27633f810b2SJeff Kirsher PI_UINT32 status; 27733f810b2SJeff Kirsher } PI_RSP_HEADER; 27833f810b2SJeff Kirsher 27933f810b2SJeff Kirsher 28033f810b2SJeff Kirsher /* Start Command */ 28133f810b2SJeff Kirsher 28233f810b2SJeff Kirsher typedef struct 28333f810b2SJeff Kirsher { 28433f810b2SJeff Kirsher PI_UINT32 cmd_type; 28533f810b2SJeff Kirsher } PI_CMD_START_REQ; 28633f810b2SJeff Kirsher 28733f810b2SJeff Kirsher /* Start Response */ 28833f810b2SJeff Kirsher 28933f810b2SJeff Kirsher typedef struct 29033f810b2SJeff Kirsher { 29133f810b2SJeff Kirsher PI_RSP_HEADER header; 29233f810b2SJeff Kirsher } PI_CMD_START_RSP; 29333f810b2SJeff Kirsher 29433f810b2SJeff Kirsher /* Filters_Set Request */ 29533f810b2SJeff Kirsher 29633f810b2SJeff Kirsher #define PI_CMD_FILTERS_SET_K_ITEMS_MAX 63 /* Fits in a 512 byte buffer */ 29733f810b2SJeff Kirsher 29833f810b2SJeff Kirsher typedef struct 29933f810b2SJeff Kirsher { 30033f810b2SJeff Kirsher PI_UINT32 cmd_type; 30133f810b2SJeff Kirsher PI_ITEM_LIST item[PI_CMD_FILTERS_SET_K_ITEMS_MAX]; 30233f810b2SJeff Kirsher } PI_CMD_FILTERS_SET_REQ; 30333f810b2SJeff Kirsher 30433f810b2SJeff Kirsher /* Filters_Set Response */ 30533f810b2SJeff Kirsher 30633f810b2SJeff Kirsher typedef struct 30733f810b2SJeff Kirsher { 30833f810b2SJeff Kirsher PI_RSP_HEADER header; 30933f810b2SJeff Kirsher } PI_CMD_FILTERS_SET_RSP; 31033f810b2SJeff Kirsher 31133f810b2SJeff Kirsher /* Filters_Get Request */ 31233f810b2SJeff Kirsher 31333f810b2SJeff Kirsher typedef struct 31433f810b2SJeff Kirsher { 31533f810b2SJeff Kirsher PI_UINT32 cmd_type; 31633f810b2SJeff Kirsher } PI_CMD_FILTERS_GET_REQ; 31733f810b2SJeff Kirsher 31833f810b2SJeff Kirsher /* Filters_Get Response */ 31933f810b2SJeff Kirsher 32033f810b2SJeff Kirsher typedef struct 32133f810b2SJeff Kirsher { 32233f810b2SJeff Kirsher PI_RSP_HEADER header; 32333f810b2SJeff Kirsher PI_UINT32 ind_group_prom; 32433f810b2SJeff Kirsher PI_UINT32 group_prom; 32533f810b2SJeff Kirsher PI_UINT32 broadcast_all; 32633f810b2SJeff Kirsher PI_UINT32 smt_all; 32733f810b2SJeff Kirsher PI_UINT32 smt_user; 32833f810b2SJeff Kirsher PI_UINT32 reserved_all; 32933f810b2SJeff Kirsher PI_UINT32 implementor_all; 33033f810b2SJeff Kirsher } PI_CMD_FILTERS_GET_RSP; 33133f810b2SJeff Kirsher 33233f810b2SJeff Kirsher 33333f810b2SJeff Kirsher /* Chars_Set Request */ 33433f810b2SJeff Kirsher 33533f810b2SJeff Kirsher #define PI_CMD_CHARS_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */ 33633f810b2SJeff Kirsher 33733f810b2SJeff Kirsher typedef struct 33833f810b2SJeff Kirsher { 33933f810b2SJeff Kirsher PI_UINT32 cmd_type; 34033f810b2SJeff Kirsher struct /* Item list */ 34133f810b2SJeff Kirsher { 34233f810b2SJeff Kirsher PI_UINT32 item_code; 34333f810b2SJeff Kirsher PI_UINT32 value; 34433f810b2SJeff Kirsher PI_UINT32 item_index; 34533f810b2SJeff Kirsher } item[PI_CMD_CHARS_SET_K_ITEMS_MAX]; 34633f810b2SJeff Kirsher } PI_CMD_CHARS_SET_REQ; 34733f810b2SJeff Kirsher 34833f810b2SJeff Kirsher /* Chars_Set Response */ 34933f810b2SJeff Kirsher 35033f810b2SJeff Kirsher typedef struct 35133f810b2SJeff Kirsher { 35233f810b2SJeff Kirsher PI_RSP_HEADER header; 35333f810b2SJeff Kirsher } PI_CMD_CHARS_SET_RSP; 35433f810b2SJeff Kirsher 35533f810b2SJeff Kirsher 35633f810b2SJeff Kirsher /* SNMP_Set Request */ 35733f810b2SJeff Kirsher 35833f810b2SJeff Kirsher #define PI_CMD_SNMP_SET_K_ITEMS_MAX 42 /* Fits in a 512 byte buffer */ 35933f810b2SJeff Kirsher 36033f810b2SJeff Kirsher typedef struct 36133f810b2SJeff Kirsher { 36233f810b2SJeff Kirsher PI_UINT32 cmd_type; 36333f810b2SJeff Kirsher struct /* Item list */ 36433f810b2SJeff Kirsher { 36533f810b2SJeff Kirsher PI_UINT32 item_code; 36633f810b2SJeff Kirsher PI_UINT32 value; 36733f810b2SJeff Kirsher PI_UINT32 item_index; 36833f810b2SJeff Kirsher } item[PI_CMD_SNMP_SET_K_ITEMS_MAX]; 36933f810b2SJeff Kirsher } PI_CMD_SNMP_SET_REQ; 37033f810b2SJeff Kirsher 37133f810b2SJeff Kirsher /* SNMP_Set Response */ 37233f810b2SJeff Kirsher 37333f810b2SJeff Kirsher typedef struct 37433f810b2SJeff Kirsher { 37533f810b2SJeff Kirsher PI_RSP_HEADER header; 37633f810b2SJeff Kirsher } PI_CMD_SNMP_SET_RSP; 37733f810b2SJeff Kirsher 37833f810b2SJeff Kirsher 37933f810b2SJeff Kirsher /* SMT_MIB_Set Request */ 38033f810b2SJeff Kirsher 38133f810b2SJeff Kirsher #define PI_CMD_SMT_MIB_SET_K_ITEMS_MAX 42 /* Max number of items */ 38233f810b2SJeff Kirsher 38333f810b2SJeff Kirsher typedef struct 38433f810b2SJeff Kirsher { 38533f810b2SJeff Kirsher PI_UINT32 cmd_type; 38633f810b2SJeff Kirsher struct 38733f810b2SJeff Kirsher { 38833f810b2SJeff Kirsher PI_UINT32 item_code; 38933f810b2SJeff Kirsher PI_UINT32 value; 39033f810b2SJeff Kirsher PI_UINT32 item_index; 39133f810b2SJeff Kirsher } item[PI_CMD_SMT_MIB_SET_K_ITEMS_MAX]; 39233f810b2SJeff Kirsher } PI_CMD_SMT_MIB_SET_REQ; 39333f810b2SJeff Kirsher 39433f810b2SJeff Kirsher /* SMT_MIB_Set Response */ 39533f810b2SJeff Kirsher 39633f810b2SJeff Kirsher typedef struct 39733f810b2SJeff Kirsher { 39833f810b2SJeff Kirsher PI_RSP_HEADER header; 39933f810b2SJeff Kirsher } PI_CMD_SMT_MIB_SET_RSP; 40033f810b2SJeff Kirsher 40133f810b2SJeff Kirsher /* SMT_MIB_Get Request */ 40233f810b2SJeff Kirsher 40333f810b2SJeff Kirsher typedef struct 40433f810b2SJeff Kirsher { 40533f810b2SJeff Kirsher PI_UINT32 cmd_type; 40633f810b2SJeff Kirsher } PI_CMD_SMT_MIB_GET_REQ; 40733f810b2SJeff Kirsher 40833f810b2SJeff Kirsher /* SMT_MIB_Get Response */ 40933f810b2SJeff Kirsher 41033f810b2SJeff Kirsher typedef struct /* Refer to ANSI FDDI SMT Rev. 7.3 */ 41133f810b2SJeff Kirsher { 41233f810b2SJeff Kirsher PI_RSP_HEADER header; 41333f810b2SJeff Kirsher 41433f810b2SJeff Kirsher /* SMT GROUP */ 41533f810b2SJeff Kirsher 41633f810b2SJeff Kirsher PI_STATION_ID smt_station_id; 41733f810b2SJeff Kirsher PI_UINT32 smt_op_version_id; 41833f810b2SJeff Kirsher PI_UINT32 smt_hi_version_id; 41933f810b2SJeff Kirsher PI_UINT32 smt_lo_version_id; 42033f810b2SJeff Kirsher PI_UINT32 smt_user_data[8]; 42133f810b2SJeff Kirsher PI_UINT32 smt_mib_version_id; 42233f810b2SJeff Kirsher PI_UINT32 smt_mac_ct; 42333f810b2SJeff Kirsher PI_UINT32 smt_non_master_ct; 42433f810b2SJeff Kirsher PI_UINT32 smt_master_ct; 42533f810b2SJeff Kirsher PI_UINT32 smt_available_paths; 42633f810b2SJeff Kirsher PI_UINT32 smt_config_capabilities; 42733f810b2SJeff Kirsher PI_UINT32 smt_config_policy; 42833f810b2SJeff Kirsher PI_UINT32 smt_connection_policy; 42933f810b2SJeff Kirsher PI_UINT32 smt_t_notify; 43033f810b2SJeff Kirsher PI_UINT32 smt_stat_rpt_policy; 43133f810b2SJeff Kirsher PI_UINT32 smt_trace_max_expiration; 43233f810b2SJeff Kirsher PI_UINT32 smt_bypass_present; 43333f810b2SJeff Kirsher PI_UINT32 smt_ecm_state; 43433f810b2SJeff Kirsher PI_UINT32 smt_cf_state; 43533f810b2SJeff Kirsher PI_UINT32 smt_remote_disconnect_flag; 43633f810b2SJeff Kirsher PI_UINT32 smt_station_status; 43733f810b2SJeff Kirsher PI_UINT32 smt_peer_wrap_flag; 43833f810b2SJeff Kirsher PI_CNTR smt_msg_time_stamp; 43933f810b2SJeff Kirsher PI_CNTR smt_transition_time_stamp; 44033f810b2SJeff Kirsher 44133f810b2SJeff Kirsher /* MAC GROUP */ 44233f810b2SJeff Kirsher 44333f810b2SJeff Kirsher PI_UINT32 mac_frame_status_functions; 44433f810b2SJeff Kirsher PI_UINT32 mac_t_max_capability; 44533f810b2SJeff Kirsher PI_UINT32 mac_tvx_capability; 44633f810b2SJeff Kirsher PI_UINT32 mac_available_paths; 44733f810b2SJeff Kirsher PI_UINT32 mac_current_path; 44833f810b2SJeff Kirsher PI_LAN_ADDR mac_upstream_nbr; 44933f810b2SJeff Kirsher PI_LAN_ADDR mac_downstream_nbr; 45033f810b2SJeff Kirsher PI_LAN_ADDR mac_old_upstream_nbr; 45133f810b2SJeff Kirsher PI_LAN_ADDR mac_old_downstream_nbr; 45233f810b2SJeff Kirsher PI_UINT32 mac_dup_address_test; 45333f810b2SJeff Kirsher PI_UINT32 mac_requested_paths; 45433f810b2SJeff Kirsher PI_UINT32 mac_downstream_port_type; 45533f810b2SJeff Kirsher PI_LAN_ADDR mac_smt_address; 45633f810b2SJeff Kirsher PI_UINT32 mac_t_req; 45733f810b2SJeff Kirsher PI_UINT32 mac_t_neg; 45833f810b2SJeff Kirsher PI_UINT32 mac_t_max; 45933f810b2SJeff Kirsher PI_UINT32 mac_tvx_value; 46033f810b2SJeff Kirsher PI_UINT32 mac_frame_error_threshold; 46133f810b2SJeff Kirsher PI_UINT32 mac_frame_error_ratio; 46233f810b2SJeff Kirsher PI_UINT32 mac_rmt_state; 46333f810b2SJeff Kirsher PI_UINT32 mac_da_flag; 46433f810b2SJeff Kirsher PI_UINT32 mac_unda_flag; 46533f810b2SJeff Kirsher PI_UINT32 mac_frame_error_flag; 46633f810b2SJeff Kirsher PI_UINT32 mac_ma_unitdata_available; 46733f810b2SJeff Kirsher PI_UINT32 mac_hardware_present; 46833f810b2SJeff Kirsher PI_UINT32 mac_ma_unitdata_enable; 46933f810b2SJeff Kirsher 47033f810b2SJeff Kirsher /* PATH GROUP */ 47133f810b2SJeff Kirsher 47233f810b2SJeff Kirsher PI_UINT32 path_configuration[8]; 47333f810b2SJeff Kirsher PI_UINT32 path_tvx_lower_bound; 47433f810b2SJeff Kirsher PI_UINT32 path_t_max_lower_bound; 47533f810b2SJeff Kirsher PI_UINT32 path_max_t_req; 47633f810b2SJeff Kirsher 47733f810b2SJeff Kirsher /* PORT GROUP */ 47833f810b2SJeff Kirsher 47933f810b2SJeff Kirsher PI_UINT32 port_my_type[PI_PHY_K_MAX]; 48033f810b2SJeff Kirsher PI_UINT32 port_neighbor_type[PI_PHY_K_MAX]; 48133f810b2SJeff Kirsher PI_UINT32 port_connection_policies[PI_PHY_K_MAX]; 48233f810b2SJeff Kirsher PI_UINT32 port_mac_indicated[PI_PHY_K_MAX]; 48333f810b2SJeff Kirsher PI_UINT32 port_current_path[PI_PHY_K_MAX]; 48433f810b2SJeff Kirsher PI_UINT32 port_requested_paths[PI_PHY_K_MAX]; 48533f810b2SJeff Kirsher PI_UINT32 port_mac_placement[PI_PHY_K_MAX]; 48633f810b2SJeff Kirsher PI_UINT32 port_available_paths[PI_PHY_K_MAX]; 48733f810b2SJeff Kirsher PI_UINT32 port_pmd_class[PI_PHY_K_MAX]; 48833f810b2SJeff Kirsher PI_UINT32 port_connection_capabilities[PI_PHY_K_MAX]; 48933f810b2SJeff Kirsher PI_UINT32 port_bs_flag[PI_PHY_K_MAX]; 49033f810b2SJeff Kirsher PI_UINT32 port_ler_estimate[PI_PHY_K_MAX]; 49133f810b2SJeff Kirsher PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX]; 49233f810b2SJeff Kirsher PI_UINT32 port_ler_alarm[PI_PHY_K_MAX]; 49333f810b2SJeff Kirsher PI_UINT32 port_connect_state[PI_PHY_K_MAX]; 49433f810b2SJeff Kirsher PI_UINT32 port_pcm_state[PI_PHY_K_MAX]; 49533f810b2SJeff Kirsher PI_UINT32 port_pc_withhold[PI_PHY_K_MAX]; 49633f810b2SJeff Kirsher PI_UINT32 port_ler_flag[PI_PHY_K_MAX]; 49733f810b2SJeff Kirsher PI_UINT32 port_hardware_present[PI_PHY_K_MAX]; 49833f810b2SJeff Kirsher 49933f810b2SJeff Kirsher /* GROUP for things that were added later, so must be at the end. */ 50033f810b2SJeff Kirsher 50133f810b2SJeff Kirsher PI_CNTR path_ring_latency; 50233f810b2SJeff Kirsher 50333f810b2SJeff Kirsher } PI_CMD_SMT_MIB_GET_RSP; 50433f810b2SJeff Kirsher 50533f810b2SJeff Kirsher 50633f810b2SJeff Kirsher /* 50733f810b2SJeff Kirsher * Item and group code definitions for SMT 7.3 mandatory objects. These 50833f810b2SJeff Kirsher * definitions are to be used as appropriate in SMT_MIB_SET commands and 50933f810b2SJeff Kirsher * certain host-sent SMT frames such as PMF Get and Set requests. The 51033f810b2SJeff Kirsher * codes have been taken from the MIB summary section of ANSI SMT 7.3. 51133f810b2SJeff Kirsher */ 51233f810b2SJeff Kirsher 51333f810b2SJeff Kirsher #define PI_GRP_K_SMT_STATION_ID 0x100A 51433f810b2SJeff Kirsher #define PI_ITEM_K_SMT_STATION_ID 0x100B 51533f810b2SJeff Kirsher #define PI_ITEM_K_SMT_OP_VERS_ID 0x100D 51633f810b2SJeff Kirsher #define PI_ITEM_K_SMT_HI_VERS_ID 0x100E 51733f810b2SJeff Kirsher #define PI_ITEM_K_SMT_LO_VERS_ID 0x100F 51833f810b2SJeff Kirsher #define PI_ITEM_K_SMT_USER_DATA 0x1011 51933f810b2SJeff Kirsher #define PI_ITEM_K_SMT_MIB_VERS_ID 0x1012 52033f810b2SJeff Kirsher 52133f810b2SJeff Kirsher #define PI_GRP_K_SMT_STATION_CONFIG 0x1014 52233f810b2SJeff Kirsher #define PI_ITEM_K_SMT_MAC_CT 0x1015 52333f810b2SJeff Kirsher #define PI_ITEM_K_SMT_NON_MASTER_CT 0x1016 52433f810b2SJeff Kirsher #define PI_ITEM_K_SMT_MASTER_CT 0x1017 52533f810b2SJeff Kirsher #define PI_ITEM_K_SMT_AVAIL_PATHS 0x1018 52633f810b2SJeff Kirsher #define PI_ITEM_K_SMT_CONFIG_CAPS 0x1019 52733f810b2SJeff Kirsher #define PI_ITEM_K_SMT_CONFIG_POL 0x101A 52833f810b2SJeff Kirsher #define PI_ITEM_K_SMT_CONN_POL 0x101B 52933f810b2SJeff Kirsher #define PI_ITEM_K_SMT_T_NOTIFY 0x101D 53033f810b2SJeff Kirsher #define PI_ITEM_K_SMT_STAT_POL 0x101E 53133f810b2SJeff Kirsher #define PI_ITEM_K_SMT_TR_MAX_EXP 0x101F 53233f810b2SJeff Kirsher #define PI_ITEM_K_SMT_PORT_INDEXES 0x1020 53333f810b2SJeff Kirsher #define PI_ITEM_K_SMT_MAC_INDEXES 0x1021 53433f810b2SJeff Kirsher #define PI_ITEM_K_SMT_BYPASS_PRESENT 0x1022 53533f810b2SJeff Kirsher 53633f810b2SJeff Kirsher #define PI_GRP_K_SMT_STATUS 0x1028 53733f810b2SJeff Kirsher #define PI_ITEM_K_SMT_ECM_STATE 0x1029 53833f810b2SJeff Kirsher #define PI_ITEM_K_SMT_CF_STATE 0x102A 53933f810b2SJeff Kirsher #define PI_ITEM_K_SMT_REM_DISC_FLAG 0x102C 54033f810b2SJeff Kirsher #define PI_ITEM_K_SMT_STATION_STATUS 0x102D 54133f810b2SJeff Kirsher #define PI_ITEM_K_SMT_PEER_WRAP_FLAG 0x102E 54233f810b2SJeff Kirsher 54333f810b2SJeff Kirsher #define PI_GRP_K_SMT_MIB_OPERATION 0x1032 54433f810b2SJeff Kirsher #define PI_ITEM_K_SMT_MSG_TIME_STAMP 0x1033 54533f810b2SJeff Kirsher #define PI_ITEM_K_SMT_TRN_TIME_STAMP 0x1034 54633f810b2SJeff Kirsher 54733f810b2SJeff Kirsher #define PI_ITEM_K_SMT_STATION_ACT 0x103C 54833f810b2SJeff Kirsher 54933f810b2SJeff Kirsher #define PI_GRP_K_MAC_CAPABILITIES 0x200A 55033f810b2SJeff Kirsher #define PI_ITEM_K_MAC_FRM_STAT_FUNC 0x200B 55133f810b2SJeff Kirsher #define PI_ITEM_K_MAC_T_MAX_CAP 0x200D 55233f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TVX_CAP 0x200E 55333f810b2SJeff Kirsher 55433f810b2SJeff Kirsher #define PI_GRP_K_MAC_CONFIG 0x2014 55533f810b2SJeff Kirsher #define PI_ITEM_K_MAC_AVAIL_PATHS 0x2016 55633f810b2SJeff Kirsher #define PI_ITEM_K_MAC_CURRENT_PATH 0x2017 55733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_UP_NBR 0x2018 55833f810b2SJeff Kirsher #define PI_ITEM_K_MAC_DOWN_NBR 0x2019 55933f810b2SJeff Kirsher #define PI_ITEM_K_MAC_OLD_UP_NBR 0x201A 56033f810b2SJeff Kirsher #define PI_ITEM_K_MAC_OLD_DOWN_NBR 0x201B 56133f810b2SJeff Kirsher #define PI_ITEM_K_MAC_DUP_ADDR_TEST 0x201D 56233f810b2SJeff Kirsher #define PI_ITEM_K_MAC_REQ_PATHS 0x2020 56333f810b2SJeff Kirsher #define PI_ITEM_K_MAC_DOWN_PORT_TYPE 0x2021 56433f810b2SJeff Kirsher #define PI_ITEM_K_MAC_INDEX 0x2022 56533f810b2SJeff Kirsher 56633f810b2SJeff Kirsher #define PI_GRP_K_MAC_ADDRESS 0x2028 56733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_SMT_ADDRESS 0x2029 56833f810b2SJeff Kirsher 56933f810b2SJeff Kirsher #define PI_GRP_K_MAC_OPERATION 0x2032 57033f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TREQ 0x2033 57133f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TNEG 0x2034 57233f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TMAX 0x2035 57333f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TVX_VALUE 0x2036 57433f810b2SJeff Kirsher 57533f810b2SJeff Kirsher #define PI_GRP_K_MAC_COUNTERS 0x2046 57633f810b2SJeff Kirsher #define PI_ITEM_K_MAC_FRAME_CT 0x2047 57733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_COPIED_CT 0x2048 57833f810b2SJeff Kirsher #define PI_ITEM_K_MAC_TRANSMIT_CT 0x2049 57933f810b2SJeff Kirsher #define PI_ITEM_K_MAC_ERROR_CT 0x2051 58033f810b2SJeff Kirsher #define PI_ITEM_K_MAC_LOST_CT 0x2052 58133f810b2SJeff Kirsher 58233f810b2SJeff Kirsher #define PI_GRP_K_MAC_FRM_ERR_COND 0x205A 58333f810b2SJeff Kirsher #define PI_ITEM_K_MAC_FRM_ERR_THR 0x205F 58433f810b2SJeff Kirsher #define PI_ITEM_K_MAC_FRM_ERR_RAT 0x2060 58533f810b2SJeff Kirsher 58633f810b2SJeff Kirsher #define PI_GRP_K_MAC_STATUS 0x206E 58733f810b2SJeff Kirsher #define PI_ITEM_K_MAC_RMT_STATE 0x206F 58833f810b2SJeff Kirsher #define PI_ITEM_K_MAC_DA_FLAG 0x2070 58933f810b2SJeff Kirsher #define PI_ITEM_K_MAC_UNDA_FLAG 0x2071 59033f810b2SJeff Kirsher #define PI_ITEM_K_MAC_FRM_ERR_FLAG 0x2072 59133f810b2SJeff Kirsher #define PI_ITEM_K_MAC_MA_UNIT_AVAIL 0x2074 59233f810b2SJeff Kirsher #define PI_ITEM_K_MAC_HW_PRESENT 0x2075 59333f810b2SJeff Kirsher #define PI_ITEM_K_MAC_MA_UNIT_ENAB 0x2076 59433f810b2SJeff Kirsher 59533f810b2SJeff Kirsher #define PI_GRP_K_PATH_CONFIG 0x320A 59633f810b2SJeff Kirsher #define PI_ITEM_K_PATH_INDEX 0x320B 59733f810b2SJeff Kirsher #define PI_ITEM_K_PATH_CONFIGURATION 0x3212 59833f810b2SJeff Kirsher #define PI_ITEM_K_PATH_TVX_LB 0x3215 59933f810b2SJeff Kirsher #define PI_ITEM_K_PATH_T_MAX_LB 0x3216 60033f810b2SJeff Kirsher #define PI_ITEM_K_PATH_MAX_T_REQ 0x3217 60133f810b2SJeff Kirsher 60233f810b2SJeff Kirsher #define PI_GRP_K_PORT_CONFIG 0x400A 60333f810b2SJeff Kirsher #define PI_ITEM_K_PORT_MY_TYPE 0x400C 60433f810b2SJeff Kirsher #define PI_ITEM_K_PORT_NBR_TYPE 0x400D 60533f810b2SJeff Kirsher #define PI_ITEM_K_PORT_CONN_POLS 0x400E 60633f810b2SJeff Kirsher #define PI_ITEM_K_PORT_MAC_INDICATED 0x400F 60733f810b2SJeff Kirsher #define PI_ITEM_K_PORT_CURRENT_PATH 0x4010 60833f810b2SJeff Kirsher #define PI_ITEM_K_PORT_REQ_PATHS 0x4011 60933f810b2SJeff Kirsher #define PI_ITEM_K_PORT_MAC_PLACEMENT 0x4012 61033f810b2SJeff Kirsher #define PI_ITEM_K_PORT_AVAIL_PATHS 0x4013 61133f810b2SJeff Kirsher #define PI_ITEM_K_PORT_PMD_CLASS 0x4016 61233f810b2SJeff Kirsher #define PI_ITEM_K_PORT_CONN_CAPS 0x4017 61333f810b2SJeff Kirsher #define PI_ITEM_K_PORT_INDEX 0x401D 61433f810b2SJeff Kirsher 61533f810b2SJeff Kirsher #define PI_GRP_K_PORT_OPERATION 0x401E 61633f810b2SJeff Kirsher #define PI_ITEM_K_PORT_BS_FLAG 0x4021 61733f810b2SJeff Kirsher 61833f810b2SJeff Kirsher #define PI_GRP_K_PORT_ERR_CNTRS 0x4028 61933f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LCT_FAIL_CT 0x402A 62033f810b2SJeff Kirsher 62133f810b2SJeff Kirsher #define PI_GRP_K_PORT_LER 0x4032 62233f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LER_ESTIMATE 0x4033 62333f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LEM_REJ_CT 0x4034 62433f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LEM_CT 0x4035 62533f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LER_CUTOFF 0x403A 62633f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LER_ALARM 0x403B 62733f810b2SJeff Kirsher 62833f810b2SJeff Kirsher #define PI_GRP_K_PORT_STATUS 0x403C 62933f810b2SJeff Kirsher #define PI_ITEM_K_PORT_CONNECT_STATE 0x403D 63033f810b2SJeff Kirsher #define PI_ITEM_K_PORT_PCM_STATE 0x403E 63133f810b2SJeff Kirsher #define PI_ITEM_K_PORT_PC_WITHHOLD 0x403F 63233f810b2SJeff Kirsher #define PI_ITEM_K_PORT_LER_FLAG 0x4040 63333f810b2SJeff Kirsher #define PI_ITEM_K_PORT_HW_PRESENT 0x4041 63433f810b2SJeff Kirsher 63533f810b2SJeff Kirsher #define PI_ITEM_K_PORT_ACT 0x4046 63633f810b2SJeff Kirsher 63733f810b2SJeff Kirsher /* Addr_Filter_Set Request */ 63833f810b2SJeff Kirsher 63933f810b2SJeff Kirsher #define PI_CMD_ADDR_FILTER_K_SIZE 62 64033f810b2SJeff Kirsher 64133f810b2SJeff Kirsher typedef struct 64233f810b2SJeff Kirsher { 64333f810b2SJeff Kirsher PI_UINT32 cmd_type; 64433f810b2SJeff Kirsher PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE]; 64533f810b2SJeff Kirsher } PI_CMD_ADDR_FILTER_SET_REQ; 64633f810b2SJeff Kirsher 64733f810b2SJeff Kirsher /* Addr_Filter_Set Response */ 64833f810b2SJeff Kirsher 64933f810b2SJeff Kirsher typedef struct 65033f810b2SJeff Kirsher { 65133f810b2SJeff Kirsher PI_RSP_HEADER header; 65233f810b2SJeff Kirsher } PI_CMD_ADDR_FILTER_SET_RSP; 65333f810b2SJeff Kirsher 65433f810b2SJeff Kirsher /* Addr_Filter_Get Request */ 65533f810b2SJeff Kirsher 65633f810b2SJeff Kirsher typedef struct 65733f810b2SJeff Kirsher { 65833f810b2SJeff Kirsher PI_UINT32 cmd_type; 65933f810b2SJeff Kirsher } PI_CMD_ADDR_FILTER_GET_REQ; 66033f810b2SJeff Kirsher 66133f810b2SJeff Kirsher /* Addr_Filter_Get Response */ 66233f810b2SJeff Kirsher 66333f810b2SJeff Kirsher typedef struct 66433f810b2SJeff Kirsher { 66533f810b2SJeff Kirsher PI_RSP_HEADER header; 66633f810b2SJeff Kirsher PI_LAN_ADDR entry[PI_CMD_ADDR_FILTER_K_SIZE]; 66733f810b2SJeff Kirsher } PI_CMD_ADDR_FILTER_GET_RSP; 66833f810b2SJeff Kirsher 66933f810b2SJeff Kirsher /* Status_Chars_Get Request */ 67033f810b2SJeff Kirsher 67133f810b2SJeff Kirsher typedef struct 67233f810b2SJeff Kirsher { 67333f810b2SJeff Kirsher PI_UINT32 cmd_type; 67433f810b2SJeff Kirsher } PI_CMD_STATUS_CHARS_GET_REQ; 67533f810b2SJeff Kirsher 67633f810b2SJeff Kirsher /* Status_Chars_Get Response */ 67733f810b2SJeff Kirsher 67833f810b2SJeff Kirsher typedef struct 67933f810b2SJeff Kirsher { 68033f810b2SJeff Kirsher PI_RSP_HEADER header; 68133f810b2SJeff Kirsher PI_STATION_ID station_id; /* Station */ 68233f810b2SJeff Kirsher PI_UINT32 station_type; 68333f810b2SJeff Kirsher PI_UINT32 smt_ver_id; 68433f810b2SJeff Kirsher PI_UINT32 smt_ver_id_max; 68533f810b2SJeff Kirsher PI_UINT32 smt_ver_id_min; 68633f810b2SJeff Kirsher PI_UINT32 station_state; 68733f810b2SJeff Kirsher PI_LAN_ADDR link_addr; /* Link */ 68833f810b2SJeff Kirsher PI_UINT32 t_req; 68933f810b2SJeff Kirsher PI_UINT32 tvx; 69033f810b2SJeff Kirsher PI_UINT32 token_timeout; 69133f810b2SJeff Kirsher PI_UINT32 purger_enb; 69233f810b2SJeff Kirsher PI_UINT32 link_state; 69333f810b2SJeff Kirsher PI_UINT32 tneg; 69433f810b2SJeff Kirsher PI_UINT32 dup_addr_flag; 69533f810b2SJeff Kirsher PI_LAN_ADDR una; 69633f810b2SJeff Kirsher PI_LAN_ADDR una_old; 69733f810b2SJeff Kirsher PI_UINT32 un_dup_addr_flag; 69833f810b2SJeff Kirsher PI_LAN_ADDR dna; 69933f810b2SJeff Kirsher PI_LAN_ADDR dna_old; 70033f810b2SJeff Kirsher PI_UINT32 purger_state; 70133f810b2SJeff Kirsher PI_UINT32 fci_mode; 70233f810b2SJeff Kirsher PI_UINT32 error_reason; 70333f810b2SJeff Kirsher PI_UINT32 loopback; 70433f810b2SJeff Kirsher PI_UINT32 ring_latency; 70533f810b2SJeff Kirsher PI_LAN_ADDR last_dir_beacon_sa; 70633f810b2SJeff Kirsher PI_LAN_ADDR last_dir_beacon_una; 70733f810b2SJeff Kirsher PI_UINT32 phy_type[PI_PHY_K_MAX]; /* Phy */ 70833f810b2SJeff Kirsher PI_UINT32 pmd_type[PI_PHY_K_MAX]; 70933f810b2SJeff Kirsher PI_UINT32 lem_threshold[PI_PHY_K_MAX]; 71033f810b2SJeff Kirsher PI_UINT32 phy_state[PI_PHY_K_MAX]; 71133f810b2SJeff Kirsher PI_UINT32 nbor_phy_type[PI_PHY_K_MAX]; 71233f810b2SJeff Kirsher PI_UINT32 link_error_est[PI_PHY_K_MAX]; 71333f810b2SJeff Kirsher PI_UINT32 broken_reason[PI_PHY_K_MAX]; 71433f810b2SJeff Kirsher PI_UINT32 reject_reason[PI_PHY_K_MAX]; 71533f810b2SJeff Kirsher PI_UINT32 cntr_interval; /* Miscellaneous */ 71633f810b2SJeff Kirsher PI_UINT32 module_rev; 71733f810b2SJeff Kirsher PI_UINT32 firmware_rev; 71833f810b2SJeff Kirsher PI_UINT32 mop_device_type; 71933f810b2SJeff Kirsher PI_UINT32 phy_led[PI_PHY_K_MAX]; 72033f810b2SJeff Kirsher PI_UINT32 flush_time; 72133f810b2SJeff Kirsher } PI_CMD_STATUS_CHARS_GET_RSP; 72233f810b2SJeff Kirsher 72333f810b2SJeff Kirsher /* FDDI_MIB_Get Request */ 72433f810b2SJeff Kirsher 72533f810b2SJeff Kirsher typedef struct 72633f810b2SJeff Kirsher { 72733f810b2SJeff Kirsher PI_UINT32 cmd_type; 72833f810b2SJeff Kirsher } PI_CMD_FDDI_MIB_GET_REQ; 72933f810b2SJeff Kirsher 73033f810b2SJeff Kirsher /* FDDI_MIB_Get Response */ 73133f810b2SJeff Kirsher 73233f810b2SJeff Kirsher typedef struct 73333f810b2SJeff Kirsher { 73433f810b2SJeff Kirsher PI_RSP_HEADER header; 73533f810b2SJeff Kirsher 73633f810b2SJeff Kirsher /* SMT GROUP */ 73733f810b2SJeff Kirsher 73833f810b2SJeff Kirsher PI_STATION_ID smt_station_id; 73933f810b2SJeff Kirsher PI_UINT32 smt_op_version_id; 74033f810b2SJeff Kirsher PI_UINT32 smt_hi_version_id; 74133f810b2SJeff Kirsher PI_UINT32 smt_lo_version_id; 74233f810b2SJeff Kirsher PI_UINT32 smt_mac_ct; 74333f810b2SJeff Kirsher PI_UINT32 smt_non_master_ct; 74433f810b2SJeff Kirsher PI_UINT32 smt_master_ct; 74533f810b2SJeff Kirsher PI_UINT32 smt_paths_available; 74633f810b2SJeff Kirsher PI_UINT32 smt_config_capabilities; 74733f810b2SJeff Kirsher PI_UINT32 smt_config_policy; 74833f810b2SJeff Kirsher PI_UINT32 smt_connection_policy; 74933f810b2SJeff Kirsher PI_UINT32 smt_t_notify; 75033f810b2SJeff Kirsher PI_UINT32 smt_status_reporting; 75133f810b2SJeff Kirsher PI_UINT32 smt_ecm_state; 75233f810b2SJeff Kirsher PI_UINT32 smt_cf_state; 75333f810b2SJeff Kirsher PI_UINT32 smt_hold_state; 75433f810b2SJeff Kirsher PI_UINT32 smt_remote_disconnect_flag; 75533f810b2SJeff Kirsher PI_UINT32 smt_station_action; 75633f810b2SJeff Kirsher 75733f810b2SJeff Kirsher /* MAC GROUP */ 75833f810b2SJeff Kirsher 75933f810b2SJeff Kirsher PI_UINT32 mac_frame_status_capabilities; 76033f810b2SJeff Kirsher PI_UINT32 mac_t_max_greatest_lower_bound; 76133f810b2SJeff Kirsher PI_UINT32 mac_tvx_greatest_lower_bound; 76233f810b2SJeff Kirsher PI_UINT32 mac_paths_available; 76333f810b2SJeff Kirsher PI_UINT32 mac_current_path; 76433f810b2SJeff Kirsher PI_LAN_ADDR mac_upstream_nbr; 76533f810b2SJeff Kirsher PI_LAN_ADDR mac_old_upstream_nbr; 76633f810b2SJeff Kirsher PI_UINT32 mac_dup_addr_test; 76733f810b2SJeff Kirsher PI_UINT32 mac_paths_requested; 76833f810b2SJeff Kirsher PI_UINT32 mac_downstream_port_type; 76933f810b2SJeff Kirsher PI_LAN_ADDR mac_smt_address; 77033f810b2SJeff Kirsher PI_UINT32 mac_t_req; 77133f810b2SJeff Kirsher PI_UINT32 mac_t_neg; 77233f810b2SJeff Kirsher PI_UINT32 mac_t_max; 77333f810b2SJeff Kirsher PI_UINT32 mac_tvx_value; 77433f810b2SJeff Kirsher PI_UINT32 mac_t_min; 77533f810b2SJeff Kirsher PI_UINT32 mac_current_frame_status; 77633f810b2SJeff Kirsher /* mac_frame_cts */ 77733f810b2SJeff Kirsher /* mac_error_cts */ 77833f810b2SJeff Kirsher /* mac_lost_cts */ 77933f810b2SJeff Kirsher PI_UINT32 mac_frame_error_threshold; 78033f810b2SJeff Kirsher PI_UINT32 mac_frame_error_ratio; 78133f810b2SJeff Kirsher PI_UINT32 mac_rmt_state; 78233f810b2SJeff Kirsher PI_UINT32 mac_da_flag; 78333f810b2SJeff Kirsher PI_UINT32 mac_una_da_flag; 78433f810b2SJeff Kirsher PI_UINT32 mac_frame_condition; 78533f810b2SJeff Kirsher PI_UINT32 mac_chip_set; 78633f810b2SJeff Kirsher PI_UINT32 mac_action; 78733f810b2SJeff Kirsher 78833f810b2SJeff Kirsher /* PATH GROUP => Does not need to be implemented */ 78933f810b2SJeff Kirsher 79033f810b2SJeff Kirsher /* PORT GROUP */ 79133f810b2SJeff Kirsher 79233f810b2SJeff Kirsher PI_UINT32 port_pc_type[PI_PHY_K_MAX]; 79333f810b2SJeff Kirsher PI_UINT32 port_pc_neighbor[PI_PHY_K_MAX]; 79433f810b2SJeff Kirsher PI_UINT32 port_connection_policies[PI_PHY_K_MAX]; 79533f810b2SJeff Kirsher PI_UINT32 port_remote_mac_indicated[PI_PHY_K_MAX]; 79633f810b2SJeff Kirsher PI_UINT32 port_ce_state[PI_PHY_K_MAX]; 79733f810b2SJeff Kirsher PI_UINT32 port_paths_requested[PI_PHY_K_MAX]; 79833f810b2SJeff Kirsher PI_UINT32 port_mac_placement[PI_PHY_K_MAX]; 79933f810b2SJeff Kirsher PI_UINT32 port_available_paths[PI_PHY_K_MAX]; 80033f810b2SJeff Kirsher PI_UINT32 port_mac_loop_time[PI_PHY_K_MAX]; 80133f810b2SJeff Kirsher PI_UINT32 port_tb_max[PI_PHY_K_MAX]; 80233f810b2SJeff Kirsher PI_UINT32 port_bs_flag[PI_PHY_K_MAX]; 80333f810b2SJeff Kirsher /* port_lct_fail_cts[PI_PHY_K_MAX]; */ 80433f810b2SJeff Kirsher PI_UINT32 port_ler_estimate[PI_PHY_K_MAX]; 80533f810b2SJeff Kirsher /* port_lem_reject_cts[PI_PHY_K_MAX]; */ 80633f810b2SJeff Kirsher /* port_lem_cts[PI_PHY_K_MAX]; */ 80733f810b2SJeff Kirsher PI_UINT32 port_ler_cutoff[PI_PHY_K_MAX]; 80833f810b2SJeff Kirsher PI_UINT32 port_ler_alarm[PI_PHY_K_MAX]; 80933f810b2SJeff Kirsher PI_UINT32 port_connect_state[PI_PHY_K_MAX]; 81033f810b2SJeff Kirsher PI_UINT32 port_pcm_state[PI_PHY_K_MAX]; 81133f810b2SJeff Kirsher PI_UINT32 port_pc_withhold[PI_PHY_K_MAX]; 81233f810b2SJeff Kirsher PI_UINT32 port_ler_condition[PI_PHY_K_MAX]; 81333f810b2SJeff Kirsher PI_UINT32 port_chip_set[PI_PHY_K_MAX]; 81433f810b2SJeff Kirsher PI_UINT32 port_action[PI_PHY_K_MAX]; 81533f810b2SJeff Kirsher 81633f810b2SJeff Kirsher /* ATTACHMENT GROUP */ 81733f810b2SJeff Kirsher 81833f810b2SJeff Kirsher PI_UINT32 attachment_class; 81933f810b2SJeff Kirsher PI_UINT32 attachment_ob_present; 82033f810b2SJeff Kirsher PI_UINT32 attachment_imax_expiration; 82133f810b2SJeff Kirsher PI_UINT32 attachment_inserted_status; 82233f810b2SJeff Kirsher PI_UINT32 attachment_insert_policy; 82333f810b2SJeff Kirsher 82433f810b2SJeff Kirsher /* CHIP SET GROUP => Does not need to be implemented */ 82533f810b2SJeff Kirsher 82633f810b2SJeff Kirsher } PI_CMD_FDDI_MIB_GET_RSP; 82733f810b2SJeff Kirsher 82833f810b2SJeff Kirsher /* DEC_Ext_MIB_Get Request */ 82933f810b2SJeff Kirsher 83033f810b2SJeff Kirsher typedef struct 83133f810b2SJeff Kirsher { 83233f810b2SJeff Kirsher PI_UINT32 cmd_type; 83333f810b2SJeff Kirsher } PI_CMD_DEC_EXT_MIB_GET_REQ; 83433f810b2SJeff Kirsher 83533f810b2SJeff Kirsher /* DEC_Ext_MIB_Get (efddi and efdx groups only) Response */ 83633f810b2SJeff Kirsher 83733f810b2SJeff Kirsher typedef struct 83833f810b2SJeff Kirsher { 83933f810b2SJeff Kirsher PI_RSP_HEADER header; 84033f810b2SJeff Kirsher 84133f810b2SJeff Kirsher /* SMT GROUP */ 84233f810b2SJeff Kirsher 84333f810b2SJeff Kirsher PI_UINT32 esmt_station_type; 84433f810b2SJeff Kirsher 84533f810b2SJeff Kirsher /* MAC GROUP */ 84633f810b2SJeff Kirsher 84733f810b2SJeff Kirsher PI_UINT32 emac_link_state; 84833f810b2SJeff Kirsher PI_UINT32 emac_ring_purger_state; 84933f810b2SJeff Kirsher PI_UINT32 emac_ring_purger_enable; 85033f810b2SJeff Kirsher PI_UINT32 emac_frame_strip_mode; 85133f810b2SJeff Kirsher PI_UINT32 emac_ring_error_reason; 85233f810b2SJeff Kirsher PI_UINT32 emac_up_nbr_dup_addr_flag; 85333f810b2SJeff Kirsher PI_UINT32 emac_restricted_token_timeout; 85433f810b2SJeff Kirsher 85533f810b2SJeff Kirsher /* PORT GROUP */ 85633f810b2SJeff Kirsher 85733f810b2SJeff Kirsher PI_UINT32 eport_pmd_type[PI_PHY_K_MAX]; 85833f810b2SJeff Kirsher PI_UINT32 eport_phy_state[PI_PHY_K_MAX]; 85933f810b2SJeff Kirsher PI_UINT32 eport_reject_reason[PI_PHY_K_MAX]; 86033f810b2SJeff Kirsher 86133f810b2SJeff Kirsher /* FDX (Full-Duplex) GROUP */ 86233f810b2SJeff Kirsher 86333f810b2SJeff Kirsher PI_UINT32 efdx_enable; /* Valid only in SMT 7.3 */ 86433f810b2SJeff Kirsher PI_UINT32 efdx_op; /* Valid only in SMT 7.3 */ 86533f810b2SJeff Kirsher PI_UINT32 efdx_state; /* Valid only in SMT 7.3 */ 86633f810b2SJeff Kirsher 86733f810b2SJeff Kirsher } PI_CMD_DEC_EXT_MIB_GET_RSP; 86833f810b2SJeff Kirsher 86933f810b2SJeff Kirsher typedef struct 87033f810b2SJeff Kirsher { 87133f810b2SJeff Kirsher PI_CNTR traces_rcvd; /* Station */ 87233f810b2SJeff Kirsher PI_CNTR frame_cnt; /* Link */ 87333f810b2SJeff Kirsher PI_CNTR error_cnt; 87433f810b2SJeff Kirsher PI_CNTR lost_cnt; 87533f810b2SJeff Kirsher PI_CNTR octets_rcvd; 87633f810b2SJeff Kirsher PI_CNTR octets_sent; 87733f810b2SJeff Kirsher PI_CNTR pdus_rcvd; 87833f810b2SJeff Kirsher PI_CNTR pdus_sent; 87933f810b2SJeff Kirsher PI_CNTR mcast_octets_rcvd; 88033f810b2SJeff Kirsher PI_CNTR mcast_octets_sent; 88133f810b2SJeff Kirsher PI_CNTR mcast_pdus_rcvd; 88233f810b2SJeff Kirsher PI_CNTR mcast_pdus_sent; 88333f810b2SJeff Kirsher PI_CNTR xmt_underruns; 88433f810b2SJeff Kirsher PI_CNTR xmt_failures; 88533f810b2SJeff Kirsher PI_CNTR block_check_errors; 88633f810b2SJeff Kirsher PI_CNTR frame_status_errors; 88733f810b2SJeff Kirsher PI_CNTR pdu_length_errors; 88833f810b2SJeff Kirsher PI_CNTR rcv_overruns; 88933f810b2SJeff Kirsher PI_CNTR user_buff_unavailable; 89033f810b2SJeff Kirsher PI_CNTR inits_initiated; 89133f810b2SJeff Kirsher PI_CNTR inits_rcvd; 89233f810b2SJeff Kirsher PI_CNTR beacons_initiated; 89333f810b2SJeff Kirsher PI_CNTR dup_addrs; 89433f810b2SJeff Kirsher PI_CNTR dup_tokens; 89533f810b2SJeff Kirsher PI_CNTR purge_errors; 89633f810b2SJeff Kirsher PI_CNTR fci_strip_errors; 89733f810b2SJeff Kirsher PI_CNTR traces_initiated; 89833f810b2SJeff Kirsher PI_CNTR directed_beacons_rcvd; 89933f810b2SJeff Kirsher PI_CNTR emac_frame_alignment_errors; 90033f810b2SJeff Kirsher PI_CNTR ebuff_errors[PI_PHY_K_MAX]; /* Phy */ 90133f810b2SJeff Kirsher PI_CNTR lct_rejects[PI_PHY_K_MAX]; 90233f810b2SJeff Kirsher PI_CNTR lem_rejects[PI_PHY_K_MAX]; 90333f810b2SJeff Kirsher PI_CNTR link_errors[PI_PHY_K_MAX]; 90433f810b2SJeff Kirsher PI_CNTR connections[PI_PHY_K_MAX]; 90533f810b2SJeff Kirsher PI_CNTR copied_cnt; /* Valid only if using SMT 7.3 */ 90633f810b2SJeff Kirsher PI_CNTR transmit_cnt; /* Valid only if using SMT 7.3 */ 90733f810b2SJeff Kirsher PI_CNTR tokens; 90833f810b2SJeff Kirsher } PI_CNTR_BLK; 90933f810b2SJeff Kirsher 91033f810b2SJeff Kirsher /* Counters_Get Request */ 91133f810b2SJeff Kirsher 91233f810b2SJeff Kirsher typedef struct 91333f810b2SJeff Kirsher { 91433f810b2SJeff Kirsher PI_UINT32 cmd_type; 91533f810b2SJeff Kirsher } PI_CMD_CNTRS_GET_REQ; 91633f810b2SJeff Kirsher 91733f810b2SJeff Kirsher /* Counters_Get Response */ 91833f810b2SJeff Kirsher 91933f810b2SJeff Kirsher typedef struct 92033f810b2SJeff Kirsher { 92133f810b2SJeff Kirsher PI_RSP_HEADER header; 92233f810b2SJeff Kirsher PI_CNTR time_since_reset; 92333f810b2SJeff Kirsher PI_CNTR_BLK cntrs; 92433f810b2SJeff Kirsher } PI_CMD_CNTRS_GET_RSP; 92533f810b2SJeff Kirsher 92633f810b2SJeff Kirsher /* Counters_Set Request */ 92733f810b2SJeff Kirsher 92833f810b2SJeff Kirsher typedef struct 92933f810b2SJeff Kirsher { 93033f810b2SJeff Kirsher PI_UINT32 cmd_type; 93133f810b2SJeff Kirsher PI_CNTR_BLK cntrs; 93233f810b2SJeff Kirsher } PI_CMD_CNTRS_SET_REQ; 93333f810b2SJeff Kirsher 93433f810b2SJeff Kirsher /* Counters_Set Response */ 93533f810b2SJeff Kirsher 93633f810b2SJeff Kirsher typedef struct 93733f810b2SJeff Kirsher { 93833f810b2SJeff Kirsher PI_RSP_HEADER header; 93933f810b2SJeff Kirsher } PI_CMD_CNTRS_SET_RSP; 94033f810b2SJeff Kirsher 94133f810b2SJeff Kirsher /* Error_Log_Clear Request */ 94233f810b2SJeff Kirsher 94333f810b2SJeff Kirsher typedef struct 94433f810b2SJeff Kirsher { 94533f810b2SJeff Kirsher PI_UINT32 cmd_type; 94633f810b2SJeff Kirsher } PI_CMD_ERROR_LOG_CLEAR_REQ; 94733f810b2SJeff Kirsher 94833f810b2SJeff Kirsher /* Error_Log_Clear Response */ 94933f810b2SJeff Kirsher 95033f810b2SJeff Kirsher typedef struct 95133f810b2SJeff Kirsher { 95233f810b2SJeff Kirsher PI_RSP_HEADER header; 95333f810b2SJeff Kirsher } PI_CMD_ERROR_LOG_CLEAR_RSP; 95433f810b2SJeff Kirsher 95533f810b2SJeff Kirsher /* Error_Log_Get Request */ 95633f810b2SJeff Kirsher 95733f810b2SJeff Kirsher #define PI_LOG_ENTRY_K_INDEX_MIN 0 /* Minimum index for entry */ 95833f810b2SJeff Kirsher 95933f810b2SJeff Kirsher typedef struct 96033f810b2SJeff Kirsher { 96133f810b2SJeff Kirsher PI_UINT32 cmd_type; 96233f810b2SJeff Kirsher PI_UINT32 entry_index; 96333f810b2SJeff Kirsher } PI_CMD_ERROR_LOG_GET_REQ; 96433f810b2SJeff Kirsher 96533f810b2SJeff Kirsher /* Error_Log_Get Response */ 96633f810b2SJeff Kirsher 96733f810b2SJeff Kirsher #define PI_K_LOG_FW_SIZE 111 /* Max number of fw longwords */ 96833f810b2SJeff Kirsher #define PI_K_LOG_DIAG_SIZE 6 /* Max number of diag longwords */ 96933f810b2SJeff Kirsher 97033f810b2SJeff Kirsher typedef struct 97133f810b2SJeff Kirsher { 97233f810b2SJeff Kirsher struct 97333f810b2SJeff Kirsher { 97433f810b2SJeff Kirsher PI_UINT32 fru_imp_mask; 97533f810b2SJeff Kirsher PI_UINT32 test_id; 97633f810b2SJeff Kirsher PI_UINT32 reserved[PI_K_LOG_DIAG_SIZE]; 97733f810b2SJeff Kirsher } diag; 97833f810b2SJeff Kirsher PI_UINT32 fw[PI_K_LOG_FW_SIZE]; 97933f810b2SJeff Kirsher } PI_LOG_ENTRY; 98033f810b2SJeff Kirsher 98133f810b2SJeff Kirsher typedef struct 98233f810b2SJeff Kirsher { 98333f810b2SJeff Kirsher PI_RSP_HEADER header; 98433f810b2SJeff Kirsher PI_UINT32 event_status; 98533f810b2SJeff Kirsher PI_UINT32 caller_id; 98633f810b2SJeff Kirsher PI_UINT32 timestamp_l; 98733f810b2SJeff Kirsher PI_UINT32 timestamp_h; 98833f810b2SJeff Kirsher PI_UINT32 write_count; 98933f810b2SJeff Kirsher PI_LOG_ENTRY entry_info; 99033f810b2SJeff Kirsher } PI_CMD_ERROR_LOG_GET_RSP; 99133f810b2SJeff Kirsher 99233f810b2SJeff Kirsher /* Define error log related constants and types. */ 99333f810b2SJeff Kirsher /* Not all of the caller id's can occur. The only ones currently */ 99433f810b2SJeff Kirsher /* implemented are: none, selftest, mfg, fw, console */ 99533f810b2SJeff Kirsher 99633f810b2SJeff Kirsher #define PI_LOG_EVENT_STATUS_K_VALID 0 /* Valid Event Status */ 99733f810b2SJeff Kirsher #define PI_LOG_EVENT_STATUS_K_INVALID 1 /* Invalid Event Status */ 99833f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_NONE 0 /* No caller */ 99933f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_SELFTEST 1 /* Normal power-up selftest */ 100033f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_MFG 2 /* Mfg power-up selftest */ 100133f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_ONLINE 3 /* On-line diagnostics */ 100233f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_HW 4 /* Hardware */ 100333f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_FW 5 /* Firmware */ 100433f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_CNS_HW 6 /* CNS firmware */ 100533f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_CNS_FW 7 /* CNS hardware */ 100633f810b2SJeff Kirsher #define PI_LOG_CALLER_ID_K_CONSOLE 8 /* Console Caller Id */ 100733f810b2SJeff Kirsher 100833f810b2SJeff Kirsher /* 100933f810b2SJeff Kirsher * Place all DMA commands in the following request and response structures 101033f810b2SJeff Kirsher * to simplify code. 101133f810b2SJeff Kirsher */ 101233f810b2SJeff Kirsher 101333f810b2SJeff Kirsher typedef union 101433f810b2SJeff Kirsher { 101533f810b2SJeff Kirsher PI_UINT32 cmd_type; 101633f810b2SJeff Kirsher PI_CMD_START_REQ start; 101733f810b2SJeff Kirsher PI_CMD_FILTERS_SET_REQ filter_set; 101833f810b2SJeff Kirsher PI_CMD_FILTERS_GET_REQ filter_get; 101933f810b2SJeff Kirsher PI_CMD_CHARS_SET_REQ char_set; 102033f810b2SJeff Kirsher PI_CMD_ADDR_FILTER_SET_REQ addr_filter_set; 102133f810b2SJeff Kirsher PI_CMD_ADDR_FILTER_GET_REQ addr_filter_get; 102233f810b2SJeff Kirsher PI_CMD_STATUS_CHARS_GET_REQ stat_char_get; 102333f810b2SJeff Kirsher PI_CMD_CNTRS_GET_REQ cntrs_get; 102433f810b2SJeff Kirsher PI_CMD_CNTRS_SET_REQ cntrs_set; 102533f810b2SJeff Kirsher PI_CMD_ERROR_LOG_CLEAR_REQ error_log_clear; 102633f810b2SJeff Kirsher PI_CMD_ERROR_LOG_GET_REQ error_log_read; 102733f810b2SJeff Kirsher PI_CMD_SNMP_SET_REQ snmp_set; 102833f810b2SJeff Kirsher PI_CMD_FDDI_MIB_GET_REQ fddi_mib_get; 102933f810b2SJeff Kirsher PI_CMD_DEC_EXT_MIB_GET_REQ dec_mib_get; 103033f810b2SJeff Kirsher PI_CMD_SMT_MIB_SET_REQ smt_mib_set; 103133f810b2SJeff Kirsher PI_CMD_SMT_MIB_GET_REQ smt_mib_get; 103233f810b2SJeff Kirsher char pad[PI_CMD_REQ_K_SIZE_MAX]; 103333f810b2SJeff Kirsher } PI_DMA_CMD_REQ; 103433f810b2SJeff Kirsher 103533f810b2SJeff Kirsher typedef union 103633f810b2SJeff Kirsher { 103733f810b2SJeff Kirsher PI_RSP_HEADER header; 103833f810b2SJeff Kirsher PI_CMD_START_RSP start; 103933f810b2SJeff Kirsher PI_CMD_FILTERS_SET_RSP filter_set; 104033f810b2SJeff Kirsher PI_CMD_FILTERS_GET_RSP filter_get; 104133f810b2SJeff Kirsher PI_CMD_CHARS_SET_RSP char_set; 104233f810b2SJeff Kirsher PI_CMD_ADDR_FILTER_SET_RSP addr_filter_set; 104333f810b2SJeff Kirsher PI_CMD_ADDR_FILTER_GET_RSP addr_filter_get; 104433f810b2SJeff Kirsher PI_CMD_STATUS_CHARS_GET_RSP stat_char_get; 104533f810b2SJeff Kirsher PI_CMD_CNTRS_GET_RSP cntrs_get; 104633f810b2SJeff Kirsher PI_CMD_CNTRS_SET_RSP cntrs_set; 104733f810b2SJeff Kirsher PI_CMD_ERROR_LOG_CLEAR_RSP error_log_clear; 104833f810b2SJeff Kirsher PI_CMD_ERROR_LOG_GET_RSP error_log_get; 104933f810b2SJeff Kirsher PI_CMD_SNMP_SET_RSP snmp_set; 105033f810b2SJeff Kirsher PI_CMD_FDDI_MIB_GET_RSP fddi_mib_get; 105133f810b2SJeff Kirsher PI_CMD_DEC_EXT_MIB_GET_RSP dec_mib_get; 105233f810b2SJeff Kirsher PI_CMD_SMT_MIB_SET_RSP smt_mib_set; 105333f810b2SJeff Kirsher PI_CMD_SMT_MIB_GET_RSP smt_mib_get; 105433f810b2SJeff Kirsher char pad[PI_CMD_RSP_K_SIZE_MAX]; 105533f810b2SJeff Kirsher } PI_DMA_CMD_RSP; 105633f810b2SJeff Kirsher 105733f810b2SJeff Kirsher typedef union 105833f810b2SJeff Kirsher { 105933f810b2SJeff Kirsher PI_DMA_CMD_REQ request; 106033f810b2SJeff Kirsher PI_DMA_CMD_RSP response; 106133f810b2SJeff Kirsher } PI_DMA_CMD_BUFFER; 106233f810b2SJeff Kirsher 106333f810b2SJeff Kirsher 106433f810b2SJeff Kirsher /* Define format of Consumer Block (resident in host memory) */ 106533f810b2SJeff Kirsher 106633f810b2SJeff Kirsher typedef struct 106733f810b2SJeff Kirsher { 106833f810b2SJeff Kirsher volatile PI_UINT32 xmt_rcv_data; 106933f810b2SJeff Kirsher volatile PI_UINT32 reserved_1; 107033f810b2SJeff Kirsher volatile PI_UINT32 smt_host; 107133f810b2SJeff Kirsher volatile PI_UINT32 reserved_2; 107233f810b2SJeff Kirsher volatile PI_UINT32 unsol; 107333f810b2SJeff Kirsher volatile PI_UINT32 reserved_3; 107433f810b2SJeff Kirsher volatile PI_UINT32 cmd_rsp; 107533f810b2SJeff Kirsher volatile PI_UINT32 reserved_4; 107633f810b2SJeff Kirsher volatile PI_UINT32 cmd_req; 107733f810b2SJeff Kirsher volatile PI_UINT32 reserved_5; 107833f810b2SJeff Kirsher } PI_CONSUMER_BLOCK; 107933f810b2SJeff Kirsher 108033f810b2SJeff Kirsher #define PI_CONS_M_RCV_INDEX 0x000000FF 108133f810b2SJeff Kirsher #define PI_CONS_M_XMT_INDEX 0x00FF0000 108233f810b2SJeff Kirsher #define PI_CONS_V_RCV_INDEX 0 108333f810b2SJeff Kirsher #define PI_CONS_V_XMT_INDEX 16 108433f810b2SJeff Kirsher 108533f810b2SJeff Kirsher /* Offsets into consumer block */ 108633f810b2SJeff Kirsher 108733f810b2SJeff Kirsher #define PI_CONS_BLK_K_XMT_RCV 0x00 108833f810b2SJeff Kirsher #define PI_CONS_BLK_K_SMT_HOST 0x08 108933f810b2SJeff Kirsher #define PI_CONS_BLK_K_UNSOL 0x10 109033f810b2SJeff Kirsher #define PI_CONS_BLK_K_CMD_RSP 0x18 109133f810b2SJeff Kirsher #define PI_CONS_BLK_K_CMD_REQ 0x20 109233f810b2SJeff Kirsher 109333f810b2SJeff Kirsher /* Offsets into descriptor block */ 109433f810b2SJeff Kirsher 109533f810b2SJeff Kirsher #define PI_DESCR_BLK_K_RCV_DATA 0x0000 109633f810b2SJeff Kirsher #define PI_DESCR_BLK_K_XMT_DATA 0x0800 109733f810b2SJeff Kirsher #define PI_DESCR_BLK_K_SMT_HOST 0x1000 109833f810b2SJeff Kirsher #define PI_DESCR_BLK_K_UNSOL 0x1200 109933f810b2SJeff Kirsher #define PI_DESCR_BLK_K_CMD_RSP 0x1280 110033f810b2SJeff Kirsher #define PI_DESCR_BLK_K_CMD_REQ 0x1300 110133f810b2SJeff Kirsher 110233f810b2SJeff Kirsher /* Define format of a rcv descr (Rcv Data, Cmd Rsp, Unsolicited, SMT Host) */ 110333f810b2SJeff Kirsher /* Note a field has been added for later versions of the PDQ to allow for */ 110433f810b2SJeff Kirsher /* finer granularity of the rcv buffer alignment. For backwards */ 110533f810b2SJeff Kirsher /* compatibility, the two bits (which allow the rcv buffer to be longword */ 110633f810b2SJeff Kirsher /* aligned) have been added at the MBZ bits. To support previous drivers, */ 110733f810b2SJeff Kirsher /* the MBZ definition is left intact. */ 110833f810b2SJeff Kirsher 110933f810b2SJeff Kirsher typedef struct 111033f810b2SJeff Kirsher { 111133f810b2SJeff Kirsher PI_UINT32 long_0; 111233f810b2SJeff Kirsher PI_UINT32 long_1; 111333f810b2SJeff Kirsher } PI_RCV_DESCR; 111433f810b2SJeff Kirsher 111533f810b2SJeff Kirsher #define PI_RCV_DESCR_M_SOP 0x80000000 111633f810b2SJeff Kirsher #define PI_RCV_DESCR_M_SEG_LEN_LO 0x60000000 111733f810b2SJeff Kirsher #define PI_RCV_DESCR_M_MBZ 0x60000000 111833f810b2SJeff Kirsher #define PI_RCV_DESCR_M_SEG_LEN 0x1F800000 111933f810b2SJeff Kirsher #define PI_RCV_DESCR_M_SEG_LEN_HI 0x1FF00000 112033f810b2SJeff Kirsher #define PI_RCV_DESCR_M_SEG_CNT 0x000F0000 112133f810b2SJeff Kirsher #define PI_RCV_DESCR_M_BUFF_HI 0x0000FFFF 112233f810b2SJeff Kirsher 112333f810b2SJeff Kirsher #define PI_RCV_DESCR_V_SOP 31 112433f810b2SJeff Kirsher #define PI_RCV_DESCR_V_SEG_LEN_LO 29 112533f810b2SJeff Kirsher #define PI_RCV_DESCR_V_MBZ 29 112633f810b2SJeff Kirsher #define PI_RCV_DESCR_V_SEG_LEN 23 112733f810b2SJeff Kirsher #define PI_RCV_DESCR_V_SEG_LEN_HI 20 112833f810b2SJeff Kirsher #define PI_RCV_DESCR_V_SEG_CNT 16 112933f810b2SJeff Kirsher #define PI_RCV_DESCR_V_BUFF_HI 0 113033f810b2SJeff Kirsher 113133f810b2SJeff Kirsher /* Define the format of a transmit descriptor (Xmt Data, Cmd Req) */ 113233f810b2SJeff Kirsher 113333f810b2SJeff Kirsher typedef struct 113433f810b2SJeff Kirsher { 113533f810b2SJeff Kirsher PI_UINT32 long_0; 113633f810b2SJeff Kirsher PI_UINT32 long_1; 113733f810b2SJeff Kirsher } PI_XMT_DESCR; 113833f810b2SJeff Kirsher 113933f810b2SJeff Kirsher #define PI_XMT_DESCR_M_SOP 0x80000000 114033f810b2SJeff Kirsher #define PI_XMT_DESCR_M_EOP 0x40000000 114133f810b2SJeff Kirsher #define PI_XMT_DESCR_M_MBZ 0x20000000 114233f810b2SJeff Kirsher #define PI_XMT_DESCR_M_SEG_LEN 0x1FFF0000 114333f810b2SJeff Kirsher #define PI_XMT_DESCR_M_BUFF_HI 0x0000FFFF 114433f810b2SJeff Kirsher 114533f810b2SJeff Kirsher #define PI_XMT_DESCR_V_SOP 31 114633f810b2SJeff Kirsher #define PI_XMT_DESCR_V_EOP 30 114733f810b2SJeff Kirsher #define PI_XMT_DESCR_V_MBZ 29 114833f810b2SJeff Kirsher #define PI_XMT_DESCR_V_SEG_LEN 16 114933f810b2SJeff Kirsher #define PI_XMT_DESCR_V_BUFF_HI 0 115033f810b2SJeff Kirsher 115133f810b2SJeff Kirsher /* Define format of the Descriptor Block (resident in host memory) */ 115233f810b2SJeff Kirsher 115333f810b2SJeff Kirsher #define PI_RCV_DATA_K_NUM_ENTRIES 256 115433f810b2SJeff Kirsher #define PI_XMT_DATA_K_NUM_ENTRIES 256 115533f810b2SJeff Kirsher #define PI_SMT_HOST_K_NUM_ENTRIES 64 115633f810b2SJeff Kirsher #define PI_UNSOL_K_NUM_ENTRIES 16 115733f810b2SJeff Kirsher #define PI_CMD_RSP_K_NUM_ENTRIES 16 115833f810b2SJeff Kirsher #define PI_CMD_REQ_K_NUM_ENTRIES 16 115933f810b2SJeff Kirsher 116033f810b2SJeff Kirsher typedef struct 116133f810b2SJeff Kirsher { 116233f810b2SJeff Kirsher PI_RCV_DESCR rcv_data[PI_RCV_DATA_K_NUM_ENTRIES]; 116333f810b2SJeff Kirsher PI_XMT_DESCR xmt_data[PI_XMT_DATA_K_NUM_ENTRIES]; 116433f810b2SJeff Kirsher PI_RCV_DESCR smt_host[PI_SMT_HOST_K_NUM_ENTRIES]; 116533f810b2SJeff Kirsher PI_RCV_DESCR unsol[PI_UNSOL_K_NUM_ENTRIES]; 116633f810b2SJeff Kirsher PI_RCV_DESCR cmd_rsp[PI_CMD_RSP_K_NUM_ENTRIES]; 116733f810b2SJeff Kirsher PI_XMT_DESCR cmd_req[PI_CMD_REQ_K_NUM_ENTRIES]; 116833f810b2SJeff Kirsher } PI_DESCR_BLOCK; 116933f810b2SJeff Kirsher 117033f810b2SJeff Kirsher /* Define Port Registers - offsets from PDQ Base address */ 117133f810b2SJeff Kirsher 117233f810b2SJeff Kirsher #define PI_PDQ_K_REG_PORT_RESET 0x00000000 117333f810b2SJeff Kirsher #define PI_PDQ_K_REG_HOST_DATA 0x00000004 117433f810b2SJeff Kirsher #define PI_PDQ_K_REG_PORT_CTRL 0x00000008 117533f810b2SJeff Kirsher #define PI_PDQ_K_REG_PORT_DATA_A 0x0000000C 117633f810b2SJeff Kirsher #define PI_PDQ_K_REG_PORT_DATA_B 0x00000010 117733f810b2SJeff Kirsher #define PI_PDQ_K_REG_PORT_STATUS 0x00000014 117833f810b2SJeff Kirsher #define PI_PDQ_K_REG_TYPE_0_STATUS 0x00000018 117933f810b2SJeff Kirsher #define PI_PDQ_K_REG_HOST_INT_ENB 0x0000001C 118033f810b2SJeff Kirsher #define PI_PDQ_K_REG_TYPE_2_PROD_NOINT 0x00000020 118133f810b2SJeff Kirsher #define PI_PDQ_K_REG_TYPE_2_PROD 0x00000024 118233f810b2SJeff Kirsher #define PI_PDQ_K_REG_CMD_RSP_PROD 0x00000028 118333f810b2SJeff Kirsher #define PI_PDQ_K_REG_CMD_REQ_PROD 0x0000002C 118433f810b2SJeff Kirsher #define PI_PDQ_K_REG_SMT_HOST_PROD 0x00000030 118533f810b2SJeff Kirsher #define PI_PDQ_K_REG_UNSOL_PROD 0x00000034 118633f810b2SJeff Kirsher 118733f810b2SJeff Kirsher /* Port Control Register - Command codes for primary commands */ 118833f810b2SJeff Kirsher 118933f810b2SJeff Kirsher #define PI_PCTRL_M_CMD_ERROR 0x8000 119033f810b2SJeff Kirsher #define PI_PCTRL_M_BLAST_FLASH 0x4000 119133f810b2SJeff Kirsher #define PI_PCTRL_M_HALT 0x2000 119233f810b2SJeff Kirsher #define PI_PCTRL_M_COPY_DATA 0x1000 119333f810b2SJeff Kirsher #define PI_PCTRL_M_ERROR_LOG_START 0x0800 119433f810b2SJeff Kirsher #define PI_PCTRL_M_ERROR_LOG_READ 0x0400 119533f810b2SJeff Kirsher #define PI_PCTRL_M_XMT_DATA_FLUSH_DONE 0x0200 119633f810b2SJeff Kirsher #define PI_PCTRL_M_INIT 0x0100 119733f810b2SJeff Kirsher #define PI_PCTRL_M_INIT_START 0x0080 119833f810b2SJeff Kirsher #define PI_PCTRL_M_CONS_BLOCK 0x0040 119933f810b2SJeff Kirsher #define PI_PCTRL_M_UNINIT 0x0020 120033f810b2SJeff Kirsher #define PI_PCTRL_M_RING_MEMBER 0x0010 120133f810b2SJeff Kirsher #define PI_PCTRL_M_MLA 0x0008 120233f810b2SJeff Kirsher #define PI_PCTRL_M_FW_REV_READ 0x0004 120333f810b2SJeff Kirsher #define PI_PCTRL_M_DEV_SPECIFIC 0x0002 120433f810b2SJeff Kirsher #define PI_PCTRL_M_SUB_CMD 0x0001 120533f810b2SJeff Kirsher 120633f810b2SJeff Kirsher /* Define sub-commands accessed via the PI_PCTRL_M_SUB_CMD command */ 120733f810b2SJeff Kirsher 120833f810b2SJeff Kirsher #define PI_SUB_CMD_K_LINK_UNINIT 0x0001 120933f810b2SJeff Kirsher #define PI_SUB_CMD_K_BURST_SIZE_SET 0x0002 121033f810b2SJeff Kirsher #define PI_SUB_CMD_K_PDQ_REV_GET 0x0004 121133f810b2SJeff Kirsher #define PI_SUB_CMD_K_HW_REV_GET 0x0008 121233f810b2SJeff Kirsher 121333f810b2SJeff Kirsher /* Define some Port Data B values */ 121433f810b2SJeff Kirsher 121533f810b2SJeff Kirsher #define PI_PDATA_B_DMA_BURST_SIZE_4 0 /* valid values for command */ 121633f810b2SJeff Kirsher #define PI_PDATA_B_DMA_BURST_SIZE_8 1 121733f810b2SJeff Kirsher #define PI_PDATA_B_DMA_BURST_SIZE_16 2 121833f810b2SJeff Kirsher #define PI_PDATA_B_DMA_BURST_SIZE_32 3 /* not supported on PCI */ 121933f810b2SJeff Kirsher #define PI_PDATA_B_DMA_BURST_SIZE_DEF PI_PDATA_B_DMA_BURST_SIZE_16 122033f810b2SJeff Kirsher 122133f810b2SJeff Kirsher /* Port Data A Reset state */ 122233f810b2SJeff Kirsher 122333f810b2SJeff Kirsher #define PI_PDATA_A_RESET_M_UPGRADE 0x00000001 122433f810b2SJeff Kirsher #define PI_PDATA_A_RESET_M_SOFT_RESET 0x00000002 122533f810b2SJeff Kirsher #define PI_PDATA_A_RESET_M_SKIP_ST 0x00000004 122633f810b2SJeff Kirsher 122733f810b2SJeff Kirsher /* Read adapter MLA address port control command constants */ 122833f810b2SJeff Kirsher 122933f810b2SJeff Kirsher #define PI_PDATA_A_MLA_K_LO 0 123033f810b2SJeff Kirsher #define PI_PDATA_A_MLA_K_HI 1 123133f810b2SJeff Kirsher 123233f810b2SJeff Kirsher /* Byte Swap values for init command */ 123333f810b2SJeff Kirsher 123433f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_DESC_BLK_ADDR 0x0FFFFE000 123533f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_RESERVED 0x000001FFC 123633f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_BSWAP_DATA 0x000000002 123733f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_BSWAP_LITERAL 0x000000001 123833f810b2SJeff Kirsher 123933f810b2SJeff Kirsher #define PI_PDATA_A_INIT_V_DESC_BLK_ADDR 13 124033f810b2SJeff Kirsher #define PI_PDATA_A_INIT_V_RESERVED 3 124133f810b2SJeff Kirsher #define PI_PDATA_A_INIT_V_BSWAP_DATA 1 124233f810b2SJeff Kirsher #define PI_PDATA_A_INIT_V_BSWAP_LITERAL 0 124333f810b2SJeff Kirsher 124433f810b2SJeff Kirsher /* Port Reset Register */ 124533f810b2SJeff Kirsher 124633f810b2SJeff Kirsher #define PI_RESET_M_ASSERT_RESET 1 124733f810b2SJeff Kirsher 124833f810b2SJeff Kirsher /* Port Status register */ 124933f810b2SJeff Kirsher 125033f810b2SJeff Kirsher #define PI_PSTATUS_V_RCV_DATA_PENDING 31 125133f810b2SJeff Kirsher #define PI_PSTATUS_V_XMT_DATA_PENDING 30 125233f810b2SJeff Kirsher #define PI_PSTATUS_V_SMT_HOST_PENDING 29 125333f810b2SJeff Kirsher #define PI_PSTATUS_V_UNSOL_PENDING 28 125433f810b2SJeff Kirsher #define PI_PSTATUS_V_CMD_RSP_PENDING 27 125533f810b2SJeff Kirsher #define PI_PSTATUS_V_CMD_REQ_PENDING 26 125633f810b2SJeff Kirsher #define PI_PSTATUS_V_TYPE_0_PENDING 25 125733f810b2SJeff Kirsher #define PI_PSTATUS_V_RESERVED_1 16 125833f810b2SJeff Kirsher #define PI_PSTATUS_V_RESERVED_2 11 125933f810b2SJeff Kirsher #define PI_PSTATUS_V_STATE 8 126033f810b2SJeff Kirsher #define PI_PSTATUS_V_HALT_ID 0 126133f810b2SJeff Kirsher 126233f810b2SJeff Kirsher #define PI_PSTATUS_M_RCV_DATA_PENDING 0x80000000 126333f810b2SJeff Kirsher #define PI_PSTATUS_M_XMT_DATA_PENDING 0x40000000 126433f810b2SJeff Kirsher #define PI_PSTATUS_M_SMT_HOST_PENDING 0x20000000 126533f810b2SJeff Kirsher #define PI_PSTATUS_M_UNSOL_PENDING 0x10000000 126633f810b2SJeff Kirsher #define PI_PSTATUS_M_CMD_RSP_PENDING 0x08000000 126733f810b2SJeff Kirsher #define PI_PSTATUS_M_CMD_REQ_PENDING 0x04000000 126833f810b2SJeff Kirsher #define PI_PSTATUS_M_TYPE_0_PENDING 0x02000000 126933f810b2SJeff Kirsher #define PI_PSTATUS_M_RESERVED_1 0x01FF0000 127033f810b2SJeff Kirsher #define PI_PSTATUS_M_RESERVED_2 0x0000F800 127133f810b2SJeff Kirsher #define PI_PSTATUS_M_STATE 0x00000700 127233f810b2SJeff Kirsher #define PI_PSTATUS_M_HALT_ID 0x000000FF 127333f810b2SJeff Kirsher 127433f810b2SJeff Kirsher /* Define Halt Id's */ 127533f810b2SJeff Kirsher /* Do not insert into this list, only append. */ 127633f810b2SJeff Kirsher 127733f810b2SJeff Kirsher #define PI_HALT_ID_K_SELFTEST_TIMEOUT 0 127833f810b2SJeff Kirsher #define PI_HALT_ID_K_PARITY_ERROR 1 127933f810b2SJeff Kirsher #define PI_HALT_ID_K_HOST_DIR_HALT 2 128033f810b2SJeff Kirsher #define PI_HALT_ID_K_SW_FAULT 3 128133f810b2SJeff Kirsher #define PI_HALT_ID_K_HW_FAULT 4 128233f810b2SJeff Kirsher #define PI_HALT_ID_K_PC_TRACE 5 128333f810b2SJeff Kirsher #define PI_HALT_ID_K_DMA_ERROR 6 /* Host Data has error reg */ 128433f810b2SJeff Kirsher #define PI_HALT_ID_K_IMAGE_CRC_ERROR 7 /* Image is bad, update it */ 128533f810b2SJeff Kirsher #define PI_HALT_ID_K_BUS_EXCEPTION 8 /* 68K bus exception */ 128633f810b2SJeff Kirsher 128733f810b2SJeff Kirsher /* Host Interrupt Enable Register as seen by host */ 128833f810b2SJeff Kirsher 128933f810b2SJeff Kirsher #define PI_HOST_INT_M_XMT_DATA_ENB 0x80000000 /* Type 2 Enables */ 129033f810b2SJeff Kirsher #define PI_HOST_INT_M_RCV_DATA_ENB 0x40000000 129133f810b2SJeff Kirsher #define PI_HOST_INT_M_SMT_HOST_ENB 0x10000000 /* Type 1 Enables */ 129233f810b2SJeff Kirsher #define PI_HOST_INT_M_UNSOL_ENB 0x20000000 129333f810b2SJeff Kirsher #define PI_HOST_INT_M_CMD_RSP_ENB 0x08000000 129433f810b2SJeff Kirsher #define PI_HOST_INT_M_CMD_REQ_ENB 0x04000000 129533f810b2SJeff Kirsher #define PI_HOST_INT_M_TYPE_1_RESERVED 0x00FF0000 129633f810b2SJeff Kirsher #define PI_HOST_INT_M_TYPE_0_RESERVED 0x0000FF00 /* Type 0 Enables */ 129733f810b2SJeff Kirsher #define PI_HOST_INT_M_1MS 0x00000080 129833f810b2SJeff Kirsher #define PI_HOST_INT_M_20MS 0x00000040 129933f810b2SJeff Kirsher #define PI_HOST_INT_M_CSR_CMD_DONE 0x00000020 130033f810b2SJeff Kirsher #define PI_HOST_INT_M_STATE_CHANGE 0x00000010 130133f810b2SJeff Kirsher #define PI_HOST_INT_M_XMT_FLUSH 0x00000008 130233f810b2SJeff Kirsher #define PI_HOST_INT_M_NXM 0x00000004 130333f810b2SJeff Kirsher #define PI_HOST_INT_M_PM_PAR_ERR 0x00000002 130433f810b2SJeff Kirsher #define PI_HOST_INT_M_BUS_PAR_ERR 0x00000001 130533f810b2SJeff Kirsher 130633f810b2SJeff Kirsher #define PI_HOST_INT_V_XMT_DATA_ENB 31 /* Type 2 Enables */ 130733f810b2SJeff Kirsher #define PI_HOST_INT_V_RCV_DATA_ENB 30 130833f810b2SJeff Kirsher #define PI_HOST_INT_V_SMT_HOST_ENB 29 /* Type 1 Enables */ 130933f810b2SJeff Kirsher #define PI_HOST_INT_V_UNSOL_ENB 28 131033f810b2SJeff Kirsher #define PI_HOST_INT_V_CMD_RSP_ENB 27 131133f810b2SJeff Kirsher #define PI_HOST_INT_V_CMD_REQ_ENB 26 131233f810b2SJeff Kirsher #define PI_HOST_INT_V_TYPE_1_RESERVED 16 131333f810b2SJeff Kirsher #define PI_HOST_INT_V_TYPE_0_RESERVED 8 /* Type 0 Enables */ 131433f810b2SJeff Kirsher #define PI_HOST_INT_V_1MS_ENB 7 131533f810b2SJeff Kirsher #define PI_HOST_INT_V_20MS_ENB 6 131633f810b2SJeff Kirsher #define PI_HOST_INT_V_CSR_CMD_DONE_ENB 5 131733f810b2SJeff Kirsher #define PI_HOST_INT_V_STATE_CHANGE_ENB 4 131833f810b2SJeff Kirsher #define PI_HOST_INT_V_XMT_FLUSH_ENB 3 131933f810b2SJeff Kirsher #define PI_HOST_INT_V_NXM_ENB 2 132033f810b2SJeff Kirsher #define PI_HOST_INT_V_PM_PAR_ERR_ENB 1 132133f810b2SJeff Kirsher #define PI_HOST_INT_V_BUS_PAR_ERR_ENB 0 132233f810b2SJeff Kirsher 132333f810b2SJeff Kirsher #define PI_HOST_INT_K_ACK_ALL_TYPE_0 0x000000FF 132433f810b2SJeff Kirsher #define PI_HOST_INT_K_DISABLE_ALL_INTS 0x00000000 132533f810b2SJeff Kirsher #define PI_HOST_INT_K_ENABLE_ALL_INTS 0xFFFFFFFF 132633f810b2SJeff Kirsher #define PI_HOST_INT_K_ENABLE_DEF_INTS 0xC000001F 132733f810b2SJeff Kirsher 132833f810b2SJeff Kirsher /* Type 0 Interrupt Status Register */ 132933f810b2SJeff Kirsher 133033f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_1MS 0x00000080 133133f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_20MS 0x00000040 133233f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_CSR_CMD_DONE 0x00000020 133333f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_STATE_CHANGE 0x00000010 133433f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_XMT_FLUSH 0x00000008 133533f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_NXM 0x00000004 133633f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_PM_PAR_ERR 0x00000002 133733f810b2SJeff Kirsher #define PI_TYPE_0_STAT_M_BUS_PAR_ERR 0x00000001 133833f810b2SJeff Kirsher 133933f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_1MS 7 134033f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_20MS 6 134133f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_CSR_CMD_DONE 5 134233f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_STATE_CHANGE 4 134333f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_XMT_FLUSH 3 134433f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_NXM 2 134533f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_PM_PAR_ERR 1 134633f810b2SJeff Kirsher #define PI_TYPE_0_STAT_V_BUS_PAR_ERR 0 134733f810b2SJeff Kirsher 134833f810b2SJeff Kirsher /* Register definition structures are defined for both big and little endian systems */ 134933f810b2SJeff Kirsher 135033f810b2SJeff Kirsher #ifndef __BIG_ENDIAN 135133f810b2SJeff Kirsher 135233f810b2SJeff Kirsher /* Little endian format of Type 1 Producer register */ 135333f810b2SJeff Kirsher 135433f810b2SJeff Kirsher typedef union 135533f810b2SJeff Kirsher { 135633f810b2SJeff Kirsher PI_UINT32 lword; 135733f810b2SJeff Kirsher struct 135833f810b2SJeff Kirsher { 135933f810b2SJeff Kirsher PI_UINT8 prod; 136033f810b2SJeff Kirsher PI_UINT8 comp; 136133f810b2SJeff Kirsher PI_UINT8 mbz_1; 136233f810b2SJeff Kirsher PI_UINT8 mbz_2; 136333f810b2SJeff Kirsher } index; 136433f810b2SJeff Kirsher } PI_TYPE_1_PROD_REG; 136533f810b2SJeff Kirsher 136633f810b2SJeff Kirsher /* Little endian format of Type 2 Producer register */ 136733f810b2SJeff Kirsher 136833f810b2SJeff Kirsher typedef union 136933f810b2SJeff Kirsher { 137033f810b2SJeff Kirsher PI_UINT32 lword; 137133f810b2SJeff Kirsher struct 137233f810b2SJeff Kirsher { 137333f810b2SJeff Kirsher PI_UINT8 rcv_prod; 137433f810b2SJeff Kirsher PI_UINT8 xmt_prod; 137533f810b2SJeff Kirsher PI_UINT8 rcv_comp; 137633f810b2SJeff Kirsher PI_UINT8 xmt_comp; 137733f810b2SJeff Kirsher } index; 137833f810b2SJeff Kirsher } PI_TYPE_2_PROD_REG; 137933f810b2SJeff Kirsher 138033f810b2SJeff Kirsher /* Little endian format of Type 1 Consumer Block longword */ 138133f810b2SJeff Kirsher 138233f810b2SJeff Kirsher typedef union 138333f810b2SJeff Kirsher { 138433f810b2SJeff Kirsher PI_UINT32 lword; 138533f810b2SJeff Kirsher struct 138633f810b2SJeff Kirsher { 138733f810b2SJeff Kirsher PI_UINT8 cons; 138833f810b2SJeff Kirsher PI_UINT8 res0; 138933f810b2SJeff Kirsher PI_UINT8 res1; 139033f810b2SJeff Kirsher PI_UINT8 res2; 139133f810b2SJeff Kirsher } index; 139233f810b2SJeff Kirsher } PI_TYPE_1_CONSUMER; 139333f810b2SJeff Kirsher 139433f810b2SJeff Kirsher /* Little endian format of Type 2 Consumer Block longword */ 139533f810b2SJeff Kirsher 139633f810b2SJeff Kirsher typedef union 139733f810b2SJeff Kirsher { 139833f810b2SJeff Kirsher PI_UINT32 lword; 139933f810b2SJeff Kirsher struct 140033f810b2SJeff Kirsher { 140133f810b2SJeff Kirsher PI_UINT8 rcv_cons; 140233f810b2SJeff Kirsher PI_UINT8 res0; 140333f810b2SJeff Kirsher PI_UINT8 xmt_cons; 140433f810b2SJeff Kirsher PI_UINT8 res1; 140533f810b2SJeff Kirsher } index; 140633f810b2SJeff Kirsher } PI_TYPE_2_CONSUMER; 140733f810b2SJeff Kirsher 140833f810b2SJeff Kirsher /* Define swapping required by DMA transfers. */ 140933f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_BSWAP_INIT \ 141033f810b2SJeff Kirsher (PI_PDATA_A_INIT_M_BSWAP_DATA) 141133f810b2SJeff Kirsher 141233f810b2SJeff Kirsher #else /* __BIG_ENDIAN */ 141333f810b2SJeff Kirsher 141433f810b2SJeff Kirsher /* Big endian format of Type 1 Producer register */ 141533f810b2SJeff Kirsher 141633f810b2SJeff Kirsher typedef union 141733f810b2SJeff Kirsher { 141833f810b2SJeff Kirsher PI_UINT32 lword; 141933f810b2SJeff Kirsher struct 142033f810b2SJeff Kirsher { 142133f810b2SJeff Kirsher PI_UINT8 mbz_2; 142233f810b2SJeff Kirsher PI_UINT8 mbz_1; 142333f810b2SJeff Kirsher PI_UINT8 comp; 142433f810b2SJeff Kirsher PI_UINT8 prod; 142533f810b2SJeff Kirsher } index; 142633f810b2SJeff Kirsher } PI_TYPE_1_PROD_REG; 142733f810b2SJeff Kirsher 142833f810b2SJeff Kirsher /* Big endian format of Type 2 Producer register */ 142933f810b2SJeff Kirsher 143033f810b2SJeff Kirsher typedef union 143133f810b2SJeff Kirsher { 143233f810b2SJeff Kirsher PI_UINT32 lword; 143333f810b2SJeff Kirsher struct 143433f810b2SJeff Kirsher { 143533f810b2SJeff Kirsher PI_UINT8 xmt_comp; 143633f810b2SJeff Kirsher PI_UINT8 rcv_comp; 143733f810b2SJeff Kirsher PI_UINT8 xmt_prod; 143833f810b2SJeff Kirsher PI_UINT8 rcv_prod; 143933f810b2SJeff Kirsher } index; 144033f810b2SJeff Kirsher } PI_TYPE_2_PROD_REG; 144133f810b2SJeff Kirsher 144233f810b2SJeff Kirsher /* Big endian format of Type 1 Consumer Block longword */ 144333f810b2SJeff Kirsher 144433f810b2SJeff Kirsher typedef union 144533f810b2SJeff Kirsher { 144633f810b2SJeff Kirsher PI_UINT32 lword; 144733f810b2SJeff Kirsher struct 144833f810b2SJeff Kirsher { 144933f810b2SJeff Kirsher PI_UINT8 res2; 145033f810b2SJeff Kirsher PI_UINT8 res1; 145133f810b2SJeff Kirsher PI_UINT8 res0; 145233f810b2SJeff Kirsher PI_UINT8 cons; 145333f810b2SJeff Kirsher } index; 145433f810b2SJeff Kirsher } PI_TYPE_1_CONSUMER; 145533f810b2SJeff Kirsher 145633f810b2SJeff Kirsher /* Big endian format of Type 2 Consumer Block longword */ 145733f810b2SJeff Kirsher 145833f810b2SJeff Kirsher typedef union 145933f810b2SJeff Kirsher { 146033f810b2SJeff Kirsher PI_UINT32 lword; 146133f810b2SJeff Kirsher struct 146233f810b2SJeff Kirsher { 146333f810b2SJeff Kirsher PI_UINT8 res1; 146433f810b2SJeff Kirsher PI_UINT8 xmt_cons; 146533f810b2SJeff Kirsher PI_UINT8 res0; 146633f810b2SJeff Kirsher PI_UINT8 rcv_cons; 146733f810b2SJeff Kirsher } index; 146833f810b2SJeff Kirsher } PI_TYPE_2_CONSUMER; 146933f810b2SJeff Kirsher 147033f810b2SJeff Kirsher /* Define swapping required by DMA transfers. */ 147133f810b2SJeff Kirsher #define PI_PDATA_A_INIT_M_BSWAP_INIT \ 147233f810b2SJeff Kirsher (PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL) 147333f810b2SJeff Kirsher 147433f810b2SJeff Kirsher #endif /* __BIG_ENDIAN */ 147533f810b2SJeff Kirsher 147633f810b2SJeff Kirsher /* Define TC PDQ CSR offset and length */ 147733f810b2SJeff Kirsher 147833f810b2SJeff Kirsher #define PI_TC_K_CSR_OFFSET 0x100000 147933f810b2SJeff Kirsher #define PI_TC_K_CSR_LEN 0x40 /* 64 bytes */ 148033f810b2SJeff Kirsher 148133f810b2SJeff Kirsher /* Define EISA controller register offsets */ 148233f810b2SJeff Kirsher 1483b98dfaf2SMaciej W. Rozycki #define PI_ESIC_K_CSR_IO_LEN 0x40 /* 64 bytes */ 1484b98dfaf2SMaciej W. Rozycki #define PI_ESIC_K_BURST_HOLDOFF_LEN 0x04 /* 4 bytes */ 14854d0438e5SMaciej W. Rozycki #define PI_ESIC_K_ESIC_CSR_LEN 0x40 /* 64 bytes */ 148633f810b2SJeff Kirsher 1487b98dfaf2SMaciej W. Rozycki #define PI_DEFEA_K_CSR_IO 0x000 148833f810b2SJeff Kirsher #define PI_DEFEA_K_BURST_HOLDOFF 0x040 14894d0438e5SMaciej W. Rozycki #define PI_ESIC_K_ESIC_CSR 0xC80 149033f810b2SJeff Kirsher 149133f810b2SJeff Kirsher #define PI_ESIC_K_SLOT_ID 0xC80 149233f810b2SJeff Kirsher #define PI_ESIC_K_SLOT_CNTRL 0xC84 149333f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_CMP_0 0xC85 149433f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_CMP_1 0xC86 149533f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_CMP_2 0xC87 149633f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_HI_CMP_0 0xC88 149733f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_HI_CMP_1 0xC89 149833f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_HI_CMP_2 0xC8A 149933f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_MASK_0 0xC8B 150033f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_MASK_1 0xC8C 150133f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_MASK_2 0xC8D 150233f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_LO_CMP_0 0xC8E 150333f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_LO_CMP_1 0xC8F 150433f810b2SJeff Kirsher #define PI_ESIC_K_MEM_ADD_LO_CMP_2 0xC90 150533f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_0_0 0xC91 150633f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_0_1 0xC92 150733f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_1_0 0xC93 150833f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_1_1 0xC94 150933f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_2_0 0xC95 151033f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_2_1 0xC96 151133f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_3_0 0xC97 151233f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_CMP_3_1 0xC98 151333f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_0_0 0xC99 151433f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_0_1 0xC9A 151533f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_1_0 0xC9B 151633f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_1_1 0xC9C 151733f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_2_0 0xC9D 151833f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_2_1 0xC9E 151933f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_3_0 0xC9F 152033f810b2SJeff Kirsher #define PI_ESIC_K_IO_ADD_MASK_3_1 0xCA0 152133f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_1 0xCA1 152233f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_2 0xCA2 152333f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_3 0xCA3 152433f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_4 0xCA4 152533f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_5 0xCA5 152633f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_6 0xCA6 152733f810b2SJeff Kirsher #define PI_ESIC_K_MOD_CONFIG_7 0xCA7 152833f810b2SJeff Kirsher #define PI_ESIC_K_DIP_SWITCH 0xCA8 152933f810b2SJeff Kirsher #define PI_ESIC_K_IO_CONFIG_STAT_0 0xCA9 153033f810b2SJeff Kirsher #define PI_ESIC_K_IO_CONFIG_STAT_1 0xCAA 153133f810b2SJeff Kirsher #define PI_ESIC_K_DMA_CONFIG 0xCAB 153233f810b2SJeff Kirsher #define PI_ESIC_K_INPUT_PORT 0xCAC 153333f810b2SJeff Kirsher #define PI_ESIC_K_OUTPUT_PORT 0xCAD 153433f810b2SJeff Kirsher #define PI_ESIC_K_FUNCTION_CNTRL 0xCAE 153533f810b2SJeff Kirsher 153633f810b2SJeff Kirsher /* Define the bits in the function control register. */ 153733f810b2SJeff Kirsher 153833f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_IOCS0 0x01 153933f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_IOCS1 0x02 154033f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_IOCS2 0x04 154133f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_IOCS3 0x08 154233f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_MEMCS0 0x10 154333f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_MEMCS1 0x20 154433f810b2SJeff Kirsher #define PI_FUNCTION_CNTRL_M_DMA 0x80 154533f810b2SJeff Kirsher 154633f810b2SJeff Kirsher /* Define the bits in the slot control register. */ 154733f810b2SJeff Kirsher 154833f810b2SJeff Kirsher #define PI_SLOT_CNTRL_M_RESET 0x04 /* Don't use. */ 154933f810b2SJeff Kirsher #define PI_SLOT_CNTRL_M_ERROR 0x02 /* Not implemented. */ 155033f810b2SJeff Kirsher #define PI_SLOT_CNTRL_M_ENB 0x01 /* Must be set. */ 155133f810b2SJeff Kirsher 155233f810b2SJeff Kirsher /* Define the bits in the burst holdoff register. */ 155333f810b2SJeff Kirsher 155433f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_M_HOLDOFF 0xFC 155533f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_M_RESERVED 0x02 155633f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_M_MEM_MAP 0x01 155733f810b2SJeff Kirsher 155833f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_V_HOLDOFF 2 155933f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_V_RESERVED 1 156033f810b2SJeff Kirsher #define PI_BURST_HOLDOFF_V_MEM_MAP 0 156133f810b2SJeff Kirsher 1562fef85fc4SMaciej W. Rozycki /* Define the implicit mask of the Memory Address Compare registers. */ 156333f810b2SJeff Kirsher 156433f810b2SJeff Kirsher #define PI_MEM_ADD_MASK_M 0x3ff 156533f810b2SJeff Kirsher 1566b98dfaf2SMaciej W. Rozycki /* Define the fields in the I/O Address Compare and Mask registers. */ 1567b98dfaf2SMaciej W. Rozycki 1568b98dfaf2SMaciej W. Rozycki #define PI_IO_CMP_M_SLOT 0xf0 156933f810b2SJeff Kirsher 157033f810b2SJeff Kirsher #define PI_IO_CMP_V_SLOT 4 157133f810b2SJeff Kirsher 157233f810b2SJeff Kirsher /* Define the fields in the Interrupt Channel Configuration and Status reg */ 157333f810b2SJeff Kirsher 157433f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_PEND 0x80 157533f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_RES_1 0x40 157633f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_IREQ_OUT 0x20 157733f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_IREQ_IN 0x10 157833f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_INT_ENB 0x08 157933f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_RES_0 0x04 158033f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_M_IRQ 0x03 158133f810b2SJeff Kirsher 158233f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_PEND 7 158333f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_RES_1 6 158433f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_IREQ_OUT 5 158533f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_IREQ_IN 4 158633f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_INT_ENB 3 158733f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_RES_0 2 158833f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_V_IRQ 0 158933f810b2SJeff Kirsher 159033f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_IRQ_K_9 0 159133f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_IRQ_K_10 1 159233f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_IRQ_K_11 2 159333f810b2SJeff Kirsher #define PI_CONFIG_STAT_0_IRQ_K_15 3 159433f810b2SJeff Kirsher 159533f810b2SJeff Kirsher /* Define DEC FDDIcontroller/EISA (DEFEA) EISA hardware ID's */ 159633f810b2SJeff Kirsher 159733f810b2SJeff Kirsher #define DEFEA_PRODUCT_ID 0x0030A310 /* DEC product 300 (no rev) */ 159833f810b2SJeff Kirsher #define DEFEA_PROD_ID_1 0x0130A310 /* DEC product 300, rev 1 */ 159933f810b2SJeff Kirsher #define DEFEA_PROD_ID_2 0x0230A310 /* DEC product 300, rev 2 */ 160033f810b2SJeff Kirsher #define DEFEA_PROD_ID_3 0x0330A310 /* DEC product 300, rev 3 */ 160133f810b2SJeff Kirsher #define DEFEA_PROD_ID_4 0x0430A310 /* DEC product 300, rev 4 */ 160233f810b2SJeff Kirsher 160333f810b2SJeff Kirsher /**********************************************/ 160433f810b2SJeff Kirsher /* Digital PFI Specification v1.0 Definitions */ 160533f810b2SJeff Kirsher /**********************************************/ 160633f810b2SJeff Kirsher 160733f810b2SJeff Kirsher /* PCI Configuration Space Constants */ 160833f810b2SJeff Kirsher 160933f810b2SJeff Kirsher #define PFI_K_LAT_TIMER_DEF 0x88 /* def max master latency timer */ 161033f810b2SJeff Kirsher #define PFI_K_LAT_TIMER_MIN 0x20 /* min max master latency timer */ 161133f810b2SJeff Kirsher #define PFI_K_CSR_MEM_LEN 0x80 /* 128 bytes */ 161233f810b2SJeff Kirsher #define PFI_K_CSR_IO_LEN 0x80 /* 128 bytes */ 161333f810b2SJeff Kirsher #define PFI_K_PKT_MEM_LEN 0x10000 /* 64K bytes */ 161433f810b2SJeff Kirsher 161533f810b2SJeff Kirsher /* PFI Register Offsets (starting at PDQ Register Base Address) */ 161633f810b2SJeff Kirsher 161733f810b2SJeff Kirsher #define PFI_K_REG_RESERVED_0 0X00000038 161833f810b2SJeff Kirsher #define PFI_K_REG_RESERVED_1 0X0000003C 161933f810b2SJeff Kirsher #define PFI_K_REG_MODE_CTRL 0X00000040 162033f810b2SJeff Kirsher #define PFI_K_REG_STATUS 0X00000044 162133f810b2SJeff Kirsher #define PFI_K_REG_FIFO_WRITE 0X00000048 162233f810b2SJeff Kirsher #define PFI_K_REG_FIFO_READ 0X0000004C 162333f810b2SJeff Kirsher 162433f810b2SJeff Kirsher /* PFI Mode Control Register Constants */ 162533f810b2SJeff Kirsher 162633f810b2SJeff Kirsher #define PFI_MODE_M_RESERVED 0XFFFFFFF0 162733f810b2SJeff Kirsher #define PFI_MODE_M_TGT_ABORT_ENB 0X00000008 162833f810b2SJeff Kirsher #define PFI_MODE_M_PDQ_INT_ENB 0X00000004 162933f810b2SJeff Kirsher #define PFI_MODE_M_PFI_INT_ENB 0X00000002 163033f810b2SJeff Kirsher #define PFI_MODE_M_DMA_ENB 0X00000001 163133f810b2SJeff Kirsher 163233f810b2SJeff Kirsher #define PFI_MODE_V_RESERVED 4 163333f810b2SJeff Kirsher #define PFI_MODE_V_TGT_ABORT_ENB 3 163433f810b2SJeff Kirsher #define PFI_MODE_V_PDQ_INT_ENB 2 163533f810b2SJeff Kirsher #define PFI_MODE_V_PFI_INT_ENB 1 163633f810b2SJeff Kirsher #define PFI_MODE_V_DMA_ENB 0 163733f810b2SJeff Kirsher 163833f810b2SJeff Kirsher #define PFI_MODE_K_ALL_DISABLE 0X00000000 163933f810b2SJeff Kirsher 164033f810b2SJeff Kirsher /* PFI Status Register Constants */ 164133f810b2SJeff Kirsher 164233f810b2SJeff Kirsher #define PFI_STATUS_M_RESERVED 0XFFFFFFC0 164333f810b2SJeff Kirsher #define PFI_STATUS_M_PFI_ERROR 0X00000020 /* only valid in rev 1 or later PFI */ 164433f810b2SJeff Kirsher #define PFI_STATUS_M_PDQ_INT 0X00000010 164533f810b2SJeff Kirsher #define PFI_STATUS_M_PDQ_DMA_ABORT 0X00000008 164633f810b2SJeff Kirsher #define PFI_STATUS_M_FIFO_FULL 0X00000004 164733f810b2SJeff Kirsher #define PFI_STATUS_M_FIFO_EMPTY 0X00000002 164833f810b2SJeff Kirsher #define PFI_STATUS_M_DMA_IN_PROGRESS 0X00000001 164933f810b2SJeff Kirsher 165033f810b2SJeff Kirsher #define PFI_STATUS_V_RESERVED 6 165133f810b2SJeff Kirsher #define PFI_STATUS_V_PFI_ERROR 5 /* only valid in rev 1 or later PFI */ 165233f810b2SJeff Kirsher #define PFI_STATUS_V_PDQ_INT 4 165333f810b2SJeff Kirsher #define PFI_STATUS_V_PDQ_DMA_ABORT 3 165433f810b2SJeff Kirsher #define PFI_STATUS_V_FIFO_FULL 2 165533f810b2SJeff Kirsher #define PFI_STATUS_V_FIFO_EMPTY 1 165633f810b2SJeff Kirsher #define PFI_STATUS_V_DMA_IN_PROGRESS 0 165733f810b2SJeff Kirsher 165833f810b2SJeff Kirsher #define DFX_FC_PRH2_PRH1_PRH0 0x54003820 /* Packet Request Header bytes + FC */ 165933f810b2SJeff Kirsher #define DFX_PRH0_BYTE 0x20 /* Packet Request Header byte 0 */ 166033f810b2SJeff Kirsher #define DFX_PRH1_BYTE 0x38 /* Packet Request Header byte 1 */ 166133f810b2SJeff Kirsher #define DFX_PRH2_BYTE 0x00 /* Packet Request Header byte 2 */ 166233f810b2SJeff Kirsher 166333f810b2SJeff Kirsher /* Driver routine status (return) codes */ 166433f810b2SJeff Kirsher 166533f810b2SJeff Kirsher #define DFX_K_SUCCESS 0 /* routine succeeded */ 166633f810b2SJeff Kirsher #define DFX_K_FAILURE 1 /* routine failed */ 166733f810b2SJeff Kirsher #define DFX_K_OUTSTATE 2 /* bad state for command */ 166833f810b2SJeff Kirsher #define DFX_K_HW_TIMEOUT 3 /* command timed out */ 166933f810b2SJeff Kirsher 167033f810b2SJeff Kirsher /* Define LLC host receive buffer min/max/default values */ 167133f810b2SJeff Kirsher 167233f810b2SJeff Kirsher #define RCV_BUFS_MIN 2 /* minimum pre-allocated receive buffers */ 167333f810b2SJeff Kirsher #define RCV_BUFS_MAX 32 /* maximum pre-allocated receive buffers */ 167433f810b2SJeff Kirsher #define RCV_BUFS_DEF 8 /* default pre-allocated receive buffers */ 167533f810b2SJeff Kirsher 167633f810b2SJeff Kirsher /* Define offsets into FDDI LLC or SMT receive frame buffers - used when indicating frames */ 167733f810b2SJeff Kirsher 167833f810b2SJeff Kirsher #define RCV_BUFF_K_DESCR 0 /* four byte FMC descriptor */ 167933f810b2SJeff Kirsher #define RCV_BUFF_K_PADDING 4 /* three null bytes */ 168033f810b2SJeff Kirsher #define RCV_BUFF_K_FC 7 /* one byte frame control */ 168133f810b2SJeff Kirsher #define RCV_BUFF_K_DA 8 /* six byte destination address */ 168233f810b2SJeff Kirsher #define RCV_BUFF_K_SA 14 /* six byte source address */ 168333f810b2SJeff Kirsher #define RCV_BUFF_K_DATA 20 /* offset to start of packet data */ 168433f810b2SJeff Kirsher 168533f810b2SJeff Kirsher /* Define offsets into FDDI LLC transmit frame buffers - used when sending frames */ 168633f810b2SJeff Kirsher 168733f810b2SJeff Kirsher #define XMT_BUFF_K_FC 0 /* one byte frame control */ 168833f810b2SJeff Kirsher #define XMT_BUFF_K_DA 1 /* six byte destination address */ 168933f810b2SJeff Kirsher #define XMT_BUFF_K_SA 7 /* six byte source address */ 169033f810b2SJeff Kirsher #define XMT_BUFF_K_DATA 13 /* offset to start of packet data */ 169133f810b2SJeff Kirsher 169233f810b2SJeff Kirsher /* Macro for checking a "value" is within a specific range */ 169333f810b2SJeff Kirsher 169433f810b2SJeff Kirsher #define IN_RANGE(value,low,high) ((value >= low) && (value <= high)) 169533f810b2SJeff Kirsher 169633f810b2SJeff Kirsher /* Only execute special print call when debug driver was built */ 169733f810b2SJeff Kirsher 169833f810b2SJeff Kirsher #ifdef DEFXX_DEBUG 169951ba0ed1SMaciej W. Rozycki #define DBG_printk(args...) printk(args) 170033f810b2SJeff Kirsher #else 170133f810b2SJeff Kirsher #define DBG_printk(args...) 170233f810b2SJeff Kirsher #endif 170333f810b2SJeff Kirsher 170433f810b2SJeff Kirsher /* Define constants for masking/unmasking interrupts */ 170533f810b2SJeff Kirsher 170633f810b2SJeff Kirsher #define DFX_MASK_INTERRUPTS 1 170733f810b2SJeff Kirsher #define DFX_UNMASK_INTERRUPTS 0 170833f810b2SJeff Kirsher 170933f810b2SJeff Kirsher /* Define structure for driver transmit descriptor block */ 171033f810b2SJeff Kirsher 171133f810b2SJeff Kirsher typedef struct 171233f810b2SJeff Kirsher { 171333f810b2SJeff Kirsher struct sk_buff *p_skb; /* ptr to skb */ 171433f810b2SJeff Kirsher } XMT_DRIVER_DESCR; 171533f810b2SJeff Kirsher 171633f810b2SJeff Kirsher typedef struct DFX_board_tag 171733f810b2SJeff Kirsher { 171833f810b2SJeff Kirsher /* Keep virtual and physical pointers to locked, physically contiguous memory */ 171933f810b2SJeff Kirsher 172033f810b2SJeff Kirsher char *kmalloced; /* pci_free_consistent this on unload */ 172133f810b2SJeff Kirsher dma_addr_t kmalloced_dma; 172233f810b2SJeff Kirsher /* DMA handle for the above */ 172333f810b2SJeff Kirsher PI_DESCR_BLOCK *descr_block_virt; /* PDQ descriptor block virt address */ 172433f810b2SJeff Kirsher dma_addr_t descr_block_phys; /* PDQ descriptor block phys address */ 172533f810b2SJeff Kirsher PI_DMA_CMD_REQ *cmd_req_virt; /* Command request buffer virt address */ 172633f810b2SJeff Kirsher dma_addr_t cmd_req_phys; /* Command request buffer phys address */ 172733f810b2SJeff Kirsher PI_DMA_CMD_RSP *cmd_rsp_virt; /* Command response buffer virt address */ 172833f810b2SJeff Kirsher dma_addr_t cmd_rsp_phys; /* Command response buffer phys address */ 172933f810b2SJeff Kirsher char *rcv_block_virt; /* LLC host receive queue buf blk virt */ 173033f810b2SJeff Kirsher dma_addr_t rcv_block_phys; /* LLC host receive queue buf blk phys */ 173133f810b2SJeff Kirsher PI_CONSUMER_BLOCK *cons_block_virt; /* PDQ consumer block virt address */ 173233f810b2SJeff Kirsher dma_addr_t cons_block_phys; /* PDQ consumer block phys address */ 173333f810b2SJeff Kirsher 173433f810b2SJeff Kirsher /* Keep local copies of Type 1 and Type 2 register data */ 173533f810b2SJeff Kirsher 173633f810b2SJeff Kirsher PI_TYPE_1_PROD_REG cmd_req_reg; /* Command Request register */ 173733f810b2SJeff Kirsher PI_TYPE_1_PROD_REG cmd_rsp_reg; /* Command Response register */ 173833f810b2SJeff Kirsher PI_TYPE_2_PROD_REG rcv_xmt_reg; /* Type 2 (RCV/XMT) register */ 173933f810b2SJeff Kirsher 174033f810b2SJeff Kirsher /* Storage for unicast and multicast address entries in adapter CAM */ 174133f810b2SJeff Kirsher 174233f810b2SJeff Kirsher u8 uc_table[1*FDDI_K_ALEN]; 174333f810b2SJeff Kirsher u32 uc_count; /* number of unicast addresses */ 174433f810b2SJeff Kirsher u8 mc_table[PI_CMD_ADDR_FILTER_K_SIZE*FDDI_K_ALEN]; 174533f810b2SJeff Kirsher u32 mc_count; /* number of multicast addresses */ 174633f810b2SJeff Kirsher 174733f810b2SJeff Kirsher /* Current packet filter settings */ 174833f810b2SJeff Kirsher 174933f810b2SJeff Kirsher u32 ind_group_prom; /* LLC individual & group frame prom mode */ 175033f810b2SJeff Kirsher u32 group_prom; /* LLC group (multicast) frame prom mode */ 175133f810b2SJeff Kirsher 175233f810b2SJeff Kirsher /* Link available flag needed to determine whether to drop outgoing packet requests */ 175333f810b2SJeff Kirsher 175433f810b2SJeff Kirsher u32 link_available; /* is link available? */ 175533f810b2SJeff Kirsher 175633f810b2SJeff Kirsher /* Resources to indicate reset type when resetting adapter */ 175733f810b2SJeff Kirsher 175833f810b2SJeff Kirsher u32 reset_type; /* skip or rerun diagnostics */ 175933f810b2SJeff Kirsher 176033f810b2SJeff Kirsher /* Store pointers to receive buffers for queue processing code */ 176133f810b2SJeff Kirsher 176233f810b2SJeff Kirsher char *p_rcv_buff_va[PI_RCV_DATA_K_NUM_ENTRIES]; 176333f810b2SJeff Kirsher 176433f810b2SJeff Kirsher /* Store pointers to transmit buffers for transmit completion code */ 176533f810b2SJeff Kirsher 176633f810b2SJeff Kirsher XMT_DRIVER_DESCR xmt_drv_descr_blk[PI_XMT_DATA_K_NUM_ENTRIES]; 176733f810b2SJeff Kirsher 176833f810b2SJeff Kirsher /* Transmit spinlocks */ 176933f810b2SJeff Kirsher 177033f810b2SJeff Kirsher spinlock_t lock; 177133f810b2SJeff Kirsher 177233f810b2SJeff Kirsher /* Store device, bus-specific, and parameter information for this adapter */ 177333f810b2SJeff Kirsher 177433f810b2SJeff Kirsher struct net_device *dev; /* pointer to device structure */ 177533f810b2SJeff Kirsher union { 177633f810b2SJeff Kirsher void __iomem *mem; 177733f810b2SJeff Kirsher int port; 177833f810b2SJeff Kirsher } base; /* base address */ 177933f810b2SJeff Kirsher struct device *bus_dev; 1780*795e272eSMaciej W. Rozycki /* Whether to use MMIO or port I/O. */ 1781*795e272eSMaciej W. Rozycki bool mmio; 178233f810b2SJeff Kirsher u32 full_duplex_enb; /* FDDI Full Duplex enable (1 == on, 2 == off) */ 178333f810b2SJeff Kirsher u32 req_ttrt; /* requested TTRT value (in 80ns units) */ 178433f810b2SJeff Kirsher u32 burst_size; /* adapter burst size (enumerated) */ 178533f810b2SJeff Kirsher u32 rcv_bufs_to_post; /* receive buffers to post for LLC host queue */ 178633f810b2SJeff Kirsher u8 factory_mac_addr[FDDI_K_ALEN]; /* factory (on-board) MAC address */ 178733f810b2SJeff Kirsher 178833f810b2SJeff Kirsher /* Common FDDI statistics structure and private counters */ 178933f810b2SJeff Kirsher 179033f810b2SJeff Kirsher struct fddi_statistics stats; 179133f810b2SJeff Kirsher 179233f810b2SJeff Kirsher u32 rcv_discards; 179333f810b2SJeff Kirsher u32 rcv_crc_errors; 179433f810b2SJeff Kirsher u32 rcv_frame_status_errors; 179533f810b2SJeff Kirsher u32 rcv_length_errors; 179633f810b2SJeff Kirsher u32 rcv_total_frames; 179733f810b2SJeff Kirsher u32 rcv_multicast_frames; 179833f810b2SJeff Kirsher u32 rcv_total_bytes; 179933f810b2SJeff Kirsher 180033f810b2SJeff Kirsher u32 xmt_discards; 180133f810b2SJeff Kirsher u32 xmt_length_errors; 180233f810b2SJeff Kirsher u32 xmt_total_frames; 180333f810b2SJeff Kirsher u32 xmt_total_bytes; 180433f810b2SJeff Kirsher } DFX_board_t; 180533f810b2SJeff Kirsher 180633f810b2SJeff Kirsher #endif /* #ifndef _DEFXX_H_ */ 1807