1 /* 2 * File Name: 3 * defxx.c 4 * 5 * Copyright Information: 6 * Copyright Digital Equipment Corporation 1996. 7 * 8 * This software may be used and distributed according to the terms of 9 * the GNU General Public License, incorporated herein by reference. 10 * 11 * Abstract: 12 * A Linux device driver supporting the Digital Equipment Corporation 13 * FDDI TURBOchannel, EISA and PCI controller families. Supported 14 * adapters include: 15 * 16 * DEC FDDIcontroller/TURBOchannel (DEFTA) 17 * DEC FDDIcontroller/EISA (DEFEA) 18 * DEC FDDIcontroller/PCI (DEFPA) 19 * 20 * The original author: 21 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 22 * 23 * Maintainers: 24 * macro Maciej W. Rozycki <macro@linux-mips.org> 25 * 26 * Credits: 27 * I'd like to thank Patricia Cross for helping me get started with 28 * Linux, David Davies for a lot of help upgrading and configuring 29 * my development system and for answering many OS and driver 30 * development questions, and Alan Cox for recommendations and 31 * integration help on getting FDDI support into Linux. LVS 32 * 33 * Driver Architecture: 34 * The driver architecture is largely based on previous driver work 35 * for other operating systems. The upper edge interface and 36 * functions were largely taken from existing Linux device drivers 37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 38 * driver. 39 * 40 * Adapter Probe - 41 * The driver scans for supported EISA adapters by reading the 42 * SLOT ID register for each EISA slot and making a match 43 * against the expected value. 44 * 45 * Bus-Specific Initialization - 46 * This driver currently supports both EISA and PCI controller 47 * families. While the custom DMA chip and FDDI logic is similar 48 * or identical, the bus logic is very different. After 49 * initialization, the only bus-specific differences is in how the 50 * driver enables and disables interrupts. Other than that, the 51 * run-time critical code behaves the same on both families. 52 * It's important to note that both adapter families are configured 53 * to I/O map, rather than memory map, the adapter registers. 54 * 55 * Driver Open/Close - 56 * In the driver open routine, the driver ISR (interrupt service 57 * routine) is registered and the adapter is brought to an 58 * operational state. In the driver close routine, the opposite 59 * occurs; the driver ISR is deregistered and the adapter is 60 * brought to a safe, but closed state. Users may use consecutive 61 * commands to bring the adapter up and down as in the following 62 * example: 63 * ifconfig fddi0 up 64 * ifconfig fddi0 down 65 * ifconfig fddi0 up 66 * 67 * Driver Shutdown - 68 * Apparently, there is no shutdown or halt routine support under 69 * Linux. This routine would be called during "reboot" or 70 * "shutdown" to allow the driver to place the adapter in a safe 71 * state before a warm reboot occurs. To be really safe, the user 72 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 73 * to ensure that the adapter DMA engine is taken off-line. However, 74 * the current driver code anticipates this problem and always issues 75 * a soft reset of the adapter at the beginning of driver initialization. 76 * A future driver enhancement in this area may occur in 2.1.X where 77 * Alan indicated that a shutdown handler may be implemented. 78 * 79 * Interrupt Service Routine - 80 * The driver supports shared interrupts, so the ISR is registered for 81 * each board with the appropriate flag and the pointer to that board's 82 * device structure. This provides the context during interrupt 83 * processing to support shared interrupts and multiple boards. 84 * 85 * Interrupt enabling/disabling can occur at many levels. At the host 86 * end, you can disable system interrupts, or disable interrupts at the 87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 88 * have a bus-logic chip interrupt enable/disable as well as a DMA 89 * controller interrupt enable/disable. 90 * 91 * The driver currently enables and disables adapter interrupts at the 92 * bus-logic chip and assumes that Linux will take care of clearing or 93 * acknowledging any host-based interrupt chips. 94 * 95 * Control Functions - 96 * Control functions are those used to support functions such as adding 97 * or deleting multicast addresses, enabling or disabling packet 98 * reception filters, or other custom/proprietary commands. Presently, 99 * the driver supports the "get statistics", "set multicast list", and 100 * "set mac address" functions defined by Linux. A list of possible 101 * enhancements include: 102 * 103 * - Custom ioctl interface for executing port interface commands 104 * - Custom ioctl interface for adding unicast addresses to 105 * adapter CAM (to support bridge functions). 106 * - Custom ioctl interface for supporting firmware upgrades. 107 * 108 * Hardware (port interface) Support Routines - 109 * The driver function names that start with "dfx_hw_" represent 110 * low-level port interface routines that are called frequently. They 111 * include issuing a DMA or port control command to the adapter, 112 * resetting the adapter, or reading the adapter state. Since the 113 * driver initialization and run-time code must make calls into the 114 * port interface, these routines were written to be as generic and 115 * usable as possible. 116 * 117 * Receive Path - 118 * The adapter DMA engine supports a 256 entry receive descriptor block 119 * of which up to 255 entries can be used at any given time. The 120 * architecture is a standard producer, consumer, completion model in 121 * which the driver "produces" receive buffers to the adapter, the 122 * adapter "consumes" the receive buffers by DMAing incoming packet data, 123 * and the driver "completes" the receive buffers by servicing the 124 * incoming packet, then "produces" a new buffer and starts the cycle 125 * again. Receive buffers can be fragmented in up to 16 fragments 126 * (descriptor entries). For simplicity, this driver posts 127 * single-fragment receive buffers of 4608 bytes, then allocates a 128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 129 * utilization, a better approach would be to pass up the receive 130 * buffer (no extra copy) then allocate and post a replacement buffer. 131 * This is a performance enhancement that should be looked into at 132 * some point. 133 * 134 * Transmit Path - 135 * Like the receive path, the adapter DMA engine supports a 256 entry 136 * transmit descriptor block of which up to 255 entries can be used at 137 * any given time. Transmit buffers can be fragmented in up to 255 138 * fragments (descriptor entries). This driver always posts one 139 * fragment per transmit packet request. 140 * 141 * The fragment contains the entire packet from FC to end of data. 142 * Before posting the buffer to the adapter, the driver sets a three-byte 143 * packet request header (PRH) which is required by the Motorola MAC chip 144 * used on the adapters. The PRH tells the MAC the type of token to 145 * receive/send, whether or not to generate and append the CRC, whether 146 * synchronous or asynchronous framing is used, etc. Since the PRH 147 * definition is not necessarily consistent across all FDDI chipsets, 148 * the driver, rather than the common FDDI packet handler routines, 149 * sets these bytes. 150 * 151 * To reduce the amount of descriptor fetches needed per transmit request, 152 * the driver takes advantage of the fact that there are at least three 153 * bytes available before the skb->data field on the outgoing transmit 154 * request. This is guaranteed by having fddi_setup() in net_init.c set 155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 157 * bytes which we'll use to store the PRH. 158 * 159 * There's a subtle advantage to adding these pad bytes to the 160 * hard_header_len, it ensures that the data portion of the packet for 161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 162 * implementations may not need the extra padding and can start copying 163 * or DMAing directly from the FC byte which starts at skb->data. Should 164 * another driver implementation need ADDITIONAL padding, the net_init.c 165 * module should be updated and dev->hard_header_len should be increased. 166 * NOTE: To maintain the alignment on the data portion of the packet, 167 * dev->hard_header_len should always be evenly divisible by 4 and at 168 * least 24 bytes in size. 169 * 170 * Modification History: 171 * Date Name Description 172 * 16-Aug-96 LVS Created. 173 * 20-Aug-96 LVS Updated dfx_probe so that version information 174 * string is only displayed if 1 or more cards are 175 * found. Changed dfx_rcv_queue_process to copy 176 * 3 NULL bytes before FC to ensure that data is 177 * longword aligned in receive buffer. 178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 179 * LLC group promiscuous mode if multicast list 180 * is too large. LLC individual/group promiscuous 181 * mode is now disabled if IFF_PROMISC flag not set. 182 * dfx_xmt_queue_pkt no longer checks for NULL skb 183 * on Alan Cox recommendation. Added node address 184 * override support. 185 * 12-Sep-96 LVS Reset current address to factory address during 186 * device open. Updated transmit path to post a 187 * single fragment which includes PRH->end of data. 188 * Mar 2000 AC Did various cleanups for 2.3.x 189 * Jun 2000 jgarzik PCI and resource alloc cleanups 190 * Jul 2000 tjeerd Much cleanup and some bug fixes 191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 192 * Feb 2001 Skb allocation fixes 193 * Feb 2001 davej PCI enable cleanups. 194 * 04 Aug 2003 macro Converted to the DMA API. 195 * 14 Aug 2004 macro Fix device names reported. 196 * 14 Jun 2005 macro Use irqreturn_t. 197 * 23 Oct 2006 macro Big-endian host support. 198 * 14 Dec 2006 macro TURBOchannel support. 199 */ 200 201 /* Include files */ 202 #include <linux/bitops.h> 203 #include <linux/compiler.h> 204 #include <linux/delay.h> 205 #include <linux/dma-mapping.h> 206 #include <linux/eisa.h> 207 #include <linux/errno.h> 208 #include <linux/fddidevice.h> 209 #include <linux/interrupt.h> 210 #include <linux/ioport.h> 211 #include <linux/kernel.h> 212 #include <linux/module.h> 213 #include <linux/netdevice.h> 214 #include <linux/pci.h> 215 #include <linux/skbuff.h> 216 #include <linux/slab.h> 217 #include <linux/string.h> 218 #include <linux/tc.h> 219 220 #include <asm/byteorder.h> 221 #include <asm/io.h> 222 223 #include "defxx.h" 224 225 /* Version information string should be updated prior to each new release! */ 226 #define DRV_NAME "defxx" 227 #define DRV_VERSION "v1.10" 228 #define DRV_RELDATE "2006/12/14" 229 230 static char version[] = 231 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 232 " Lawrence V. Stefani and others\n"; 233 234 #define DYNAMIC_BUFFERS 1 235 236 #define SKBUFF_RX_COPYBREAK 200 237 /* 238 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 239 * alignment for compatibility with old EISA boards. 240 */ 241 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 242 243 #ifdef CONFIG_EISA 244 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) 245 #else 246 #define DFX_BUS_EISA(dev) 0 247 #endif 248 249 #ifdef CONFIG_TC 250 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) 251 #else 252 #define DFX_BUS_TC(dev) 0 253 #endif 254 255 #ifdef CONFIG_DEFXX_MMIO 256 #define DFX_MMIO 1 257 #else 258 #define DFX_MMIO 0 259 #endif 260 261 /* Define module-wide (static) routines */ 262 263 static void dfx_bus_init(struct net_device *dev); 264 static void dfx_bus_uninit(struct net_device *dev); 265 static void dfx_bus_config_check(DFX_board_t *bp); 266 267 static int dfx_driver_init(struct net_device *dev, 268 const char *print_name, 269 resource_size_t bar_start); 270 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 271 272 static int dfx_open(struct net_device *dev); 273 static int dfx_close(struct net_device *dev); 274 275 static void dfx_int_pr_halt_id(DFX_board_t *bp); 276 static void dfx_int_type_0_process(DFX_board_t *bp); 277 static void dfx_int_common(struct net_device *dev); 278 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 279 280 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 281 static void dfx_ctl_set_multicast_list(struct net_device *dev); 282 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 283 static int dfx_ctl_update_cam(DFX_board_t *bp); 284 static int dfx_ctl_update_filters(DFX_board_t *bp); 285 286 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 287 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 288 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 289 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 290 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 291 292 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 293 static void dfx_rcv_queue_process(DFX_board_t *bp); 294 #ifdef DYNAMIC_BUFFERS 295 static void dfx_rcv_flush(DFX_board_t *bp); 296 #else 297 static inline void dfx_rcv_flush(DFX_board_t *bp) {} 298 #endif 299 300 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 301 struct net_device *dev); 302 static int dfx_xmt_done(DFX_board_t *bp); 303 static void dfx_xmt_flush(DFX_board_t *bp); 304 305 /* Define module-wide (static) variables */ 306 307 static struct pci_driver dfx_pci_driver; 308 static struct eisa_driver dfx_eisa_driver; 309 static struct tc_driver dfx_tc_driver; 310 311 312 /* 313 * ======================= 314 * = dfx_port_write_long = 315 * = dfx_port_read_long = 316 * ======================= 317 * 318 * Overview: 319 * Routines for reading and writing values from/to adapter 320 * 321 * Returns: 322 * None 323 * 324 * Arguments: 325 * bp - pointer to board information 326 * offset - register offset from base I/O address 327 * data - for dfx_port_write_long, this is a value to write; 328 * for dfx_port_read_long, this is a pointer to store 329 * the read value 330 * 331 * Functional Description: 332 * These routines perform the correct operation to read or write 333 * the adapter register. 334 * 335 * EISA port block base addresses are based on the slot number in which the 336 * controller is installed. For example, if the EISA controller is installed 337 * in slot 4, the port block base address is 0x4000. If the controller is 338 * installed in slot 2, the port block base address is 0x2000, and so on. 339 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 340 * registers using the register offsets defined in DEFXX.H. 341 * 342 * PCI port block base addresses are assigned by the PCI BIOS or system 343 * firmware. There is one 128 byte port block which can be accessed. It 344 * allows for I/O mapping of both PDQ and PFI registers using the register 345 * offsets defined in DEFXX.H. 346 * 347 * Return Codes: 348 * None 349 * 350 * Assumptions: 351 * bp->base is a valid base I/O address for this adapter. 352 * offset is a valid register offset for this adapter. 353 * 354 * Side Effects: 355 * Rather than produce macros for these functions, these routines 356 * are defined using "inline" to ensure that the compiler will 357 * generate inline code and not waste a procedure call and return. 358 * This provides all the benefits of macros, but with the 359 * advantage of strict data type checking. 360 */ 361 362 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) 363 { 364 writel(data, bp->base.mem + offset); 365 mb(); 366 } 367 368 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) 369 { 370 outl(data, bp->base.port + offset); 371 } 372 373 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) 374 { 375 struct device __maybe_unused *bdev = bp->bus_dev; 376 int dfx_bus_tc = DFX_BUS_TC(bdev); 377 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 378 379 if (dfx_use_mmio) 380 dfx_writel(bp, offset, data); 381 else 382 dfx_outl(bp, offset, data); 383 } 384 385 386 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) 387 { 388 mb(); 389 *data = readl(bp->base.mem + offset); 390 } 391 392 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) 393 { 394 *data = inl(bp->base.port + offset); 395 } 396 397 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) 398 { 399 struct device __maybe_unused *bdev = bp->bus_dev; 400 int dfx_bus_tc = DFX_BUS_TC(bdev); 401 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 402 403 if (dfx_use_mmio) 404 dfx_readl(bp, offset, data); 405 else 406 dfx_inl(bp, offset, data); 407 } 408 409 410 /* 411 * ================ 412 * = dfx_get_bars = 413 * ================ 414 * 415 * Overview: 416 * Retrieves the address range used to access control and status 417 * registers. 418 * 419 * Returns: 420 * None 421 * 422 * Arguments: 423 * bdev - pointer to device information 424 * bar_start - pointer to store the start address 425 * bar_len - pointer to store the length of the area 426 * 427 * Assumptions: 428 * I am sure there are some. 429 * 430 * Side Effects: 431 * None 432 */ 433 static void dfx_get_bars(struct device *bdev, 434 resource_size_t *bar_start, resource_size_t *bar_len) 435 { 436 int dfx_bus_pci = dev_is_pci(bdev); 437 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 438 int dfx_bus_tc = DFX_BUS_TC(bdev); 439 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 440 441 if (dfx_bus_pci) { 442 int num = dfx_use_mmio ? 0 : 1; 443 444 *bar_start = pci_resource_start(to_pci_dev(bdev), num); 445 *bar_len = pci_resource_len(to_pci_dev(bdev), num); 446 } 447 if (dfx_bus_eisa) { 448 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 449 resource_size_t bar; 450 451 if (dfx_use_mmio) { 452 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2); 453 bar <<= 8; 454 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1); 455 bar <<= 8; 456 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0); 457 bar <<= 16; 458 *bar_start = bar; 459 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2); 460 bar <<= 8; 461 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1); 462 bar <<= 8; 463 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0); 464 bar <<= 16; 465 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; 466 } else { 467 *bar_start = base_addr; 468 *bar_len = PI_ESIC_K_CSR_IO_LEN; 469 } 470 } 471 if (dfx_bus_tc) { 472 *bar_start = to_tc_dev(bdev)->resource.start + 473 PI_TC_K_CSR_OFFSET; 474 *bar_len = PI_TC_K_CSR_LEN; 475 } 476 } 477 478 static const struct net_device_ops dfx_netdev_ops = { 479 .ndo_open = dfx_open, 480 .ndo_stop = dfx_close, 481 .ndo_start_xmit = dfx_xmt_queue_pkt, 482 .ndo_get_stats = dfx_ctl_get_stats, 483 .ndo_set_rx_mode = dfx_ctl_set_multicast_list, 484 .ndo_set_mac_address = dfx_ctl_set_mac_address, 485 }; 486 487 /* 488 * ================ 489 * = dfx_register = 490 * ================ 491 * 492 * Overview: 493 * Initializes a supported FDDI controller 494 * 495 * Returns: 496 * Condition code 497 * 498 * Arguments: 499 * bdev - pointer to device information 500 * 501 * Functional Description: 502 * 503 * Return Codes: 504 * 0 - This device (fddi0, fddi1, etc) configured successfully 505 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 506 * 507 * Assumptions: 508 * It compiles so it should work :-( (PCI cards do :-) 509 * 510 * Side Effects: 511 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 512 * initialized and the board resources are read and stored in 513 * the device structure. 514 */ 515 static int dfx_register(struct device *bdev) 516 { 517 static int version_disp; 518 int dfx_bus_pci = dev_is_pci(bdev); 519 int dfx_bus_tc = DFX_BUS_TC(bdev); 520 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 521 const char *print_name = dev_name(bdev); 522 struct net_device *dev; 523 DFX_board_t *bp; /* board pointer */ 524 resource_size_t bar_start = 0; /* pointer to port */ 525 resource_size_t bar_len = 0; /* resource length */ 526 int alloc_size; /* total buffer size used */ 527 struct resource *region; 528 int err = 0; 529 530 if (!version_disp) { /* display version info if adapter is found */ 531 version_disp = 1; /* set display flag to TRUE so that */ 532 printk(version); /* we only display this string ONCE */ 533 } 534 535 dev = alloc_fddidev(sizeof(*bp)); 536 if (!dev) { 537 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", 538 print_name); 539 return -ENOMEM; 540 } 541 542 /* Enable PCI device. */ 543 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) { 544 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n", 545 print_name); 546 goto err_out; 547 } 548 549 SET_NETDEV_DEV(dev, bdev); 550 551 bp = netdev_priv(dev); 552 bp->bus_dev = bdev; 553 dev_set_drvdata(bdev, dev); 554 555 dfx_get_bars(bdev, &bar_start, &bar_len); 556 557 if (dfx_use_mmio) 558 region = request_mem_region(bar_start, bar_len, print_name); 559 else 560 region = request_region(bar_start, bar_len, print_name); 561 if (!region) { 562 printk(KERN_ERR "%s: Cannot reserve I/O resource " 563 "0x%lx @ 0x%lx, aborting\n", 564 print_name, (long)bar_len, (long)bar_start); 565 err = -EBUSY; 566 goto err_out_disable; 567 } 568 569 /* Set up I/O base address. */ 570 if (dfx_use_mmio) { 571 bp->base.mem = ioremap_nocache(bar_start, bar_len); 572 if (!bp->base.mem) { 573 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); 574 err = -ENOMEM; 575 goto err_out_region; 576 } 577 } else { 578 bp->base.port = bar_start; 579 dev->base_addr = bar_start; 580 } 581 582 /* Initialize new device structure */ 583 dev->netdev_ops = &dfx_netdev_ops; 584 585 if (dfx_bus_pci) 586 pci_set_master(to_pci_dev(bdev)); 587 588 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { 589 err = -ENODEV; 590 goto err_out_unmap; 591 } 592 593 err = register_netdev(dev); 594 if (err) 595 goto err_out_kfree; 596 597 printk("%s: registered as %s\n", print_name, dev->name); 598 return 0; 599 600 err_out_kfree: 601 alloc_size = sizeof(PI_DESCR_BLOCK) + 602 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 603 #ifndef DYNAMIC_BUFFERS 604 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 605 #endif 606 sizeof(PI_CONSUMER_BLOCK) + 607 (PI_ALIGN_K_DESC_BLK - 1); 608 if (bp->kmalloced) 609 dma_free_coherent(bdev, alloc_size, 610 bp->kmalloced, bp->kmalloced_dma); 611 612 err_out_unmap: 613 if (dfx_use_mmio) 614 iounmap(bp->base.mem); 615 616 err_out_region: 617 if (dfx_use_mmio) 618 release_mem_region(bar_start, bar_len); 619 else 620 release_region(bar_start, bar_len); 621 622 err_out_disable: 623 if (dfx_bus_pci) 624 pci_disable_device(to_pci_dev(bdev)); 625 626 err_out: 627 free_netdev(dev); 628 return err; 629 } 630 631 632 /* 633 * ================ 634 * = dfx_bus_init = 635 * ================ 636 * 637 * Overview: 638 * Initializes the bus-specific controller logic. 639 * 640 * Returns: 641 * None 642 * 643 * Arguments: 644 * dev - pointer to device information 645 * 646 * Functional Description: 647 * Determine and save adapter IRQ in device table, 648 * then perform bus-specific logic initialization. 649 * 650 * Return Codes: 651 * None 652 * 653 * Assumptions: 654 * bp->base has already been set with the proper 655 * base I/O address for this device. 656 * 657 * Side Effects: 658 * Interrupts are enabled at the adapter bus-specific logic. 659 * Note: Interrupts at the DMA engine (PDQ chip) are not 660 * enabled yet. 661 */ 662 663 static void dfx_bus_init(struct net_device *dev) 664 { 665 DFX_board_t *bp = netdev_priv(dev); 666 struct device *bdev = bp->bus_dev; 667 int dfx_bus_pci = dev_is_pci(bdev); 668 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 669 int dfx_bus_tc = DFX_BUS_TC(bdev); 670 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 671 u8 val; 672 673 DBG_printk("In dfx_bus_init...\n"); 674 675 /* Initialize a pointer back to the net_device struct */ 676 bp->dev = dev; 677 678 /* Initialize adapter based on bus type */ 679 680 if (dfx_bus_tc) 681 dev->irq = to_tc_dev(bdev)->interrupt; 682 if (dfx_bus_eisa) { 683 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 684 685 /* Get the interrupt level from the ESIC chip. */ 686 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 687 val &= PI_CONFIG_STAT_0_M_IRQ; 688 val >>= PI_CONFIG_STAT_0_V_IRQ; 689 690 switch (val) { 691 case PI_CONFIG_STAT_0_IRQ_K_9: 692 dev->irq = 9; 693 break; 694 695 case PI_CONFIG_STAT_0_IRQ_K_10: 696 dev->irq = 10; 697 break; 698 699 case PI_CONFIG_STAT_0_IRQ_K_11: 700 dev->irq = 11; 701 break; 702 703 case PI_CONFIG_STAT_0_IRQ_K_15: 704 dev->irq = 15; 705 break; 706 } 707 708 /* 709 * Enable memory decoding (MEMCS0) and/or port decoding 710 * (IOCS1/IOCS0) as appropriate in Function Control 711 * Register. One of the port chip selects seems to be 712 * used for the Burst Holdoff register, but this bit of 713 * documentation is missing and as yet it has not been 714 * determined which of the two. This is also the reason 715 * the size of the decoded port range is twice as large 716 * as one required by the PDQ. 717 */ 718 719 /* Set the decode range of the board. */ 720 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); 721 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val); 722 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0); 723 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val); 724 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0); 725 val = PI_ESIC_K_CSR_IO_LEN - 1; 726 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff); 727 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff); 728 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff); 729 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff); 730 731 /* Enable the decoders. */ 732 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; 733 if (dfx_use_mmio) 734 val |= PI_FUNCTION_CNTRL_M_MEMCS0; 735 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val); 736 737 /* 738 * Enable access to the rest of the module 739 * (including PDQ and packet memory). 740 */ 741 val = PI_SLOT_CNTRL_M_ENB; 742 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val); 743 744 /* 745 * Map PDQ registers into memory or port space. This is 746 * done with a bit in the Burst Holdoff register. 747 */ 748 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); 749 if (dfx_use_mmio) 750 val |= PI_BURST_HOLDOFF_V_MEM_MAP; 751 else 752 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; 753 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val); 754 755 /* Enable interrupts at EISA bus interface chip (ESIC) */ 756 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 757 val |= PI_CONFIG_STAT_0_M_INT_ENB; 758 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 759 } 760 if (dfx_bus_pci) { 761 struct pci_dev *pdev = to_pci_dev(bdev); 762 763 /* Get the interrupt level from the PCI Configuration Table */ 764 765 dev->irq = pdev->irq; 766 767 /* Check Latency Timer and set if less than minimal */ 768 769 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 770 if (val < PFI_K_LAT_TIMER_MIN) { 771 val = PFI_K_LAT_TIMER_DEF; 772 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 773 } 774 775 /* Enable interrupts at PCI bus interface chip (PFI) */ 776 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; 777 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); 778 } 779 } 780 781 /* 782 * ================== 783 * = dfx_bus_uninit = 784 * ================== 785 * 786 * Overview: 787 * Uninitializes the bus-specific controller logic. 788 * 789 * Returns: 790 * None 791 * 792 * Arguments: 793 * dev - pointer to device information 794 * 795 * Functional Description: 796 * Perform bus-specific logic uninitialization. 797 * 798 * Return Codes: 799 * None 800 * 801 * Assumptions: 802 * bp->base has already been set with the proper 803 * base I/O address for this device. 804 * 805 * Side Effects: 806 * Interrupts are disabled at the adapter bus-specific logic. 807 */ 808 809 static void dfx_bus_uninit(struct net_device *dev) 810 { 811 DFX_board_t *bp = netdev_priv(dev); 812 struct device *bdev = bp->bus_dev; 813 int dfx_bus_pci = dev_is_pci(bdev); 814 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 815 u8 val; 816 817 DBG_printk("In dfx_bus_uninit...\n"); 818 819 /* Uninitialize adapter based on bus type */ 820 821 if (dfx_bus_eisa) { 822 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 823 824 /* Disable interrupts at EISA bus interface chip (ESIC) */ 825 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 826 val &= ~PI_CONFIG_STAT_0_M_INT_ENB; 827 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 828 } 829 if (dfx_bus_pci) { 830 /* Disable interrupts at PCI bus interface chip (PFI) */ 831 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); 832 } 833 } 834 835 836 /* 837 * ======================== 838 * = dfx_bus_config_check = 839 * ======================== 840 * 841 * Overview: 842 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 843 * are illegal, then this routine will set new defaults. 844 * 845 * Returns: 846 * None 847 * 848 * Arguments: 849 * bp - pointer to board information 850 * 851 * Functional Description: 852 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 853 * PDQ, and all FDDI PCI controllers, all values are legal. 854 * 855 * Return Codes: 856 * None 857 * 858 * Assumptions: 859 * dfx_adap_init has NOT been called yet so burst size and other items have 860 * not been set. 861 * 862 * Side Effects: 863 * None 864 */ 865 866 static void dfx_bus_config_check(DFX_board_t *bp) 867 { 868 struct device __maybe_unused *bdev = bp->bus_dev; 869 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 870 int status; /* return code from adapter port control call */ 871 u32 host_data; /* LW data returned from port control call */ 872 873 DBG_printk("In dfx_bus_config_check...\n"); 874 875 /* Configuration check only valid for EISA adapter */ 876 877 if (dfx_bus_eisa) { 878 /* 879 * First check if revision 2 EISA controller. Rev. 1 cards used 880 * PDQ revision B, so no workaround needed in this case. Rev. 3 881 * cards used PDQ revision E, so no workaround needed in this 882 * case, either. Only Rev. 2 cards used either Rev. D or E 883 * chips, so we must verify the chip revision on Rev. 2 cards. 884 */ 885 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { 886 /* 887 * Revision 2 FDDI EISA controller found, 888 * so let's check PDQ revision of adapter. 889 */ 890 status = dfx_hw_port_ctrl_req(bp, 891 PI_PCTRL_M_SUB_CMD, 892 PI_SUB_CMD_K_PDQ_REV_GET, 893 0, 894 &host_data); 895 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 896 { 897 /* 898 * Either we couldn't determine the PDQ revision, or 899 * we determined that it is at revision D. In either case, 900 * we need to implement the workaround. 901 */ 902 903 /* Ensure that the burst size is set to 8 longwords or less */ 904 905 switch (bp->burst_size) 906 { 907 case PI_PDATA_B_DMA_BURST_SIZE_32: 908 case PI_PDATA_B_DMA_BURST_SIZE_16: 909 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 910 break; 911 912 default: 913 break; 914 } 915 916 /* Ensure that full-duplex mode is not enabled */ 917 918 bp->full_duplex_enb = PI_SNMP_K_FALSE; 919 } 920 } 921 } 922 } 923 924 925 /* 926 * =================== 927 * = dfx_driver_init = 928 * =================== 929 * 930 * Overview: 931 * Initializes remaining adapter board structure information 932 * and makes sure adapter is in a safe state prior to dfx_open(). 933 * 934 * Returns: 935 * Condition code 936 * 937 * Arguments: 938 * dev - pointer to device information 939 * print_name - printable device name 940 * 941 * Functional Description: 942 * This function allocates additional resources such as the host memory 943 * blocks needed by the adapter (eg. descriptor and consumer blocks). 944 * Remaining bus initialization steps are also completed. The adapter 945 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 946 * must call dfx_open() to open the adapter and bring it on-line. 947 * 948 * Return Codes: 949 * DFX_K_SUCCESS - initialization succeeded 950 * DFX_K_FAILURE - initialization failed - could not allocate memory 951 * or read adapter MAC address 952 * 953 * Assumptions: 954 * Memory allocated from pci_alloc_consistent() call is physically 955 * contiguous, locked memory. 956 * 957 * Side Effects: 958 * Adapter is reset and should be in DMA_UNAVAILABLE state before 959 * returning from this routine. 960 */ 961 962 static int dfx_driver_init(struct net_device *dev, const char *print_name, 963 resource_size_t bar_start) 964 { 965 DFX_board_t *bp = netdev_priv(dev); 966 struct device *bdev = bp->bus_dev; 967 int dfx_bus_pci = dev_is_pci(bdev); 968 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 969 int dfx_bus_tc = DFX_BUS_TC(bdev); 970 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 971 int alloc_size; /* total buffer size needed */ 972 char *top_v, *curr_v; /* virtual addrs into memory block */ 973 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 974 u32 data; /* host data register value */ 975 __le32 le32; 976 char *board_name = NULL; 977 978 DBG_printk("In dfx_driver_init...\n"); 979 980 /* Initialize bus-specific hardware registers */ 981 982 dfx_bus_init(dev); 983 984 /* 985 * Initialize default values for configurable parameters 986 * 987 * Note: All of these parameters are ones that a user may 988 * want to customize. It'd be nice to break these 989 * out into Space.c or someplace else that's more 990 * accessible/understandable than this file. 991 */ 992 993 bp->full_duplex_enb = PI_SNMP_K_FALSE; 994 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 995 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 996 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 997 998 /* 999 * Ensure that HW configuration is OK 1000 * 1001 * Note: Depending on the hardware revision, we may need to modify 1002 * some of the configurable parameters to workaround hardware 1003 * limitations. We'll perform this configuration check AFTER 1004 * setting the parameters to their default values. 1005 */ 1006 1007 dfx_bus_config_check(bp); 1008 1009 /* Disable PDQ interrupts first */ 1010 1011 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1012 1013 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1014 1015 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1016 1017 /* Read the factory MAC address from the adapter then save it */ 1018 1019 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 1020 &data) != DFX_K_SUCCESS) { 1021 printk("%s: Could not read adapter factory MAC address!\n", 1022 print_name); 1023 return DFX_K_FAILURE; 1024 } 1025 le32 = cpu_to_le32(data); 1026 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); 1027 1028 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 1029 &data) != DFX_K_SUCCESS) { 1030 printk("%s: Could not read adapter factory MAC address!\n", 1031 print_name); 1032 return DFX_K_FAILURE; 1033 } 1034 le32 = cpu_to_le32(data); 1035 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); 1036 1037 /* 1038 * Set current address to factory address 1039 * 1040 * Note: Node address override support is handled through 1041 * dfx_ctl_set_mac_address. 1042 */ 1043 1044 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1045 if (dfx_bus_tc) 1046 board_name = "DEFTA"; 1047 if (dfx_bus_eisa) 1048 board_name = "DEFEA"; 1049 if (dfx_bus_pci) 1050 board_name = "DEFPA"; 1051 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n", 1052 print_name, board_name, dfx_use_mmio ? "" : "I/O ", 1053 (long long)bar_start, dev->irq, dev->dev_addr); 1054 1055 /* 1056 * Get memory for descriptor block, consumer block, and other buffers 1057 * that need to be DMA read or written to by the adapter. 1058 */ 1059 1060 alloc_size = sizeof(PI_DESCR_BLOCK) + 1061 PI_CMD_REQ_K_SIZE_MAX + 1062 PI_CMD_RSP_K_SIZE_MAX + 1063 #ifndef DYNAMIC_BUFFERS 1064 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 1065 #endif 1066 sizeof(PI_CONSUMER_BLOCK) + 1067 (PI_ALIGN_K_DESC_BLK - 1); 1068 bp->kmalloced = top_v = dma_zalloc_coherent(bp->bus_dev, alloc_size, 1069 &bp->kmalloced_dma, 1070 GFP_ATOMIC); 1071 if (top_v == NULL) 1072 return DFX_K_FAILURE; 1073 1074 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 1075 1076 /* 1077 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 1078 * plus the amount of memory needed was allocated. The physical address 1079 * is now 8K aligned. By carving up the memory in a specific order, 1080 * we'll guarantee the alignment requirements for all other structures. 1081 * 1082 * Note: If the assumptions change regarding the non-paged, non-cached, 1083 * physically contiguous nature of the memory block or the address 1084 * alignments, then we'll need to implement a different algorithm 1085 * for allocating the needed memory. 1086 */ 1087 1088 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 1089 curr_v = top_v + (curr_p - top_p); 1090 1091 /* Reserve space for descriptor block */ 1092 1093 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 1094 bp->descr_block_phys = curr_p; 1095 curr_v += sizeof(PI_DESCR_BLOCK); 1096 curr_p += sizeof(PI_DESCR_BLOCK); 1097 1098 /* Reserve space for command request buffer */ 1099 1100 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 1101 bp->cmd_req_phys = curr_p; 1102 curr_v += PI_CMD_REQ_K_SIZE_MAX; 1103 curr_p += PI_CMD_REQ_K_SIZE_MAX; 1104 1105 /* Reserve space for command response buffer */ 1106 1107 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 1108 bp->cmd_rsp_phys = curr_p; 1109 curr_v += PI_CMD_RSP_K_SIZE_MAX; 1110 curr_p += PI_CMD_RSP_K_SIZE_MAX; 1111 1112 /* Reserve space for the LLC host receive queue buffers */ 1113 1114 bp->rcv_block_virt = curr_v; 1115 bp->rcv_block_phys = curr_p; 1116 1117 #ifndef DYNAMIC_BUFFERS 1118 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1119 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1120 #endif 1121 1122 /* Reserve space for the consumer block */ 1123 1124 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 1125 bp->cons_block_phys = curr_p; 1126 1127 /* Display virtual and physical addresses if debug driver */ 1128 1129 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 1130 print_name, 1131 (long)bp->descr_block_virt, bp->descr_block_phys); 1132 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 1133 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 1134 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 1135 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 1136 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 1137 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 1138 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 1139 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 1140 1141 return DFX_K_SUCCESS; 1142 } 1143 1144 1145 /* 1146 * ================= 1147 * = dfx_adap_init = 1148 * ================= 1149 * 1150 * Overview: 1151 * Brings the adapter to the link avail/link unavailable state. 1152 * 1153 * Returns: 1154 * Condition code 1155 * 1156 * Arguments: 1157 * bp - pointer to board information 1158 * get_buffers - non-zero if buffers to be allocated 1159 * 1160 * Functional Description: 1161 * Issues the low-level firmware/hardware calls necessary to bring 1162 * the adapter up, or to properly reset and restore adapter during 1163 * run-time. 1164 * 1165 * Return Codes: 1166 * DFX_K_SUCCESS - Adapter brought up successfully 1167 * DFX_K_FAILURE - Adapter initialization failed 1168 * 1169 * Assumptions: 1170 * bp->reset_type should be set to a valid reset type value before 1171 * calling this routine. 1172 * 1173 * Side Effects: 1174 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1175 * upon a successful return of this routine. 1176 */ 1177 1178 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1179 { 1180 DBG_printk("In dfx_adap_init...\n"); 1181 1182 /* Disable PDQ interrupts first */ 1183 1184 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1185 1186 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1187 1188 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1189 { 1190 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1191 return DFX_K_FAILURE; 1192 } 1193 1194 /* 1195 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1196 * so we'll acknowledge all Type 0 interrupts now before continuing. 1197 */ 1198 1199 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1200 1201 /* 1202 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1203 * 1204 * Note: We only need to clear host copies of these registers. The PDQ reset 1205 * takes care of the on-board register values. 1206 */ 1207 1208 bp->cmd_req_reg.lword = 0; 1209 bp->cmd_rsp_reg.lword = 0; 1210 bp->rcv_xmt_reg.lword = 0; 1211 1212 /* Clear consumer block before going to DMA_AVAILABLE state */ 1213 1214 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1215 1216 /* Initialize the DMA Burst Size */ 1217 1218 if (dfx_hw_port_ctrl_req(bp, 1219 PI_PCTRL_M_SUB_CMD, 1220 PI_SUB_CMD_K_BURST_SIZE_SET, 1221 bp->burst_size, 1222 NULL) != DFX_K_SUCCESS) 1223 { 1224 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1225 return DFX_K_FAILURE; 1226 } 1227 1228 /* 1229 * Set base address of Consumer Block 1230 * 1231 * Assumption: 32-bit physical address of consumer block is 64 byte 1232 * aligned. That is, bits 0-5 of the address must be zero. 1233 */ 1234 1235 if (dfx_hw_port_ctrl_req(bp, 1236 PI_PCTRL_M_CONS_BLOCK, 1237 bp->cons_block_phys, 1238 0, 1239 NULL) != DFX_K_SUCCESS) 1240 { 1241 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1242 return DFX_K_FAILURE; 1243 } 1244 1245 /* 1246 * Set the base address of Descriptor Block and bring adapter 1247 * to DMA_AVAILABLE state. 1248 * 1249 * Note: We also set the literal and data swapping requirements 1250 * in this command. 1251 * 1252 * Assumption: 32-bit physical address of descriptor block 1253 * is 8Kbyte aligned. 1254 */ 1255 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, 1256 (u32)(bp->descr_block_phys | 1257 PI_PDATA_A_INIT_M_BSWAP_INIT), 1258 0, NULL) != DFX_K_SUCCESS) { 1259 printk("%s: Could not set descriptor block address!\n", 1260 bp->dev->name); 1261 return DFX_K_FAILURE; 1262 } 1263 1264 /* Set transmit flush timeout value */ 1265 1266 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1267 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1268 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1269 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1270 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1271 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1272 { 1273 printk("%s: DMA command request failed!\n", bp->dev->name); 1274 return DFX_K_FAILURE; 1275 } 1276 1277 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1278 1279 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1280 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1281 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1282 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1283 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1284 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1285 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1286 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1287 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1288 { 1289 printk("%s: DMA command request failed!\n", bp->dev->name); 1290 return DFX_K_FAILURE; 1291 } 1292 1293 /* Initialize adapter CAM */ 1294 1295 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1296 { 1297 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1298 return DFX_K_FAILURE; 1299 } 1300 1301 /* Initialize adapter filters */ 1302 1303 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1304 { 1305 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1306 return DFX_K_FAILURE; 1307 } 1308 1309 /* 1310 * Remove any existing dynamic buffers (i.e. if the adapter is being 1311 * reinitialized) 1312 */ 1313 1314 if (get_buffers) 1315 dfx_rcv_flush(bp); 1316 1317 /* Initialize receive descriptor block and produce buffers */ 1318 1319 if (dfx_rcv_init(bp, get_buffers)) 1320 { 1321 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1322 if (get_buffers) 1323 dfx_rcv_flush(bp); 1324 return DFX_K_FAILURE; 1325 } 1326 1327 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1328 1329 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1330 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1331 { 1332 printk("%s: Start command failed\n", bp->dev->name); 1333 if (get_buffers) 1334 dfx_rcv_flush(bp); 1335 return DFX_K_FAILURE; 1336 } 1337 1338 /* Initialization succeeded, reenable PDQ interrupts */ 1339 1340 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1341 return DFX_K_SUCCESS; 1342 } 1343 1344 1345 /* 1346 * ============ 1347 * = dfx_open = 1348 * ============ 1349 * 1350 * Overview: 1351 * Opens the adapter 1352 * 1353 * Returns: 1354 * Condition code 1355 * 1356 * Arguments: 1357 * dev - pointer to device information 1358 * 1359 * Functional Description: 1360 * This function brings the adapter to an operational state. 1361 * 1362 * Return Codes: 1363 * 0 - Adapter was successfully opened 1364 * -EAGAIN - Could not register IRQ or adapter initialization failed 1365 * 1366 * Assumptions: 1367 * This routine should only be called for a device that was 1368 * initialized successfully. 1369 * 1370 * Side Effects: 1371 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1372 * if the open is successful. 1373 */ 1374 1375 static int dfx_open(struct net_device *dev) 1376 { 1377 DFX_board_t *bp = netdev_priv(dev); 1378 int ret; 1379 1380 DBG_printk("In dfx_open...\n"); 1381 1382 /* Register IRQ - support shared interrupts by passing device ptr */ 1383 1384 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, 1385 dev); 1386 if (ret) { 1387 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1388 return ret; 1389 } 1390 1391 /* 1392 * Set current address to factory MAC address 1393 * 1394 * Note: We've already done this step in dfx_driver_init. 1395 * However, it's possible that a user has set a node 1396 * address override, then closed and reopened the 1397 * adapter. Unless we reset the device address field 1398 * now, we'll continue to use the existing modified 1399 * address. 1400 */ 1401 1402 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1403 1404 /* Clear local unicast/multicast address tables and counts */ 1405 1406 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1407 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1408 bp->uc_count = 0; 1409 bp->mc_count = 0; 1410 1411 /* Disable promiscuous filter settings */ 1412 1413 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1414 bp->group_prom = PI_FSTATE_K_BLOCK; 1415 1416 spin_lock_init(&bp->lock); 1417 1418 /* Reset and initialize adapter */ 1419 1420 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1421 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1422 { 1423 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1424 free_irq(dev->irq, dev); 1425 return -EAGAIN; 1426 } 1427 1428 /* Set device structure info */ 1429 netif_start_queue(dev); 1430 return 0; 1431 } 1432 1433 1434 /* 1435 * ============= 1436 * = dfx_close = 1437 * ============= 1438 * 1439 * Overview: 1440 * Closes the device/module. 1441 * 1442 * Returns: 1443 * Condition code 1444 * 1445 * Arguments: 1446 * dev - pointer to device information 1447 * 1448 * Functional Description: 1449 * This routine closes the adapter and brings it to a safe state. 1450 * The interrupt service routine is deregistered with the OS. 1451 * The adapter can be opened again with another call to dfx_open(). 1452 * 1453 * Return Codes: 1454 * Always return 0. 1455 * 1456 * Assumptions: 1457 * No further requests for this adapter are made after this routine is 1458 * called. dfx_open() can be called to reset and reinitialize the 1459 * adapter. 1460 * 1461 * Side Effects: 1462 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1463 * routine. 1464 */ 1465 1466 static int dfx_close(struct net_device *dev) 1467 { 1468 DFX_board_t *bp = netdev_priv(dev); 1469 1470 DBG_printk("In dfx_close...\n"); 1471 1472 /* Disable PDQ interrupts first */ 1473 1474 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1475 1476 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1477 1478 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1479 1480 /* 1481 * Flush any pending transmit buffers 1482 * 1483 * Note: It's important that we flush the transmit buffers 1484 * BEFORE we clear our copy of the Type 2 register. 1485 * Otherwise, we'll have no idea how many buffers 1486 * we need to free. 1487 */ 1488 1489 dfx_xmt_flush(bp); 1490 1491 /* 1492 * Clear Type 1 and Type 2 registers after adapter reset 1493 * 1494 * Note: Even though we're closing the adapter, it's 1495 * possible that an interrupt will occur after 1496 * dfx_close is called. Without some assurance to 1497 * the contrary we want to make sure that we don't 1498 * process receive and transmit LLC frames and update 1499 * the Type 2 register with bad information. 1500 */ 1501 1502 bp->cmd_req_reg.lword = 0; 1503 bp->cmd_rsp_reg.lword = 0; 1504 bp->rcv_xmt_reg.lword = 0; 1505 1506 /* Clear consumer block for the same reason given above */ 1507 1508 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1509 1510 /* Release all dynamically allocate skb in the receive ring. */ 1511 1512 dfx_rcv_flush(bp); 1513 1514 /* Clear device structure flags */ 1515 1516 netif_stop_queue(dev); 1517 1518 /* Deregister (free) IRQ */ 1519 1520 free_irq(dev->irq, dev); 1521 1522 return 0; 1523 } 1524 1525 1526 /* 1527 * ====================== 1528 * = dfx_int_pr_halt_id = 1529 * ====================== 1530 * 1531 * Overview: 1532 * Displays halt id's in string form. 1533 * 1534 * Returns: 1535 * None 1536 * 1537 * Arguments: 1538 * bp - pointer to board information 1539 * 1540 * Functional Description: 1541 * Determine current halt id and display appropriate string. 1542 * 1543 * Return Codes: 1544 * None 1545 * 1546 * Assumptions: 1547 * None 1548 * 1549 * Side Effects: 1550 * None 1551 */ 1552 1553 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1554 { 1555 PI_UINT32 port_status; /* PDQ port status register value */ 1556 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1557 1558 /* Read the latest port status */ 1559 1560 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1561 1562 /* Display halt state transition information */ 1563 1564 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1565 switch (halt_id) 1566 { 1567 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1568 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1569 break; 1570 1571 case PI_HALT_ID_K_PARITY_ERROR: 1572 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1573 break; 1574 1575 case PI_HALT_ID_K_HOST_DIR_HALT: 1576 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1577 break; 1578 1579 case PI_HALT_ID_K_SW_FAULT: 1580 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1581 break; 1582 1583 case PI_HALT_ID_K_HW_FAULT: 1584 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1585 break; 1586 1587 case PI_HALT_ID_K_PC_TRACE: 1588 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1589 break; 1590 1591 case PI_HALT_ID_K_DMA_ERROR: 1592 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1593 break; 1594 1595 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1596 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1597 break; 1598 1599 case PI_HALT_ID_K_BUS_EXCEPTION: 1600 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1601 break; 1602 1603 default: 1604 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1605 break; 1606 } 1607 } 1608 1609 1610 /* 1611 * ========================== 1612 * = dfx_int_type_0_process = 1613 * ========================== 1614 * 1615 * Overview: 1616 * Processes Type 0 interrupts. 1617 * 1618 * Returns: 1619 * None 1620 * 1621 * Arguments: 1622 * bp - pointer to board information 1623 * 1624 * Functional Description: 1625 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1626 * is a serious fault on the adapter, then an error message is displayed 1627 * and the adapter is reset. 1628 * 1629 * One tricky potential timing window is the rapid succession of "link avail" 1630 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1631 * interrupt must be done before reading the state from the Port Status 1632 * register. This is true because a state change could occur after reading 1633 * the data, but before acknowledging the interrupt. If this state change 1634 * does happen, it would be lost because the driver is using the old state, 1635 * and it will never know about the new state because it subsequently 1636 * acknowledges the state change interrupt. 1637 * 1638 * INCORRECT CORRECT 1639 * read type 0 int reasons read type 0 int reasons 1640 * read adapter state ack type 0 interrupts 1641 * ack type 0 interrupts read adapter state 1642 * ... process interrupt ... ... process interrupt ... 1643 * 1644 * Return Codes: 1645 * None 1646 * 1647 * Assumptions: 1648 * None 1649 * 1650 * Side Effects: 1651 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1652 * or if the port status indicates that the adapter is halted. The driver 1653 * is responsible for reinitializing the adapter with the current CAM 1654 * contents and adapter filter settings. 1655 */ 1656 1657 static void dfx_int_type_0_process(DFX_board_t *bp) 1658 1659 { 1660 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1661 PI_UINT32 state; /* current adap state (from port status) */ 1662 1663 /* 1664 * Read host interrupt Type 0 register to determine which Type 0 1665 * interrupts are pending. Immediately write it back out to clear 1666 * those interrupts. 1667 */ 1668 1669 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1670 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1671 1672 /* Check for Type 0 error interrupts */ 1673 1674 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1675 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1676 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1677 { 1678 /* Check for Non-Existent Memory error */ 1679 1680 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1681 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1682 1683 /* Check for Packet Memory Parity error */ 1684 1685 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1686 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1687 1688 /* Check for Host Bus Parity error */ 1689 1690 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1691 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1692 1693 /* Reset adapter and bring it back on-line */ 1694 1695 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1696 bp->reset_type = 0; /* rerun on-board diagnostics */ 1697 printk("%s: Resetting adapter...\n", bp->dev->name); 1698 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1699 { 1700 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1701 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1702 return; 1703 } 1704 printk("%s: Adapter reset successful!\n", bp->dev->name); 1705 return; 1706 } 1707 1708 /* Check for transmit flush interrupt */ 1709 1710 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1711 { 1712 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1713 1714 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1715 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1716 (void) dfx_hw_port_ctrl_req(bp, 1717 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1718 0, 1719 0, 1720 NULL); 1721 } 1722 1723 /* Check for adapter state change */ 1724 1725 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1726 { 1727 /* Get latest adapter state */ 1728 1729 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1730 if (state == PI_STATE_K_HALTED) 1731 { 1732 /* 1733 * Adapter has transitioned to HALTED state, try to reset 1734 * adapter to bring it back on-line. If reset fails, 1735 * leave the adapter in the broken state. 1736 */ 1737 1738 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1739 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1740 1741 /* Reset adapter and bring it back on-line */ 1742 1743 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1744 bp->reset_type = 0; /* rerun on-board diagnostics */ 1745 printk("%s: Resetting adapter...\n", bp->dev->name); 1746 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1747 { 1748 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1749 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1750 return; 1751 } 1752 printk("%s: Adapter reset successful!\n", bp->dev->name); 1753 } 1754 else if (state == PI_STATE_K_LINK_AVAIL) 1755 { 1756 bp->link_available = PI_K_TRUE; /* set link available flag */ 1757 } 1758 } 1759 } 1760 1761 1762 /* 1763 * ================== 1764 * = dfx_int_common = 1765 * ================== 1766 * 1767 * Overview: 1768 * Interrupt service routine (ISR) 1769 * 1770 * Returns: 1771 * None 1772 * 1773 * Arguments: 1774 * bp - pointer to board information 1775 * 1776 * Functional Description: 1777 * This is the ISR which processes incoming adapter interrupts. 1778 * 1779 * Return Codes: 1780 * None 1781 * 1782 * Assumptions: 1783 * This routine assumes PDQ interrupts have not been disabled. 1784 * When interrupts are disabled at the PDQ, the Port Status register 1785 * is automatically cleared. This routine uses the Port Status 1786 * register value to determine whether a Type 0 interrupt occurred, 1787 * so it's important that adapter interrupts are not normally 1788 * enabled/disabled at the PDQ. 1789 * 1790 * It's vital that this routine is NOT reentered for the 1791 * same board and that the OS is not in another section of 1792 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1793 * different thread. 1794 * 1795 * Side Effects: 1796 * Pending interrupts are serviced. Depending on the type of 1797 * interrupt, acknowledging and clearing the interrupt at the 1798 * PDQ involves writing a register to clear the interrupt bit 1799 * or updating completion indices. 1800 */ 1801 1802 static void dfx_int_common(struct net_device *dev) 1803 { 1804 DFX_board_t *bp = netdev_priv(dev); 1805 PI_UINT32 port_status; /* Port Status register */ 1806 1807 /* Process xmt interrupts - frequent case, so always call this routine */ 1808 1809 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1810 netif_wake_queue(dev); 1811 1812 /* Process rcv interrupts - frequent case, so always call this routine */ 1813 1814 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1815 1816 /* 1817 * Transmit and receive producer and completion indices are updated on the 1818 * adapter by writing to the Type 2 Producer register. Since the frequent 1819 * case is that we'll be processing either LLC transmit or receive buffers, 1820 * we'll optimize I/O writes by doing a single register write here. 1821 */ 1822 1823 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1824 1825 /* Read PDQ Port Status register to find out which interrupts need processing */ 1826 1827 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1828 1829 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1830 1831 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1832 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1833 } 1834 1835 1836 /* 1837 * ================= 1838 * = dfx_interrupt = 1839 * ================= 1840 * 1841 * Overview: 1842 * Interrupt processing routine 1843 * 1844 * Returns: 1845 * Whether a valid interrupt was seen. 1846 * 1847 * Arguments: 1848 * irq - interrupt vector 1849 * dev_id - pointer to device information 1850 * 1851 * Functional Description: 1852 * This routine calls the interrupt processing routine for this adapter. It 1853 * disables and reenables adapter interrupts, as appropriate. We can support 1854 * shared interrupts since the incoming dev_id pointer provides our device 1855 * structure context. 1856 * 1857 * Return Codes: 1858 * IRQ_HANDLED - an IRQ was handled. 1859 * IRQ_NONE - no IRQ was handled. 1860 * 1861 * Assumptions: 1862 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1863 * on Intel-based systems) is done by the operating system outside this 1864 * routine. 1865 * 1866 * System interrupts are enabled through this call. 1867 * 1868 * Side Effects: 1869 * Interrupts are disabled, then reenabled at the adapter. 1870 */ 1871 1872 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1873 { 1874 struct net_device *dev = dev_id; 1875 DFX_board_t *bp = netdev_priv(dev); 1876 struct device *bdev = bp->bus_dev; 1877 int dfx_bus_pci = dev_is_pci(bdev); 1878 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 1879 int dfx_bus_tc = DFX_BUS_TC(bdev); 1880 1881 /* Service adapter interrupts */ 1882 1883 if (dfx_bus_pci) { 1884 u32 status; 1885 1886 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1887 if (!(status & PFI_STATUS_M_PDQ_INT)) 1888 return IRQ_NONE; 1889 1890 spin_lock(&bp->lock); 1891 1892 /* Disable PDQ-PFI interrupts at PFI */ 1893 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1894 PFI_MODE_M_DMA_ENB); 1895 1896 /* Call interrupt service routine for this adapter */ 1897 dfx_int_common(dev); 1898 1899 /* Clear PDQ interrupt status bit and reenable interrupts */ 1900 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1901 PFI_STATUS_M_PDQ_INT); 1902 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1903 (PFI_MODE_M_PDQ_INT_ENB | 1904 PFI_MODE_M_DMA_ENB)); 1905 1906 spin_unlock(&bp->lock); 1907 } 1908 if (dfx_bus_eisa) { 1909 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 1910 u8 status; 1911 1912 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1913 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1914 return IRQ_NONE; 1915 1916 spin_lock(&bp->lock); 1917 1918 /* Disable interrupts at the ESIC */ 1919 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1920 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1921 1922 /* Call interrupt service routine for this adapter */ 1923 dfx_int_common(dev); 1924 1925 /* Reenable interrupts at the ESIC */ 1926 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1927 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1928 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1929 1930 spin_unlock(&bp->lock); 1931 } 1932 if (dfx_bus_tc) { 1933 u32 status; 1934 1935 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); 1936 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | 1937 PI_PSTATUS_M_XMT_DATA_PENDING | 1938 PI_PSTATUS_M_SMT_HOST_PENDING | 1939 PI_PSTATUS_M_UNSOL_PENDING | 1940 PI_PSTATUS_M_CMD_RSP_PENDING | 1941 PI_PSTATUS_M_CMD_REQ_PENDING | 1942 PI_PSTATUS_M_TYPE_0_PENDING))) 1943 return IRQ_NONE; 1944 1945 spin_lock(&bp->lock); 1946 1947 /* Call interrupt service routine for this adapter */ 1948 dfx_int_common(dev); 1949 1950 spin_unlock(&bp->lock); 1951 } 1952 1953 return IRQ_HANDLED; 1954 } 1955 1956 1957 /* 1958 * ===================== 1959 * = dfx_ctl_get_stats = 1960 * ===================== 1961 * 1962 * Overview: 1963 * Get statistics for FDDI adapter 1964 * 1965 * Returns: 1966 * Pointer to FDDI statistics structure 1967 * 1968 * Arguments: 1969 * dev - pointer to device information 1970 * 1971 * Functional Description: 1972 * Gets current MIB objects from adapter, then 1973 * returns FDDI statistics structure as defined 1974 * in if_fddi.h. 1975 * 1976 * Note: Since the FDDI statistics structure is 1977 * still new and the device structure doesn't 1978 * have an FDDI-specific get statistics handler, 1979 * we'll return the FDDI statistics structure as 1980 * a pointer to an Ethernet statistics structure. 1981 * That way, at least the first part of the statistics 1982 * structure can be decoded properly, and it allows 1983 * "smart" applications to perform a second cast to 1984 * decode the FDDI-specific statistics. 1985 * 1986 * We'll have to pay attention to this routine as the 1987 * device structure becomes more mature and LAN media 1988 * independent. 1989 * 1990 * Return Codes: 1991 * None 1992 * 1993 * Assumptions: 1994 * None 1995 * 1996 * Side Effects: 1997 * None 1998 */ 1999 2000 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 2001 { 2002 DFX_board_t *bp = netdev_priv(dev); 2003 2004 /* Fill the bp->stats structure with driver-maintained counters */ 2005 2006 bp->stats.gen.rx_packets = bp->rcv_total_frames; 2007 bp->stats.gen.tx_packets = bp->xmt_total_frames; 2008 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 2009 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 2010 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 2011 bp->rcv_frame_status_errors + 2012 bp->rcv_length_errors; 2013 bp->stats.gen.tx_errors = bp->xmt_length_errors; 2014 bp->stats.gen.rx_dropped = bp->rcv_discards; 2015 bp->stats.gen.tx_dropped = bp->xmt_discards; 2016 bp->stats.gen.multicast = bp->rcv_multicast_frames; 2017 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 2018 2019 /* Get FDDI SMT MIB objects */ 2020 2021 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 2022 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2023 return (struct net_device_stats *)&bp->stats; 2024 2025 /* Fill the bp->stats structure with the SMT MIB object values */ 2026 2027 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 2028 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 2029 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 2030 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 2031 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 2032 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 2033 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 2034 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 2035 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 2036 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 2037 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 2038 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 2039 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 2040 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 2041 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 2042 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 2043 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 2044 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 2045 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 2046 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 2047 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 2048 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 2049 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 2050 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 2051 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 2052 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 2053 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 2054 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 2055 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 2056 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 2057 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 2058 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 2059 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 2060 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 2061 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 2062 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 2063 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 2064 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 2065 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 2066 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 2067 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 2068 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 2069 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 2070 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 2071 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 2072 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 2073 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 2074 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 2075 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 2076 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 2077 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 2078 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 2079 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 2080 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 2081 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 2082 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 2083 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 2084 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 2085 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 2086 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 2087 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 2088 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 2089 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 2090 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 2091 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 2092 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 2093 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 2094 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 2095 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 2096 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 2097 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 2098 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 2099 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 2100 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 2101 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 2102 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 2103 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 2104 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 2105 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 2106 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 2107 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 2108 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 2109 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 2110 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 2111 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 2112 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 2113 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 2114 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 2115 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 2116 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 2117 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 2118 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 2119 2120 /* Get FDDI counters */ 2121 2122 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 2123 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2124 return (struct net_device_stats *)&bp->stats; 2125 2126 /* Fill the bp->stats structure with the FDDI counter values */ 2127 2128 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 2129 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 2130 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 2131 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 2132 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 2133 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 2134 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 2135 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 2136 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 2137 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 2138 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 2139 2140 return (struct net_device_stats *)&bp->stats; 2141 } 2142 2143 2144 /* 2145 * ============================== 2146 * = dfx_ctl_set_multicast_list = 2147 * ============================== 2148 * 2149 * Overview: 2150 * Enable/Disable LLC frame promiscuous mode reception 2151 * on the adapter and/or update multicast address table. 2152 * 2153 * Returns: 2154 * None 2155 * 2156 * Arguments: 2157 * dev - pointer to device information 2158 * 2159 * Functional Description: 2160 * This routine follows a fairly simple algorithm for setting the 2161 * adapter filters and CAM: 2162 * 2163 * if IFF_PROMISC flag is set 2164 * enable LLC individual/group promiscuous mode 2165 * else 2166 * disable LLC individual/group promiscuous mode 2167 * if number of incoming multicast addresses > 2168 * (CAM max size - number of unicast addresses in CAM) 2169 * enable LLC group promiscuous mode 2170 * set driver-maintained multicast address count to zero 2171 * else 2172 * disable LLC group promiscuous mode 2173 * set driver-maintained multicast address count to incoming count 2174 * update adapter CAM 2175 * update adapter filters 2176 * 2177 * Return Codes: 2178 * None 2179 * 2180 * Assumptions: 2181 * Multicast addresses are presented in canonical (LSB) format. 2182 * 2183 * Side Effects: 2184 * On-board adapter CAM and filters are updated. 2185 */ 2186 2187 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2188 { 2189 DFX_board_t *bp = netdev_priv(dev); 2190 int i; /* used as index in for loop */ 2191 struct netdev_hw_addr *ha; 2192 2193 /* Enable LLC frame promiscuous mode, if necessary */ 2194 2195 if (dev->flags & IFF_PROMISC) 2196 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2197 2198 /* Else, update multicast address table */ 2199 2200 else 2201 { 2202 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2203 /* 2204 * Check whether incoming multicast address count exceeds table size 2205 * 2206 * Note: The adapters utilize an on-board 64 entry CAM for 2207 * supporting perfect filtering of multicast packets 2208 * and bridge functions when adding unicast addresses. 2209 * There is no hash function available. To support 2210 * additional multicast addresses, the all multicast 2211 * filter (LLC group promiscuous mode) must be enabled. 2212 * 2213 * The firmware reserves two CAM entries for SMT-related 2214 * multicast addresses, which leaves 62 entries available. 2215 * The following code ensures that we're not being asked 2216 * to add more than 62 addresses to the CAM. If we are, 2217 * the driver will enable the all multicast filter. 2218 * Should the number of multicast addresses drop below 2219 * the high water mark, the filter will be disabled and 2220 * perfect filtering will be used. 2221 */ 2222 2223 if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2224 { 2225 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2226 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2227 } 2228 else 2229 { 2230 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2231 bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */ 2232 } 2233 2234 /* Copy addresses to multicast address table, then update adapter CAM */ 2235 2236 i = 0; 2237 netdev_for_each_mc_addr(ha, dev) 2238 memcpy(&bp->mc_table[i++ * FDDI_K_ALEN], 2239 ha->addr, FDDI_K_ALEN); 2240 2241 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2242 { 2243 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2244 } 2245 else 2246 { 2247 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2248 } 2249 } 2250 2251 /* Update adapter filters */ 2252 2253 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2254 { 2255 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2256 } 2257 else 2258 { 2259 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2260 } 2261 } 2262 2263 2264 /* 2265 * =========================== 2266 * = dfx_ctl_set_mac_address = 2267 * =========================== 2268 * 2269 * Overview: 2270 * Add node address override (unicast address) to adapter 2271 * CAM and update dev_addr field in device table. 2272 * 2273 * Returns: 2274 * None 2275 * 2276 * Arguments: 2277 * dev - pointer to device information 2278 * addr - pointer to sockaddr structure containing unicast address to add 2279 * 2280 * Functional Description: 2281 * The adapter supports node address overrides by adding one or more 2282 * unicast addresses to the adapter CAM. This is similar to adding 2283 * multicast addresses. In this routine we'll update the driver and 2284 * device structures with the new address, then update the adapter CAM 2285 * to ensure that the adapter will copy and strip frames destined and 2286 * sourced by that address. 2287 * 2288 * Return Codes: 2289 * Always returns zero. 2290 * 2291 * Assumptions: 2292 * The address pointed to by addr->sa_data is a valid unicast 2293 * address and is presented in canonical (LSB) format. 2294 * 2295 * Side Effects: 2296 * On-board adapter CAM is updated. On-board adapter filters 2297 * may be updated. 2298 */ 2299 2300 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2301 { 2302 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2303 DFX_board_t *bp = netdev_priv(dev); 2304 2305 /* Copy unicast address to driver-maintained structs and update count */ 2306 2307 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2308 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2309 bp->uc_count = 1; 2310 2311 /* 2312 * Verify we're not exceeding the CAM size by adding unicast address 2313 * 2314 * Note: It's possible that before entering this routine we've 2315 * already filled the CAM with 62 multicast addresses. 2316 * Since we need to place the node address override into 2317 * the CAM, we have to check to see that we're not 2318 * exceeding the CAM size. If we are, we have to enable 2319 * the LLC group (multicast) promiscuous mode filter as 2320 * in dfx_ctl_set_multicast_list. 2321 */ 2322 2323 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2324 { 2325 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2326 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2327 2328 /* Update adapter filters */ 2329 2330 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2331 { 2332 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2333 } 2334 else 2335 { 2336 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2337 } 2338 } 2339 2340 /* Update adapter CAM with new unicast address */ 2341 2342 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2343 { 2344 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2345 } 2346 else 2347 { 2348 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2349 } 2350 return 0; /* always return zero */ 2351 } 2352 2353 2354 /* 2355 * ====================== 2356 * = dfx_ctl_update_cam = 2357 * ====================== 2358 * 2359 * Overview: 2360 * Procedure to update adapter CAM (Content Addressable Memory) 2361 * with desired unicast and multicast address entries. 2362 * 2363 * Returns: 2364 * Condition code 2365 * 2366 * Arguments: 2367 * bp - pointer to board information 2368 * 2369 * Functional Description: 2370 * Updates adapter CAM with current contents of board structure 2371 * unicast and multicast address tables. Since there are only 62 2372 * free entries in CAM, this routine ensures that the command 2373 * request buffer is not overrun. 2374 * 2375 * Return Codes: 2376 * DFX_K_SUCCESS - Request succeeded 2377 * DFX_K_FAILURE - Request failed 2378 * 2379 * Assumptions: 2380 * All addresses being added (unicast and multicast) are in canonical 2381 * order. 2382 * 2383 * Side Effects: 2384 * On-board adapter CAM is updated. 2385 */ 2386 2387 static int dfx_ctl_update_cam(DFX_board_t *bp) 2388 { 2389 int i; /* used as index */ 2390 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2391 2392 /* 2393 * Fill in command request information 2394 * 2395 * Note: Even though both the unicast and multicast address 2396 * table entries are stored as contiguous 6 byte entries, 2397 * the firmware address filter set command expects each 2398 * entry to be two longwords (8 bytes total). We must be 2399 * careful to only copy the six bytes of each unicast and 2400 * multicast table entry into each command entry. This 2401 * is also why we must first clear the entire command 2402 * request buffer. 2403 */ 2404 2405 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2406 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2407 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2408 2409 /* Now add unicast addresses to command request buffer, if any */ 2410 2411 for (i=0; i < (int)bp->uc_count; i++) 2412 { 2413 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2414 { 2415 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2416 p_addr++; /* point to next command entry */ 2417 } 2418 } 2419 2420 /* Now add multicast addresses to command request buffer, if any */ 2421 2422 for (i=0; i < (int)bp->mc_count; i++) 2423 { 2424 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2425 { 2426 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2427 p_addr++; /* point to next command entry */ 2428 } 2429 } 2430 2431 /* Issue command to update adapter CAM, then return */ 2432 2433 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2434 return DFX_K_FAILURE; 2435 return DFX_K_SUCCESS; 2436 } 2437 2438 2439 /* 2440 * ========================== 2441 * = dfx_ctl_update_filters = 2442 * ========================== 2443 * 2444 * Overview: 2445 * Procedure to update adapter filters with desired 2446 * filter settings. 2447 * 2448 * Returns: 2449 * Condition code 2450 * 2451 * Arguments: 2452 * bp - pointer to board information 2453 * 2454 * Functional Description: 2455 * Enables or disables filter using current filter settings. 2456 * 2457 * Return Codes: 2458 * DFX_K_SUCCESS - Request succeeded. 2459 * DFX_K_FAILURE - Request failed. 2460 * 2461 * Assumptions: 2462 * We must always pass up packets destined to the broadcast 2463 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2464 * broadcast filter enabled. 2465 * 2466 * Side Effects: 2467 * On-board adapter filters are updated. 2468 */ 2469 2470 static int dfx_ctl_update_filters(DFX_board_t *bp) 2471 { 2472 int i = 0; /* used as index */ 2473 2474 /* Fill in command request information */ 2475 2476 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2477 2478 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2479 2480 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2481 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2482 2483 /* Initialize LLC Individual/Group Promiscuous filter */ 2484 2485 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2486 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2487 2488 /* Initialize LLC Group Promiscuous filter */ 2489 2490 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2491 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2492 2493 /* Terminate the item code list */ 2494 2495 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2496 2497 /* Issue command to update adapter filters, then return */ 2498 2499 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2500 return DFX_K_FAILURE; 2501 return DFX_K_SUCCESS; 2502 } 2503 2504 2505 /* 2506 * ====================== 2507 * = dfx_hw_dma_cmd_req = 2508 * ====================== 2509 * 2510 * Overview: 2511 * Sends PDQ DMA command to adapter firmware 2512 * 2513 * Returns: 2514 * Condition code 2515 * 2516 * Arguments: 2517 * bp - pointer to board information 2518 * 2519 * Functional Description: 2520 * The command request and response buffers are posted to the adapter in the manner 2521 * described in the PDQ Port Specification: 2522 * 2523 * 1. Command Response Buffer is posted to adapter. 2524 * 2. Command Request Buffer is posted to adapter. 2525 * 3. Command Request consumer index is polled until it indicates that request 2526 * buffer has been DMA'd to adapter. 2527 * 4. Command Response consumer index is polled until it indicates that response 2528 * buffer has been DMA'd from adapter. 2529 * 2530 * This ordering ensures that a response buffer is already available for the firmware 2531 * to use once it's done processing the request buffer. 2532 * 2533 * Return Codes: 2534 * DFX_K_SUCCESS - DMA command succeeded 2535 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2536 * DFX_K_HW_TIMEOUT - DMA command timed out 2537 * 2538 * Assumptions: 2539 * Command request buffer has already been filled with desired DMA command. 2540 * 2541 * Side Effects: 2542 * None 2543 */ 2544 2545 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2546 { 2547 int status; /* adapter status */ 2548 int timeout_cnt; /* used in for loops */ 2549 2550 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2551 2552 status = dfx_hw_adap_state_rd(bp); 2553 if ((status == PI_STATE_K_RESET) || 2554 (status == PI_STATE_K_HALTED) || 2555 (status == PI_STATE_K_DMA_UNAVAIL) || 2556 (status == PI_STATE_K_UPGRADE)) 2557 return DFX_K_OUTSTATE; 2558 2559 /* Put response buffer on the command response queue */ 2560 2561 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2562 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2563 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2564 2565 /* Bump (and wrap) the producer index and write out to register */ 2566 2567 bp->cmd_rsp_reg.index.prod += 1; 2568 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2569 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2570 2571 /* Put request buffer on the command request queue */ 2572 2573 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2574 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2575 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2576 2577 /* Bump (and wrap) the producer index and write out to register */ 2578 2579 bp->cmd_req_reg.index.prod += 1; 2580 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2581 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2582 2583 /* 2584 * Here we wait for the command request consumer index to be equal 2585 * to the producer, indicating that the adapter has DMAed the request. 2586 */ 2587 2588 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2589 { 2590 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2591 break; 2592 udelay(100); /* wait for 100 microseconds */ 2593 } 2594 if (timeout_cnt == 0) 2595 return DFX_K_HW_TIMEOUT; 2596 2597 /* Bump (and wrap) the completion index and write out to register */ 2598 2599 bp->cmd_req_reg.index.comp += 1; 2600 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2601 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2602 2603 /* 2604 * Here we wait for the command response consumer index to be equal 2605 * to the producer, indicating that the adapter has DMAed the response. 2606 */ 2607 2608 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2609 { 2610 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2611 break; 2612 udelay(100); /* wait for 100 microseconds */ 2613 } 2614 if (timeout_cnt == 0) 2615 return DFX_K_HW_TIMEOUT; 2616 2617 /* Bump (and wrap) the completion index and write out to register */ 2618 2619 bp->cmd_rsp_reg.index.comp += 1; 2620 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2621 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2622 return DFX_K_SUCCESS; 2623 } 2624 2625 2626 /* 2627 * ======================== 2628 * = dfx_hw_port_ctrl_req = 2629 * ======================== 2630 * 2631 * Overview: 2632 * Sends PDQ port control command to adapter firmware 2633 * 2634 * Returns: 2635 * Host data register value in host_data if ptr is not NULL 2636 * 2637 * Arguments: 2638 * bp - pointer to board information 2639 * command - port control command 2640 * data_a - port data A register value 2641 * data_b - port data B register value 2642 * host_data - ptr to host data register value 2643 * 2644 * Functional Description: 2645 * Send generic port control command to adapter by writing 2646 * to various PDQ port registers, then polling for completion. 2647 * 2648 * Return Codes: 2649 * DFX_K_SUCCESS - port control command succeeded 2650 * DFX_K_HW_TIMEOUT - port control command timed out 2651 * 2652 * Assumptions: 2653 * None 2654 * 2655 * Side Effects: 2656 * None 2657 */ 2658 2659 static int dfx_hw_port_ctrl_req( 2660 DFX_board_t *bp, 2661 PI_UINT32 command, 2662 PI_UINT32 data_a, 2663 PI_UINT32 data_b, 2664 PI_UINT32 *host_data 2665 ) 2666 2667 { 2668 PI_UINT32 port_cmd; /* Port Control command register value */ 2669 int timeout_cnt; /* used in for loops */ 2670 2671 /* Set Command Error bit in command longword */ 2672 2673 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2674 2675 /* Issue port command to the adapter */ 2676 2677 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2678 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2679 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2680 2681 /* Now wait for command to complete */ 2682 2683 if (command == PI_PCTRL_M_BLAST_FLASH) 2684 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2685 else 2686 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2687 2688 for (; timeout_cnt > 0; timeout_cnt--) 2689 { 2690 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2691 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2692 break; 2693 udelay(100); /* wait for 100 microseconds */ 2694 } 2695 if (timeout_cnt == 0) 2696 return DFX_K_HW_TIMEOUT; 2697 2698 /* 2699 * If the address of host_data is non-zero, assume caller has supplied a 2700 * non NULL pointer, and return the contents of the HOST_DATA register in 2701 * it. 2702 */ 2703 2704 if (host_data != NULL) 2705 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2706 return DFX_K_SUCCESS; 2707 } 2708 2709 2710 /* 2711 * ===================== 2712 * = dfx_hw_adap_reset = 2713 * ===================== 2714 * 2715 * Overview: 2716 * Resets adapter 2717 * 2718 * Returns: 2719 * None 2720 * 2721 * Arguments: 2722 * bp - pointer to board information 2723 * type - type of reset to perform 2724 * 2725 * Functional Description: 2726 * Issue soft reset to adapter by writing to PDQ Port Reset 2727 * register. Use incoming reset type to tell adapter what 2728 * kind of reset operation to perform. 2729 * 2730 * Return Codes: 2731 * None 2732 * 2733 * Assumptions: 2734 * This routine merely issues a soft reset to the adapter. 2735 * It is expected that after this routine returns, the caller 2736 * will appropriately poll the Port Status register for the 2737 * adapter to enter the proper state. 2738 * 2739 * Side Effects: 2740 * Internal adapter registers are cleared. 2741 */ 2742 2743 static void dfx_hw_adap_reset( 2744 DFX_board_t *bp, 2745 PI_UINT32 type 2746 ) 2747 2748 { 2749 /* Set Reset type and assert reset */ 2750 2751 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2752 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2753 2754 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2755 2756 udelay(20); 2757 2758 /* Deassert reset */ 2759 2760 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2761 } 2762 2763 2764 /* 2765 * ======================== 2766 * = dfx_hw_adap_state_rd = 2767 * ======================== 2768 * 2769 * Overview: 2770 * Returns current adapter state 2771 * 2772 * Returns: 2773 * Adapter state per PDQ Port Specification 2774 * 2775 * Arguments: 2776 * bp - pointer to board information 2777 * 2778 * Functional Description: 2779 * Reads PDQ Port Status register and returns adapter state. 2780 * 2781 * Return Codes: 2782 * None 2783 * 2784 * Assumptions: 2785 * None 2786 * 2787 * Side Effects: 2788 * None 2789 */ 2790 2791 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2792 { 2793 PI_UINT32 port_status; /* Port Status register value */ 2794 2795 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2796 return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE; 2797 } 2798 2799 2800 /* 2801 * ===================== 2802 * = dfx_hw_dma_uninit = 2803 * ===================== 2804 * 2805 * Overview: 2806 * Brings adapter to DMA_UNAVAILABLE state 2807 * 2808 * Returns: 2809 * Condition code 2810 * 2811 * Arguments: 2812 * bp - pointer to board information 2813 * type - type of reset to perform 2814 * 2815 * Functional Description: 2816 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2817 * 1. Set reset type bit in Port Data A Register then reset adapter. 2818 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2819 * 2820 * Return Codes: 2821 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2822 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2823 * 2824 * Assumptions: 2825 * None 2826 * 2827 * Side Effects: 2828 * Internal adapter registers are cleared. 2829 */ 2830 2831 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2832 { 2833 int timeout_cnt; /* used in for loops */ 2834 2835 /* Set reset type bit and reset adapter */ 2836 2837 dfx_hw_adap_reset(bp, type); 2838 2839 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2840 2841 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2842 { 2843 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2844 break; 2845 udelay(100); /* wait for 100 microseconds */ 2846 } 2847 if (timeout_cnt == 0) 2848 return DFX_K_HW_TIMEOUT; 2849 return DFX_K_SUCCESS; 2850 } 2851 2852 /* 2853 * Align an sk_buff to a boundary power of 2 2854 * 2855 */ 2856 #ifdef DYNAMIC_BUFFERS 2857 static void my_skb_align(struct sk_buff *skb, int n) 2858 { 2859 unsigned long x = (unsigned long)skb->data; 2860 unsigned long v; 2861 2862 v = ALIGN(x, n); /* Where we want to be */ 2863 2864 skb_reserve(skb, v - x); 2865 } 2866 #endif 2867 2868 /* 2869 * ================ 2870 * = dfx_rcv_init = 2871 * ================ 2872 * 2873 * Overview: 2874 * Produces buffers to adapter LLC Host receive descriptor block 2875 * 2876 * Returns: 2877 * None 2878 * 2879 * Arguments: 2880 * bp - pointer to board information 2881 * get_buffers - non-zero if buffers to be allocated 2882 * 2883 * Functional Description: 2884 * This routine can be called during dfx_adap_init() or during an adapter 2885 * reset. It initializes the descriptor block and produces all allocated 2886 * LLC Host queue receive buffers. 2887 * 2888 * Return Codes: 2889 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2890 * dynamic buffer allocation). If the buffer allocation failed, the 2891 * already allocated buffers will not be released and the caller should do 2892 * this. 2893 * 2894 * Assumptions: 2895 * The PDQ has been reset and the adapter and driver maintained Type 2 2896 * register indices are cleared. 2897 * 2898 * Side Effects: 2899 * Receive buffers are posted to the adapter LLC queue and the adapter 2900 * is notified. 2901 */ 2902 2903 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2904 { 2905 int i, j; /* used in for loop */ 2906 2907 /* 2908 * Since each receive buffer is a single fragment of same length, initialize 2909 * first longword in each receive descriptor for entire LLC Host descriptor 2910 * block. Also initialize second longword in each receive descriptor with 2911 * physical address of receive buffer. We'll always allocate receive 2912 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2913 * block and produce new receive buffers by simply updating the receive 2914 * producer index. 2915 * 2916 * Assumptions: 2917 * To support all shipping versions of PDQ, the receive buffer size 2918 * must be mod 128 in length and the physical address must be 128 byte 2919 * aligned. In other words, bits 0-6 of the length and address must 2920 * be zero for the following descriptor field entries to be correct on 2921 * all PDQ-based boards. We guaranteed both requirements during 2922 * driver initialization when we allocated memory for the receive buffers. 2923 */ 2924 2925 if (get_buffers) { 2926 #ifdef DYNAMIC_BUFFERS 2927 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2928 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2929 { 2930 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO); 2931 if (!newskb) 2932 return -ENOMEM; 2933 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2934 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2935 /* 2936 * align to 128 bytes for compatibility with 2937 * the old EISA boards. 2938 */ 2939 2940 my_skb_align(newskb, 128); 2941 bp->descr_block_virt->rcv_data[i + j].long_1 = 2942 (u32)dma_map_single(bp->bus_dev, newskb->data, 2943 NEW_SKB_SIZE, 2944 DMA_FROM_DEVICE); 2945 /* 2946 * p_rcv_buff_va is only used inside the 2947 * kernel so we put the skb pointer here. 2948 */ 2949 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2950 } 2951 #else 2952 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2953 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2954 { 2955 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2956 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2957 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2958 bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2959 } 2960 #endif 2961 } 2962 2963 /* Update receive producer and Type 2 register */ 2964 2965 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2966 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2967 return 0; 2968 } 2969 2970 2971 /* 2972 * ========================= 2973 * = dfx_rcv_queue_process = 2974 * ========================= 2975 * 2976 * Overview: 2977 * Process received LLC frames. 2978 * 2979 * Returns: 2980 * None 2981 * 2982 * Arguments: 2983 * bp - pointer to board information 2984 * 2985 * Functional Description: 2986 * Received LLC frames are processed until there are no more consumed frames. 2987 * Once all frames are processed, the receive buffers are returned to the 2988 * adapter. Note that this algorithm fixes the length of time that can be spent 2989 * in this routine, because there are a fixed number of receive buffers to 2990 * process and buffers are not produced until this routine exits and returns 2991 * to the ISR. 2992 * 2993 * Return Codes: 2994 * None 2995 * 2996 * Assumptions: 2997 * None 2998 * 2999 * Side Effects: 3000 * None 3001 */ 3002 3003 static void dfx_rcv_queue_process( 3004 DFX_board_t *bp 3005 ) 3006 3007 { 3008 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3009 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 3010 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 3011 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 3012 3013 /* Service all consumed LLC receive frames */ 3014 3015 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3016 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 3017 { 3018 /* Process any errors */ 3019 3020 int entry; 3021 3022 entry = bp->rcv_xmt_reg.index.rcv_comp; 3023 #ifdef DYNAMIC_BUFFERS 3024 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 3025 #else 3026 p_buff = bp->p_rcv_buff_va[entry]; 3027 #endif 3028 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 3029 3030 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 3031 { 3032 if (descr & PI_FMC_DESCR_M_RCC_CRC) 3033 bp->rcv_crc_errors++; 3034 else 3035 bp->rcv_frame_status_errors++; 3036 } 3037 else 3038 { 3039 int rx_in_place = 0; 3040 3041 /* The frame was received without errors - verify packet length */ 3042 3043 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 3044 pkt_len -= 4; /* subtract 4 byte CRC */ 3045 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3046 bp->rcv_length_errors++; 3047 else{ 3048 #ifdef DYNAMIC_BUFFERS 3049 if (pkt_len > SKBUFF_RX_COPYBREAK) { 3050 struct sk_buff *newskb; 3051 3052 newskb = dev_alloc_skb(NEW_SKB_SIZE); 3053 if (newskb){ 3054 rx_in_place = 1; 3055 3056 my_skb_align(newskb, 128); 3057 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 3058 dma_unmap_single(bp->bus_dev, 3059 bp->descr_block_virt->rcv_data[entry].long_1, 3060 NEW_SKB_SIZE, 3061 DMA_FROM_DEVICE); 3062 skb_reserve(skb, RCV_BUFF_K_PADDING); 3063 bp->p_rcv_buff_va[entry] = (char *)newskb; 3064 bp->descr_block_virt->rcv_data[entry].long_1 = 3065 (u32)dma_map_single(bp->bus_dev, 3066 newskb->data, 3067 NEW_SKB_SIZE, 3068 DMA_FROM_DEVICE); 3069 } else 3070 skb = NULL; 3071 } else 3072 #endif 3073 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 3074 if (skb == NULL) 3075 { 3076 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 3077 bp->rcv_discards++; 3078 break; 3079 } 3080 else { 3081 if (!rx_in_place) { 3082 /* Receive buffer allocated, pass receive packet up */ 3083 3084 skb_copy_to_linear_data(skb, 3085 p_buff + RCV_BUFF_K_PADDING, 3086 pkt_len + 3); 3087 } 3088 3089 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 3090 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 3091 skb->protocol = fddi_type_trans(skb, bp->dev); 3092 bp->rcv_total_bytes += skb->len; 3093 netif_rx(skb); 3094 3095 /* Update the rcv counters */ 3096 bp->rcv_total_frames++; 3097 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 3098 bp->rcv_multicast_frames++; 3099 } 3100 } 3101 } 3102 3103 /* 3104 * Advance the producer (for recycling) and advance the completion 3105 * (for servicing received frames). Note that it is okay to 3106 * advance the producer without checking that it passes the 3107 * completion index because they are both advanced at the same 3108 * rate. 3109 */ 3110 3111 bp->rcv_xmt_reg.index.rcv_prod += 1; 3112 bp->rcv_xmt_reg.index.rcv_comp += 1; 3113 } 3114 } 3115 3116 3117 /* 3118 * ===================== 3119 * = dfx_xmt_queue_pkt = 3120 * ===================== 3121 * 3122 * Overview: 3123 * Queues packets for transmission 3124 * 3125 * Returns: 3126 * Condition code 3127 * 3128 * Arguments: 3129 * skb - pointer to sk_buff to queue for transmission 3130 * dev - pointer to device information 3131 * 3132 * Functional Description: 3133 * Here we assume that an incoming skb transmit request 3134 * is contained in a single physically contiguous buffer 3135 * in which the virtual address of the start of packet 3136 * (skb->data) can be converted to a physical address 3137 * by using pci_map_single(). 3138 * 3139 * Since the adapter architecture requires a three byte 3140 * packet request header to prepend the start of packet, 3141 * we'll write the three byte field immediately prior to 3142 * the FC byte. This assumption is valid because we've 3143 * ensured that dev->hard_header_len includes three pad 3144 * bytes. By posting a single fragment to the adapter, 3145 * we'll reduce the number of descriptor fetches and 3146 * bus traffic needed to send the request. 3147 * 3148 * Also, we can't free the skb until after it's been DMA'd 3149 * out by the adapter, so we'll queue it in the driver and 3150 * return it in dfx_xmt_done. 3151 * 3152 * Return Codes: 3153 * 0 - driver queued packet, link is unavailable, or skbuff was bad 3154 * 1 - caller should requeue the sk_buff for later transmission 3155 * 3156 * Assumptions: 3157 * First and foremost, we assume the incoming skb pointer 3158 * is NOT NULL and is pointing to a valid sk_buff structure. 3159 * 3160 * The outgoing packet is complete, starting with the 3161 * frame control byte including the last byte of data, 3162 * but NOT including the 4 byte CRC. We'll let the 3163 * adapter hardware generate and append the CRC. 3164 * 3165 * The entire packet is stored in one physically 3166 * contiguous buffer which is not cached and whose 3167 * 32-bit physical address can be determined. 3168 * 3169 * It's vital that this routine is NOT reentered for the 3170 * same board and that the OS is not in another section of 3171 * code (eg. dfx_int_common) for the same board on a 3172 * different thread. 3173 * 3174 * Side Effects: 3175 * None 3176 */ 3177 3178 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 3179 struct net_device *dev) 3180 { 3181 DFX_board_t *bp = netdev_priv(dev); 3182 u8 prod; /* local transmit producer index */ 3183 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3184 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3185 unsigned long flags; 3186 3187 netif_stop_queue(dev); 3188 3189 /* 3190 * Verify that incoming transmit request is OK 3191 * 3192 * Note: The packet size check is consistent with other 3193 * Linux device drivers, although the correct packet 3194 * size should be verified before calling the 3195 * transmit routine. 3196 */ 3197 3198 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3199 { 3200 printk("%s: Invalid packet length - %u bytes\n", 3201 dev->name, skb->len); 3202 bp->xmt_length_errors++; /* bump error counter */ 3203 netif_wake_queue(dev); 3204 dev_kfree_skb(skb); 3205 return NETDEV_TX_OK; /* return "success" */ 3206 } 3207 /* 3208 * See if adapter link is available, if not, free buffer 3209 * 3210 * Note: If the link isn't available, free buffer and return 0 3211 * rather than tell the upper layer to requeue the packet. 3212 * The methodology here is that by the time the link 3213 * becomes available, the packet to be sent will be 3214 * fairly stale. By simply dropping the packet, the 3215 * higher layer protocols will eventually time out 3216 * waiting for response packets which it won't receive. 3217 */ 3218 3219 if (bp->link_available == PI_K_FALSE) 3220 { 3221 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3222 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3223 else 3224 { 3225 bp->xmt_discards++; /* bump error counter */ 3226 dev_kfree_skb(skb); /* free sk_buff now */ 3227 netif_wake_queue(dev); 3228 return NETDEV_TX_OK; /* return "success" */ 3229 } 3230 } 3231 3232 spin_lock_irqsave(&bp->lock, flags); 3233 3234 /* Get the current producer and the next free xmt data descriptor */ 3235 3236 prod = bp->rcv_xmt_reg.index.xmt_prod; 3237 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3238 3239 /* 3240 * Get pointer to auxiliary queue entry to contain information 3241 * for this packet. 3242 * 3243 * Note: The current xmt producer index will become the 3244 * current xmt completion index when we complete this 3245 * packet later on. So, we'll get the pointer to the 3246 * next auxiliary queue entry now before we bump the 3247 * producer index. 3248 */ 3249 3250 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3251 3252 /* Write the three PRH bytes immediately before the FC byte */ 3253 3254 skb_push(skb,3); 3255 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3256 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3257 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3258 3259 /* 3260 * Write the descriptor with buffer info and bump producer 3261 * 3262 * Note: Since we need to start DMA from the packet request 3263 * header, we'll add 3 bytes to the DMA buffer length, 3264 * and we'll determine the physical address of the 3265 * buffer from the PRH, not skb->data. 3266 * 3267 * Assumptions: 3268 * 1. Packet starts with the frame control (FC) byte 3269 * at skb->data. 3270 * 2. The 4-byte CRC is not appended to the buffer or 3271 * included in the length. 3272 * 3. Packet length (skb->len) is from FC to end of 3273 * data, inclusive. 3274 * 4. The packet length does not exceed the maximum 3275 * FDDI LLC frame length of 4491 bytes. 3276 * 5. The entire packet is contained in a physically 3277 * contiguous, non-cached, locked memory space 3278 * comprised of a single buffer pointed to by 3279 * skb->data. 3280 * 6. The physical address of the start of packet 3281 * can be determined from the virtual address 3282 * by using pci_map_single() and is only 32-bits 3283 * wide. 3284 */ 3285 3286 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3287 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data, 3288 skb->len, DMA_TO_DEVICE); 3289 3290 /* 3291 * Verify that descriptor is actually available 3292 * 3293 * Note: If descriptor isn't available, return 1 which tells 3294 * the upper layer to requeue the packet for later 3295 * transmission. 3296 * 3297 * We need to ensure that the producer never reaches the 3298 * completion, except to indicate that the queue is empty. 3299 */ 3300 3301 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3302 { 3303 skb_pull(skb,3); 3304 spin_unlock_irqrestore(&bp->lock, flags); 3305 return NETDEV_TX_BUSY; /* requeue packet for later */ 3306 } 3307 3308 /* 3309 * Save info for this packet for xmt done indication routine 3310 * 3311 * Normally, we'd save the producer index in the p_xmt_drv_descr 3312 * structure so that we'd have it handy when we complete this 3313 * packet later (in dfx_xmt_done). However, since the current 3314 * transmit architecture guarantees a single fragment for the 3315 * entire packet, we can simply bump the completion index by 3316 * one (1) for each completed packet. 3317 * 3318 * Note: If this assumption changes and we're presented with 3319 * an inconsistent number of transmit fragments for packet 3320 * data, we'll need to modify this code to save the current 3321 * transmit producer index. 3322 */ 3323 3324 p_xmt_drv_descr->p_skb = skb; 3325 3326 /* Update Type 2 register */ 3327 3328 bp->rcv_xmt_reg.index.xmt_prod = prod; 3329 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3330 spin_unlock_irqrestore(&bp->lock, flags); 3331 netif_wake_queue(dev); 3332 return NETDEV_TX_OK; /* packet queued to adapter */ 3333 } 3334 3335 3336 /* 3337 * ================ 3338 * = dfx_xmt_done = 3339 * ================ 3340 * 3341 * Overview: 3342 * Processes all frames that have been transmitted. 3343 * 3344 * Returns: 3345 * None 3346 * 3347 * Arguments: 3348 * bp - pointer to board information 3349 * 3350 * Functional Description: 3351 * For all consumed transmit descriptors that have not 3352 * yet been completed, we'll free the skb we were holding 3353 * onto using dev_kfree_skb and bump the appropriate 3354 * counters. 3355 * 3356 * Return Codes: 3357 * None 3358 * 3359 * Assumptions: 3360 * The Type 2 register is not updated in this routine. It is 3361 * assumed that it will be updated in the ISR when dfx_xmt_done 3362 * returns. 3363 * 3364 * Side Effects: 3365 * None 3366 */ 3367 3368 static int dfx_xmt_done(DFX_board_t *bp) 3369 { 3370 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3371 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3372 u8 comp; /* local transmit completion index */ 3373 int freed = 0; /* buffers freed */ 3374 3375 /* Service all consumed transmit frames */ 3376 3377 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3378 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3379 { 3380 /* Get pointer to the transmit driver descriptor block information */ 3381 3382 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3383 3384 /* Increment transmit counters */ 3385 3386 bp->xmt_total_frames++; 3387 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3388 3389 /* Return skb to operating system */ 3390 comp = bp->rcv_xmt_reg.index.xmt_comp; 3391 dma_unmap_single(bp->bus_dev, 3392 bp->descr_block_virt->xmt_data[comp].long_1, 3393 p_xmt_drv_descr->p_skb->len, 3394 DMA_TO_DEVICE); 3395 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3396 3397 /* 3398 * Move to start of next packet by updating completion index 3399 * 3400 * Here we assume that a transmit packet request is always 3401 * serviced by posting one fragment. We can therefore 3402 * simplify the completion code by incrementing the 3403 * completion index by one. This code will need to be 3404 * modified if this assumption changes. See comments 3405 * in dfx_xmt_queue_pkt for more details. 3406 */ 3407 3408 bp->rcv_xmt_reg.index.xmt_comp += 1; 3409 freed++; 3410 } 3411 return freed; 3412 } 3413 3414 3415 /* 3416 * ================= 3417 * = dfx_rcv_flush = 3418 * ================= 3419 * 3420 * Overview: 3421 * Remove all skb's in the receive ring. 3422 * 3423 * Returns: 3424 * None 3425 * 3426 * Arguments: 3427 * bp - pointer to board information 3428 * 3429 * Functional Description: 3430 * Free's all the dynamically allocated skb's that are 3431 * currently attached to the device receive ring. This 3432 * function is typically only used when the device is 3433 * initialized or reinitialized. 3434 * 3435 * Return Codes: 3436 * None 3437 * 3438 * Side Effects: 3439 * None 3440 */ 3441 #ifdef DYNAMIC_BUFFERS 3442 static void dfx_rcv_flush( DFX_board_t *bp ) 3443 { 3444 int i, j; 3445 3446 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3447 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3448 { 3449 struct sk_buff *skb; 3450 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3451 if (skb) 3452 dev_kfree_skb(skb); 3453 bp->p_rcv_buff_va[i+j] = NULL; 3454 } 3455 3456 } 3457 #endif /* DYNAMIC_BUFFERS */ 3458 3459 /* 3460 * ================= 3461 * = dfx_xmt_flush = 3462 * ================= 3463 * 3464 * Overview: 3465 * Processes all frames whether they've been transmitted 3466 * or not. 3467 * 3468 * Returns: 3469 * None 3470 * 3471 * Arguments: 3472 * bp - pointer to board information 3473 * 3474 * Functional Description: 3475 * For all produced transmit descriptors that have not 3476 * yet been completed, we'll free the skb we were holding 3477 * onto using dev_kfree_skb and bump the appropriate 3478 * counters. Of course, it's possible that some of 3479 * these transmit requests actually did go out, but we 3480 * won't make that distinction here. Finally, we'll 3481 * update the consumer index to match the producer. 3482 * 3483 * Return Codes: 3484 * None 3485 * 3486 * Assumptions: 3487 * This routine does NOT update the Type 2 register. It 3488 * is assumed that this routine is being called during a 3489 * transmit flush interrupt, or a shutdown or close routine. 3490 * 3491 * Side Effects: 3492 * None 3493 */ 3494 3495 static void dfx_xmt_flush( DFX_board_t *bp ) 3496 { 3497 u32 prod_cons; /* rcv/xmt consumer block longword */ 3498 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3499 u8 comp; /* local transmit completion index */ 3500 3501 /* Flush all outstanding transmit frames */ 3502 3503 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3504 { 3505 /* Get pointer to the transmit driver descriptor block information */ 3506 3507 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3508 3509 /* Return skb to operating system */ 3510 comp = bp->rcv_xmt_reg.index.xmt_comp; 3511 dma_unmap_single(bp->bus_dev, 3512 bp->descr_block_virt->xmt_data[comp].long_1, 3513 p_xmt_drv_descr->p_skb->len, 3514 DMA_TO_DEVICE); 3515 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3516 3517 /* Increment transmit error counter */ 3518 3519 bp->xmt_discards++; 3520 3521 /* 3522 * Move to start of next packet by updating completion index 3523 * 3524 * Here we assume that a transmit packet request is always 3525 * serviced by posting one fragment. We can therefore 3526 * simplify the completion code by incrementing the 3527 * completion index by one. This code will need to be 3528 * modified if this assumption changes. See comments 3529 * in dfx_xmt_queue_pkt for more details. 3530 */ 3531 3532 bp->rcv_xmt_reg.index.xmt_comp += 1; 3533 } 3534 3535 /* Update the transmit consumer index in the consumer block */ 3536 3537 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3538 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3539 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3540 } 3541 3542 /* 3543 * ================== 3544 * = dfx_unregister = 3545 * ================== 3546 * 3547 * Overview: 3548 * Shuts down an FDDI controller 3549 * 3550 * Returns: 3551 * Condition code 3552 * 3553 * Arguments: 3554 * bdev - pointer to device information 3555 * 3556 * Functional Description: 3557 * 3558 * Return Codes: 3559 * None 3560 * 3561 * Assumptions: 3562 * It compiles so it should work :-( (PCI cards do :-) 3563 * 3564 * Side Effects: 3565 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 3566 * freed. 3567 */ 3568 static void dfx_unregister(struct device *bdev) 3569 { 3570 struct net_device *dev = dev_get_drvdata(bdev); 3571 DFX_board_t *bp = netdev_priv(dev); 3572 int dfx_bus_pci = dev_is_pci(bdev); 3573 int dfx_bus_tc = DFX_BUS_TC(bdev); 3574 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 3575 resource_size_t bar_start = 0; /* pointer to port */ 3576 resource_size_t bar_len = 0; /* resource length */ 3577 int alloc_size; /* total buffer size used */ 3578 3579 unregister_netdev(dev); 3580 3581 alloc_size = sizeof(PI_DESCR_BLOCK) + 3582 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3583 #ifndef DYNAMIC_BUFFERS 3584 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3585 #endif 3586 sizeof(PI_CONSUMER_BLOCK) + 3587 (PI_ALIGN_K_DESC_BLK - 1); 3588 if (bp->kmalloced) 3589 dma_free_coherent(bdev, alloc_size, 3590 bp->kmalloced, bp->kmalloced_dma); 3591 3592 dfx_bus_uninit(dev); 3593 3594 dfx_get_bars(bdev, &bar_start, &bar_len); 3595 if (dfx_use_mmio) { 3596 iounmap(bp->base.mem); 3597 release_mem_region(bar_start, bar_len); 3598 } else 3599 release_region(bar_start, bar_len); 3600 3601 if (dfx_bus_pci) 3602 pci_disable_device(to_pci_dev(bdev)); 3603 3604 free_netdev(dev); 3605 } 3606 3607 3608 static int __maybe_unused dfx_dev_register(struct device *); 3609 static int __maybe_unused dfx_dev_unregister(struct device *); 3610 3611 #ifdef CONFIG_PCI 3612 static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *); 3613 static void dfx_pci_unregister(struct pci_dev *); 3614 3615 static DEFINE_PCI_DEVICE_TABLE(dfx_pci_table) = { 3616 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, 3617 { } 3618 }; 3619 MODULE_DEVICE_TABLE(pci, dfx_pci_table); 3620 3621 static struct pci_driver dfx_pci_driver = { 3622 .name = "defxx", 3623 .id_table = dfx_pci_table, 3624 .probe = dfx_pci_register, 3625 .remove = dfx_pci_unregister, 3626 }; 3627 3628 static int dfx_pci_register(struct pci_dev *pdev, 3629 const struct pci_device_id *ent) 3630 { 3631 return dfx_register(&pdev->dev); 3632 } 3633 3634 static void dfx_pci_unregister(struct pci_dev *pdev) 3635 { 3636 dfx_unregister(&pdev->dev); 3637 } 3638 #endif /* CONFIG_PCI */ 3639 3640 #ifdef CONFIG_EISA 3641 static struct eisa_device_id dfx_eisa_table[] = { 3642 { "DEC3001", DEFEA_PROD_ID_1 }, 3643 { "DEC3002", DEFEA_PROD_ID_2 }, 3644 { "DEC3003", DEFEA_PROD_ID_3 }, 3645 { "DEC3004", DEFEA_PROD_ID_4 }, 3646 { } 3647 }; 3648 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); 3649 3650 static struct eisa_driver dfx_eisa_driver = { 3651 .id_table = dfx_eisa_table, 3652 .driver = { 3653 .name = "defxx", 3654 .bus = &eisa_bus_type, 3655 .probe = dfx_dev_register, 3656 .remove = dfx_dev_unregister, 3657 }, 3658 }; 3659 #endif /* CONFIG_EISA */ 3660 3661 #ifdef CONFIG_TC 3662 static struct tc_device_id const dfx_tc_table[] = { 3663 { "DEC ", "PMAF-FA " }, 3664 { "DEC ", "PMAF-FD " }, 3665 { "DEC ", "PMAF-FS " }, 3666 { "DEC ", "PMAF-FU " }, 3667 { } 3668 }; 3669 MODULE_DEVICE_TABLE(tc, dfx_tc_table); 3670 3671 static struct tc_driver dfx_tc_driver = { 3672 .id_table = dfx_tc_table, 3673 .driver = { 3674 .name = "defxx", 3675 .bus = &tc_bus_type, 3676 .probe = dfx_dev_register, 3677 .remove = dfx_dev_unregister, 3678 }, 3679 }; 3680 #endif /* CONFIG_TC */ 3681 3682 static int __maybe_unused dfx_dev_register(struct device *dev) 3683 { 3684 int status; 3685 3686 status = dfx_register(dev); 3687 if (!status) 3688 get_device(dev); 3689 return status; 3690 } 3691 3692 static int __maybe_unused dfx_dev_unregister(struct device *dev) 3693 { 3694 put_device(dev); 3695 dfx_unregister(dev); 3696 return 0; 3697 } 3698 3699 3700 static int dfx_init(void) 3701 { 3702 int status; 3703 3704 status = pci_register_driver(&dfx_pci_driver); 3705 if (!status) 3706 status = eisa_driver_register(&dfx_eisa_driver); 3707 if (!status) 3708 status = tc_register_driver(&dfx_tc_driver); 3709 return status; 3710 } 3711 3712 static void dfx_cleanup(void) 3713 { 3714 tc_unregister_driver(&dfx_tc_driver); 3715 eisa_driver_unregister(&dfx_eisa_driver); 3716 pci_unregister_driver(&dfx_pci_driver); 3717 } 3718 3719 module_init(dfx_init); 3720 module_exit(dfx_cleanup); 3721 MODULE_AUTHOR("Lawrence V. Stefani"); 3722 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " 3723 DRV_VERSION " " DRV_RELDATE); 3724 MODULE_LICENSE("GPL"); 3725