1 /* 2 * Intel IXP4xx Ethernet driver for Linux 3 * 4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Ethernet port config (0x00 is not present on IXP42X): 11 * 12 * logical port 0x00 0x10 0x20 13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 14 * physical PortId 2 0 1 15 * TX queue 23 24 25 16 * RX-free queue 26 27 28 17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 18 * 19 * 20 * Queue entries: 21 * bits 0 -> 1 - NPE ID (RX and TX-done) 22 * bits 0 -> 2 - priority (TX, per 802.1D) 23 * bits 3 -> 4 - port ID (user-set?) 24 * bits 5 -> 31 - physical descriptor address 25 */ 26 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmapool.h> 30 #include <linux/etherdevice.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/ptp_classify.h> 37 #include <linux/slab.h> 38 #include <linux/module.h> 39 #include <mach/ixp46x_ts.h> 40 #include <mach/npe.h> 41 #include <mach/qmgr.h> 42 43 #define DEBUG_DESC 0 44 #define DEBUG_RX 0 45 #define DEBUG_TX 0 46 #define DEBUG_PKT_BYTES 0 47 #define DEBUG_MDIO 0 48 #define DEBUG_CLOSE 0 49 50 #define DRV_NAME "ixp4xx_eth" 51 52 #define MAX_NPES 3 53 54 #define RX_DESCS 64 /* also length of all RX queues */ 55 #define TX_DESCS 16 /* also length of all TX queues */ 56 #define TXDONE_QUEUE_LEN 64 /* dwords */ 57 58 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 59 #define REGS_SIZE 0x1000 60 #define MAX_MRU 1536 /* 0x600 */ 61 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 62 63 #define NAPI_WEIGHT 16 64 #define MDIO_INTERVAL (3 * HZ) 65 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 66 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 67 68 #define NPE_ID(port_id) ((port_id) >> 4) 69 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 70 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 71 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 72 #define TXDONE_QUEUE 31 73 74 #define PTP_SLAVE_MODE 1 75 #define PTP_MASTER_MODE 2 76 #define PORT2CHANNEL(p) NPE_ID(p->id) 77 78 /* TX Control Registers */ 79 #define TX_CNTRL0_TX_EN 0x01 80 #define TX_CNTRL0_HALFDUPLEX 0x02 81 #define TX_CNTRL0_RETRY 0x04 82 #define TX_CNTRL0_PAD_EN 0x08 83 #define TX_CNTRL0_APPEND_FCS 0x10 84 #define TX_CNTRL0_2DEFER 0x20 85 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 86 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 87 88 /* RX Control Registers */ 89 #define RX_CNTRL0_RX_EN 0x01 90 #define RX_CNTRL0_PADSTRIP_EN 0x02 91 #define RX_CNTRL0_SEND_FCS 0x04 92 #define RX_CNTRL0_PAUSE_EN 0x08 93 #define RX_CNTRL0_LOOP_EN 0x10 94 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 95 #define RX_CNTRL0_RX_RUNT_EN 0x40 96 #define RX_CNTRL0_BCAST_DIS 0x80 97 #define RX_CNTRL1_DEFER_EN 0x01 98 99 /* Core Control Register */ 100 #define CORE_RESET 0x01 101 #define CORE_RX_FIFO_FLUSH 0x02 102 #define CORE_TX_FIFO_FLUSH 0x04 103 #define CORE_SEND_JAM 0x08 104 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 105 106 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 107 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 108 TX_CNTRL0_2DEFER) 109 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 110 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 111 112 113 /* NPE message codes */ 114 #define NPE_GETSTATUS 0x00 115 #define NPE_EDB_SETPORTADDRESS 0x01 116 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 117 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 118 #define NPE_GETSTATS 0x04 119 #define NPE_RESETSTATS 0x05 120 #define NPE_SETMAXFRAMELENGTHS 0x06 121 #define NPE_VLAN_SETRXTAGMODE 0x07 122 #define NPE_VLAN_SETDEFAULTRXVID 0x08 123 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 124 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 125 #define NPE_VLAN_SETRXQOSENTRY 0x0B 126 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 127 #define NPE_STP_SETBLOCKINGSTATE 0x0D 128 #define NPE_FW_SETFIREWALLMODE 0x0E 129 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 130 #define NPE_PC_SETAPMACTABLE 0x11 131 #define NPE_SETLOOPBACK_MODE 0x12 132 #define NPE_PC_SETBSSIDTABLE 0x13 133 #define NPE_ADDRESS_FILTER_CONFIG 0x14 134 #define NPE_APPENDFCSCONFIG 0x15 135 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 136 #define NPE_MAC_RECOVERY_START 0x17 137 138 139 #ifdef __ARMEB__ 140 typedef struct sk_buff buffer_t; 141 #define free_buffer dev_kfree_skb 142 #define free_buffer_irq dev_kfree_skb_irq 143 #else 144 typedef void buffer_t; 145 #define free_buffer kfree 146 #define free_buffer_irq kfree 147 #endif 148 149 struct eth_regs { 150 u32 tx_control[2], __res1[2]; /* 000 */ 151 u32 rx_control[2], __res2[2]; /* 010 */ 152 u32 random_seed, __res3[3]; /* 020 */ 153 u32 partial_empty_threshold, __res4; /* 030 */ 154 u32 partial_full_threshold, __res5; /* 038 */ 155 u32 tx_start_bytes, __res6[3]; /* 040 */ 156 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 157 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 158 u32 slot_time, __res9[3]; /* 070 */ 159 u32 mdio_command[4]; /* 080 */ 160 u32 mdio_status[4]; /* 090 */ 161 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 162 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 163 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 164 u32 hw_addr[6], __res13[61]; /* 0F0 */ 165 u32 core_control; /* 1FC */ 166 }; 167 168 struct port { 169 struct resource *mem_res; 170 struct eth_regs __iomem *regs; 171 struct npe *npe; 172 struct net_device *netdev; 173 struct napi_struct napi; 174 struct phy_device *phydev; 175 struct eth_plat_info *plat; 176 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 177 struct desc *desc_tab; /* coherent */ 178 u32 desc_tab_phys; 179 int id; /* logical port ID */ 180 int speed, duplex; 181 u8 firmware[4]; 182 int hwts_tx_en; 183 int hwts_rx_en; 184 }; 185 186 /* NPE message structure */ 187 struct msg { 188 #ifdef __ARMEB__ 189 u8 cmd, eth_id, byte2, byte3; 190 u8 byte4, byte5, byte6, byte7; 191 #else 192 u8 byte3, byte2, eth_id, cmd; 193 u8 byte7, byte6, byte5, byte4; 194 #endif 195 }; 196 197 /* Ethernet packet descriptor */ 198 struct desc { 199 u32 next; /* pointer to next buffer, unused */ 200 201 #ifdef __ARMEB__ 202 u16 buf_len; /* buffer length */ 203 u16 pkt_len; /* packet length */ 204 u32 data; /* pointer to data buffer in RAM */ 205 u8 dest_id; 206 u8 src_id; 207 u16 flags; 208 u8 qos; 209 u8 padlen; 210 u16 vlan_tci; 211 #else 212 u16 pkt_len; /* packet length */ 213 u16 buf_len; /* buffer length */ 214 u32 data; /* pointer to data buffer in RAM */ 215 u16 flags; 216 u8 src_id; 217 u8 dest_id; 218 u16 vlan_tci; 219 u8 padlen; 220 u8 qos; 221 #endif 222 223 #ifdef __ARMEB__ 224 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 225 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 226 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 227 #else 228 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 229 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 230 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 231 #endif 232 }; 233 234 235 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 236 (n) * sizeof(struct desc)) 237 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 238 239 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 240 ((n) + RX_DESCS) * sizeof(struct desc)) 241 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 242 243 #ifndef __ARMEB__ 244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 245 { 246 int i; 247 for (i = 0; i < cnt; i++) 248 dest[i] = swab32(src[i]); 249 } 250 #endif 251 252 static spinlock_t mdio_lock; 253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 254 static struct mii_bus *mdio_bus; 255 static int ports_open; 256 static struct port *npe_port_tab[MAX_NPES]; 257 static struct dma_pool *dma_pool; 258 259 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 260 { 261 u8 *data = skb->data; 262 unsigned int offset; 263 u16 *hi, *id; 264 u32 lo; 265 266 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 267 return 0; 268 269 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 270 271 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 272 return 0; 273 274 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 275 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 276 277 memcpy(&lo, &hi[1], sizeof(lo)); 278 279 return (uid_hi == ntohs(*hi) && 280 uid_lo == ntohl(lo) && 281 seqid == ntohs(*id)); 282 } 283 284 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 285 { 286 struct skb_shared_hwtstamps *shhwtstamps; 287 struct ixp46x_ts_regs *regs; 288 u64 ns; 289 u32 ch, hi, lo, val; 290 u16 uid, seq; 291 292 if (!port->hwts_rx_en) 293 return; 294 295 ch = PORT2CHANNEL(port); 296 297 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 298 299 val = __raw_readl(®s->channel[ch].ch_event); 300 301 if (!(val & RX_SNAPSHOT_LOCKED)) 302 return; 303 304 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 305 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 306 307 uid = hi & 0xffff; 308 seq = (hi >> 16) & 0xffff; 309 310 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 311 goto out; 312 313 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 314 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 315 ns = ((u64) hi) << 32; 316 ns |= lo; 317 ns <<= TICKS_NS_SHIFT; 318 319 shhwtstamps = skb_hwtstamps(skb); 320 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 321 shhwtstamps->hwtstamp = ns_to_ktime(ns); 322 out: 323 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 324 } 325 326 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 327 { 328 struct skb_shared_hwtstamps shhwtstamps; 329 struct ixp46x_ts_regs *regs; 330 struct skb_shared_info *shtx; 331 u64 ns; 332 u32 ch, cnt, hi, lo, val; 333 334 shtx = skb_shinfo(skb); 335 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 336 shtx->tx_flags |= SKBTX_IN_PROGRESS; 337 else 338 return; 339 340 ch = PORT2CHANNEL(port); 341 342 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 343 344 /* 345 * This really stinks, but we have to poll for the Tx time stamp. 346 * Usually, the time stamp is ready after 4 to 6 microseconds. 347 */ 348 for (cnt = 0; cnt < 100; cnt++) { 349 val = __raw_readl(®s->channel[ch].ch_event); 350 if (val & TX_SNAPSHOT_LOCKED) 351 break; 352 udelay(1); 353 } 354 if (!(val & TX_SNAPSHOT_LOCKED)) { 355 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 356 return; 357 } 358 359 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 360 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 361 ns = ((u64) hi) << 32; 362 ns |= lo; 363 ns <<= TICKS_NS_SHIFT; 364 365 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 366 shhwtstamps.hwtstamp = ns_to_ktime(ns); 367 skb_tstamp_tx(skb, &shhwtstamps); 368 369 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 370 } 371 372 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 373 { 374 struct hwtstamp_config cfg; 375 struct ixp46x_ts_regs *regs; 376 struct port *port = netdev_priv(netdev); 377 int ch; 378 379 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 380 return -EFAULT; 381 382 if (cfg.flags) /* reserved for future extensions */ 383 return -EINVAL; 384 385 ch = PORT2CHANNEL(port); 386 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 387 388 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 389 return -ERANGE; 390 391 switch (cfg.rx_filter) { 392 case HWTSTAMP_FILTER_NONE: 393 port->hwts_rx_en = 0; 394 break; 395 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 396 port->hwts_rx_en = PTP_SLAVE_MODE; 397 __raw_writel(0, ®s->channel[ch].ch_control); 398 break; 399 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 400 port->hwts_rx_en = PTP_MASTER_MODE; 401 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 402 break; 403 default: 404 return -ERANGE; 405 } 406 407 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 408 409 /* Clear out any old time stamps. */ 410 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 411 ®s->channel[ch].ch_event); 412 413 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 414 } 415 416 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 417 { 418 struct hwtstamp_config cfg; 419 struct port *port = netdev_priv(netdev); 420 421 cfg.flags = 0; 422 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 423 424 switch (port->hwts_rx_en) { 425 case 0: 426 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 427 break; 428 case PTP_SLAVE_MODE: 429 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 430 break; 431 case PTP_MASTER_MODE: 432 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 433 break; 434 default: 435 WARN_ON_ONCE(1); 436 return -ERANGE; 437 } 438 439 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 440 } 441 442 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 443 int write, u16 cmd) 444 { 445 int cycles = 0; 446 447 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 448 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 449 return -1; 450 } 451 452 if (write) { 453 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 454 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 455 } 456 __raw_writel(((phy_id << 5) | location) & 0xFF, 457 &mdio_regs->mdio_command[2]); 458 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 459 &mdio_regs->mdio_command[3]); 460 461 while ((cycles < MAX_MDIO_RETRIES) && 462 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 463 udelay(1); 464 cycles++; 465 } 466 467 if (cycles == MAX_MDIO_RETRIES) { 468 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 469 phy_id); 470 return -1; 471 } 472 473 #if DEBUG_MDIO 474 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 475 phy_id, write ? "write" : "read", cycles); 476 #endif 477 478 if (write) 479 return 0; 480 481 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 482 #if DEBUG_MDIO 483 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 484 phy_id); 485 #endif 486 return 0xFFFF; /* don't return error */ 487 } 488 489 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 490 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 491 } 492 493 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 494 { 495 unsigned long flags; 496 int ret; 497 498 spin_lock_irqsave(&mdio_lock, flags); 499 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 500 spin_unlock_irqrestore(&mdio_lock, flags); 501 #if DEBUG_MDIO 502 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 503 phy_id, location, ret); 504 #endif 505 return ret; 506 } 507 508 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 509 u16 val) 510 { 511 unsigned long flags; 512 int ret; 513 514 spin_lock_irqsave(&mdio_lock, flags); 515 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 516 spin_unlock_irqrestore(&mdio_lock, flags); 517 #if DEBUG_MDIO 518 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 519 bus->name, phy_id, location, val, ret); 520 #endif 521 return ret; 522 } 523 524 static int ixp4xx_mdio_register(void) 525 { 526 int err; 527 528 if (!(mdio_bus = mdiobus_alloc())) 529 return -ENOMEM; 530 531 if (cpu_is_ixp43x()) { 532 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ 533 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) 534 return -ENODEV; 535 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; 536 } else { 537 /* All MII PHY accesses use NPE-B Ethernet registers */ 538 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) 539 return -ENODEV; 540 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; 541 } 542 543 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 544 spin_lock_init(&mdio_lock); 545 mdio_bus->name = "IXP4xx MII Bus"; 546 mdio_bus->read = &ixp4xx_mdio_read; 547 mdio_bus->write = &ixp4xx_mdio_write; 548 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 549 550 if ((err = mdiobus_register(mdio_bus))) 551 mdiobus_free(mdio_bus); 552 return err; 553 } 554 555 static void ixp4xx_mdio_remove(void) 556 { 557 mdiobus_unregister(mdio_bus); 558 mdiobus_free(mdio_bus); 559 } 560 561 562 static void ixp4xx_adjust_link(struct net_device *dev) 563 { 564 struct port *port = netdev_priv(dev); 565 struct phy_device *phydev = port->phydev; 566 567 if (!phydev->link) { 568 if (port->speed) { 569 port->speed = 0; 570 printk(KERN_INFO "%s: link down\n", dev->name); 571 } 572 return; 573 } 574 575 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 576 return; 577 578 port->speed = phydev->speed; 579 port->duplex = phydev->duplex; 580 581 if (port->duplex) 582 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 583 &port->regs->tx_control[0]); 584 else 585 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 586 &port->regs->tx_control[0]); 587 588 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", 589 dev->name, port->speed, port->duplex ? "full" : "half"); 590 } 591 592 593 static inline void debug_pkt(struct net_device *dev, const char *func, 594 u8 *data, int len) 595 { 596 #if DEBUG_PKT_BYTES 597 int i; 598 599 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); 600 for (i = 0; i < len; i++) { 601 if (i >= DEBUG_PKT_BYTES) 602 break; 603 printk("%s%02X", 604 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 605 data[i]); 606 } 607 printk("\n"); 608 #endif 609 } 610 611 612 static inline void debug_desc(u32 phys, struct desc *desc) 613 { 614 #if DEBUG_DESC 615 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 616 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 617 phys, desc->next, desc->buf_len, desc->pkt_len, 618 desc->data, desc->dest_id, desc->src_id, desc->flags, 619 desc->qos, desc->padlen, desc->vlan_tci, 620 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 621 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 622 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 623 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 624 #endif 625 } 626 627 static inline int queue_get_desc(unsigned int queue, struct port *port, 628 int is_tx) 629 { 630 u32 phys, tab_phys, n_desc; 631 struct desc *tab; 632 633 if (!(phys = qmgr_get_entry(queue))) 634 return -1; 635 636 phys &= ~0x1F; /* mask out non-address bits */ 637 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 638 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 639 n_desc = (phys - tab_phys) / sizeof(struct desc); 640 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 641 debug_desc(phys, &tab[n_desc]); 642 BUG_ON(tab[n_desc].next); 643 return n_desc; 644 } 645 646 static inline void queue_put_desc(unsigned int queue, u32 phys, 647 struct desc *desc) 648 { 649 debug_desc(phys, desc); 650 BUG_ON(phys & 0x1F); 651 qmgr_put_entry(queue, phys); 652 /* Don't check for queue overflow here, we've allocated sufficient 653 length and queues >= 32 don't support this check anyway. */ 654 } 655 656 657 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 658 { 659 #ifdef __ARMEB__ 660 dma_unmap_single(&port->netdev->dev, desc->data, 661 desc->buf_len, DMA_TO_DEVICE); 662 #else 663 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 664 ALIGN((desc->data & 3) + desc->buf_len, 4), 665 DMA_TO_DEVICE); 666 #endif 667 } 668 669 670 static void eth_rx_irq(void *pdev) 671 { 672 struct net_device *dev = pdev; 673 struct port *port = netdev_priv(dev); 674 675 #if DEBUG_RX 676 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 677 #endif 678 qmgr_disable_irq(port->plat->rxq); 679 napi_schedule(&port->napi); 680 } 681 682 static int eth_poll(struct napi_struct *napi, int budget) 683 { 684 struct port *port = container_of(napi, struct port, napi); 685 struct net_device *dev = port->netdev; 686 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 687 int received = 0; 688 689 #if DEBUG_RX 690 printk(KERN_DEBUG "%s: eth_poll\n", dev->name); 691 #endif 692 693 while (received < budget) { 694 struct sk_buff *skb; 695 struct desc *desc; 696 int n; 697 #ifdef __ARMEB__ 698 struct sk_buff *temp; 699 u32 phys; 700 #endif 701 702 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 703 #if DEBUG_RX 704 printk(KERN_DEBUG "%s: eth_poll napi_complete\n", 705 dev->name); 706 #endif 707 napi_complete(napi); 708 qmgr_enable_irq(rxq); 709 if (!qmgr_stat_below_low_watermark(rxq) && 710 napi_reschedule(napi)) { /* not empty again */ 711 #if DEBUG_RX 712 printk(KERN_DEBUG "%s: eth_poll" 713 " napi_reschedule successed\n", 714 dev->name); 715 #endif 716 qmgr_disable_irq(rxq); 717 continue; 718 } 719 #if DEBUG_RX 720 printk(KERN_DEBUG "%s: eth_poll all done\n", 721 dev->name); 722 #endif 723 return received; /* all work done */ 724 } 725 726 desc = rx_desc_ptr(port, n); 727 728 #ifdef __ARMEB__ 729 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 730 phys = dma_map_single(&dev->dev, skb->data, 731 RX_BUFF_SIZE, DMA_FROM_DEVICE); 732 if (dma_mapping_error(&dev->dev, phys)) { 733 dev_kfree_skb(skb); 734 skb = NULL; 735 } 736 } 737 #else 738 skb = netdev_alloc_skb(dev, 739 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 740 #endif 741 742 if (!skb) { 743 dev->stats.rx_dropped++; 744 /* put the desc back on RX-ready queue */ 745 desc->buf_len = MAX_MRU; 746 desc->pkt_len = 0; 747 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 748 continue; 749 } 750 751 /* process received frame */ 752 #ifdef __ARMEB__ 753 temp = skb; 754 skb = port->rx_buff_tab[n]; 755 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 756 RX_BUFF_SIZE, DMA_FROM_DEVICE); 757 #else 758 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 759 RX_BUFF_SIZE, DMA_FROM_DEVICE); 760 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 761 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 762 #endif 763 skb_reserve(skb, NET_IP_ALIGN); 764 skb_put(skb, desc->pkt_len); 765 766 debug_pkt(dev, "eth_poll", skb->data, skb->len); 767 768 ixp_rx_timestamp(port, skb); 769 skb->protocol = eth_type_trans(skb, dev); 770 dev->stats.rx_packets++; 771 dev->stats.rx_bytes += skb->len; 772 netif_receive_skb(skb); 773 774 /* put the new buffer on RX-free queue */ 775 #ifdef __ARMEB__ 776 port->rx_buff_tab[n] = temp; 777 desc->data = phys + NET_IP_ALIGN; 778 #endif 779 desc->buf_len = MAX_MRU; 780 desc->pkt_len = 0; 781 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 782 received++; 783 } 784 785 #if DEBUG_RX 786 printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); 787 #endif 788 return received; /* not all work done */ 789 } 790 791 792 static void eth_txdone_irq(void *unused) 793 { 794 u32 phys; 795 796 #if DEBUG_TX 797 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 798 #endif 799 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 800 u32 npe_id, n_desc; 801 struct port *port; 802 struct desc *desc; 803 int start; 804 805 npe_id = phys & 3; 806 BUG_ON(npe_id >= MAX_NPES); 807 port = npe_port_tab[npe_id]; 808 BUG_ON(!port); 809 phys &= ~0x1F; /* mask out non-address bits */ 810 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 811 BUG_ON(n_desc >= TX_DESCS); 812 desc = tx_desc_ptr(port, n_desc); 813 debug_desc(phys, desc); 814 815 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 816 port->netdev->stats.tx_packets++; 817 port->netdev->stats.tx_bytes += desc->pkt_len; 818 819 dma_unmap_tx(port, desc); 820 #if DEBUG_TX 821 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 822 port->netdev->name, port->tx_buff_tab[n_desc]); 823 #endif 824 free_buffer_irq(port->tx_buff_tab[n_desc]); 825 port->tx_buff_tab[n_desc] = NULL; 826 } 827 828 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 829 queue_put_desc(port->plat->txreadyq, phys, desc); 830 if (start) { /* TX-ready queue was empty */ 831 #if DEBUG_TX 832 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 833 port->netdev->name); 834 #endif 835 netif_wake_queue(port->netdev); 836 } 837 } 838 } 839 840 static int eth_xmit(struct sk_buff *skb, struct net_device *dev) 841 { 842 struct port *port = netdev_priv(dev); 843 unsigned int txreadyq = port->plat->txreadyq; 844 int len, offset, bytes, n; 845 void *mem; 846 u32 phys; 847 struct desc *desc; 848 849 #if DEBUG_TX 850 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); 851 #endif 852 853 if (unlikely(skb->len > MAX_MRU)) { 854 dev_kfree_skb(skb); 855 dev->stats.tx_errors++; 856 return NETDEV_TX_OK; 857 } 858 859 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 860 861 len = skb->len; 862 #ifdef __ARMEB__ 863 offset = 0; /* no need to keep alignment */ 864 bytes = len; 865 mem = skb->data; 866 #else 867 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 868 bytes = ALIGN(offset + len, 4); 869 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 870 dev_kfree_skb(skb); 871 dev->stats.tx_dropped++; 872 return NETDEV_TX_OK; 873 } 874 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); 875 #endif 876 877 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 878 if (dma_mapping_error(&dev->dev, phys)) { 879 dev_kfree_skb(skb); 880 #ifndef __ARMEB__ 881 kfree(mem); 882 #endif 883 dev->stats.tx_dropped++; 884 return NETDEV_TX_OK; 885 } 886 887 n = queue_get_desc(txreadyq, port, 1); 888 BUG_ON(n < 0); 889 desc = tx_desc_ptr(port, n); 890 891 #ifdef __ARMEB__ 892 port->tx_buff_tab[n] = skb; 893 #else 894 port->tx_buff_tab[n] = mem; 895 #endif 896 desc->data = phys + offset; 897 desc->buf_len = desc->pkt_len = len; 898 899 /* NPE firmware pads short frames with zeros internally */ 900 wmb(); 901 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 902 903 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 904 #if DEBUG_TX 905 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); 906 #endif 907 netif_stop_queue(dev); 908 /* we could miss TX ready interrupt */ 909 /* really empty in fact */ 910 if (!qmgr_stat_below_low_watermark(txreadyq)) { 911 #if DEBUG_TX 912 printk(KERN_DEBUG "%s: eth_xmit ready again\n", 913 dev->name); 914 #endif 915 netif_wake_queue(dev); 916 } 917 } 918 919 #if DEBUG_TX 920 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); 921 #endif 922 923 ixp_tx_timestamp(port, skb); 924 skb_tx_timestamp(skb); 925 926 #ifndef __ARMEB__ 927 dev_kfree_skb(skb); 928 #endif 929 return NETDEV_TX_OK; 930 } 931 932 933 static void eth_set_mcast_list(struct net_device *dev) 934 { 935 struct port *port = netdev_priv(dev); 936 struct netdev_hw_addr *ha; 937 u8 diffs[ETH_ALEN], *addr; 938 int i; 939 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 940 941 if (dev->flags & IFF_ALLMULTI) { 942 for (i = 0; i < ETH_ALEN; i++) { 943 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 944 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 945 } 946 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 947 &port->regs->rx_control[0]); 948 return; 949 } 950 951 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 952 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 953 &port->regs->rx_control[0]); 954 return; 955 } 956 957 memset(diffs, 0, ETH_ALEN); 958 959 addr = NULL; 960 netdev_for_each_mc_addr(ha, dev) { 961 if (!addr) 962 addr = ha->addr; /* first MAC address */ 963 for (i = 0; i < ETH_ALEN; i++) 964 diffs[i] |= addr[i] ^ ha->addr[i]; 965 } 966 967 for (i = 0; i < ETH_ALEN; i++) { 968 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 969 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 970 } 971 972 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 973 &port->regs->rx_control[0]); 974 } 975 976 977 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 978 { 979 struct port *port = netdev_priv(dev); 980 981 if (!netif_running(dev)) 982 return -EINVAL; 983 984 if (cpu_is_ixp46x()) { 985 if (cmd == SIOCSHWTSTAMP) 986 return hwtstamp_set(dev, req); 987 if (cmd == SIOCGHWTSTAMP) 988 return hwtstamp_get(dev, req); 989 } 990 991 return phy_mii_ioctl(port->phydev, req, cmd); 992 } 993 994 /* ethtool support */ 995 996 static void ixp4xx_get_drvinfo(struct net_device *dev, 997 struct ethtool_drvinfo *info) 998 { 999 struct port *port = netdev_priv(dev); 1000 1001 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 1002 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 1003 port->firmware[0], port->firmware[1], 1004 port->firmware[2], port->firmware[3]); 1005 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 1006 } 1007 1008 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1009 { 1010 struct port *port = netdev_priv(dev); 1011 return phy_ethtool_gset(port->phydev, cmd); 1012 } 1013 1014 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1015 { 1016 struct port *port = netdev_priv(dev); 1017 return phy_ethtool_sset(port->phydev, cmd); 1018 } 1019 1020 static int ixp4xx_nway_reset(struct net_device *dev) 1021 { 1022 struct port *port = netdev_priv(dev); 1023 return phy_start_aneg(port->phydev); 1024 } 1025 1026 int ixp46x_phc_index = -1; 1027 EXPORT_SYMBOL_GPL(ixp46x_phc_index); 1028 1029 static int ixp4xx_get_ts_info(struct net_device *dev, 1030 struct ethtool_ts_info *info) 1031 { 1032 if (!cpu_is_ixp46x()) { 1033 info->so_timestamping = 1034 SOF_TIMESTAMPING_TX_SOFTWARE | 1035 SOF_TIMESTAMPING_RX_SOFTWARE | 1036 SOF_TIMESTAMPING_SOFTWARE; 1037 info->phc_index = -1; 1038 return 0; 1039 } 1040 info->so_timestamping = 1041 SOF_TIMESTAMPING_TX_HARDWARE | 1042 SOF_TIMESTAMPING_RX_HARDWARE | 1043 SOF_TIMESTAMPING_RAW_HARDWARE; 1044 info->phc_index = ixp46x_phc_index; 1045 info->tx_types = 1046 (1 << HWTSTAMP_TX_OFF) | 1047 (1 << HWTSTAMP_TX_ON); 1048 info->rx_filters = 1049 (1 << HWTSTAMP_FILTER_NONE) | 1050 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1051 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1052 return 0; 1053 } 1054 1055 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1056 .get_drvinfo = ixp4xx_get_drvinfo, 1057 .get_settings = ixp4xx_get_settings, 1058 .set_settings = ixp4xx_set_settings, 1059 .nway_reset = ixp4xx_nway_reset, 1060 .get_link = ethtool_op_get_link, 1061 .get_ts_info = ixp4xx_get_ts_info, 1062 }; 1063 1064 1065 static int request_queues(struct port *port) 1066 { 1067 int err; 1068 1069 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1070 "%s:RX-free", port->netdev->name); 1071 if (err) 1072 return err; 1073 1074 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1075 "%s:RX", port->netdev->name); 1076 if (err) 1077 goto rel_rxfree; 1078 1079 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1080 "%s:TX", port->netdev->name); 1081 if (err) 1082 goto rel_rx; 1083 1084 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1085 "%s:TX-ready", port->netdev->name); 1086 if (err) 1087 goto rel_tx; 1088 1089 /* TX-done queue handles skbs sent out by the NPEs */ 1090 if (!ports_open) { 1091 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1092 "%s:TX-done", DRV_NAME); 1093 if (err) 1094 goto rel_txready; 1095 } 1096 return 0; 1097 1098 rel_txready: 1099 qmgr_release_queue(port->plat->txreadyq); 1100 rel_tx: 1101 qmgr_release_queue(TX_QUEUE(port->id)); 1102 rel_rx: 1103 qmgr_release_queue(port->plat->rxq); 1104 rel_rxfree: 1105 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1106 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1107 port->netdev->name); 1108 return err; 1109 } 1110 1111 static void release_queues(struct port *port) 1112 { 1113 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1114 qmgr_release_queue(port->plat->rxq); 1115 qmgr_release_queue(TX_QUEUE(port->id)); 1116 qmgr_release_queue(port->plat->txreadyq); 1117 1118 if (!ports_open) 1119 qmgr_release_queue(TXDONE_QUEUE); 1120 } 1121 1122 static int init_queues(struct port *port) 1123 { 1124 int i; 1125 1126 if (!ports_open) { 1127 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1128 POOL_ALLOC_SIZE, 32, 0); 1129 if (!dma_pool) 1130 return -ENOMEM; 1131 } 1132 1133 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, 1134 &port->desc_tab_phys))) 1135 return -ENOMEM; 1136 memset(port->desc_tab, 0, POOL_ALLOC_SIZE); 1137 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1138 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1139 1140 /* Setup RX buffers */ 1141 for (i = 0; i < RX_DESCS; i++) { 1142 struct desc *desc = rx_desc_ptr(port, i); 1143 buffer_t *buff; /* skb or kmalloc()ated memory */ 1144 void *data; 1145 #ifdef __ARMEB__ 1146 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1147 return -ENOMEM; 1148 data = buff->data; 1149 #else 1150 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1151 return -ENOMEM; 1152 data = buff; 1153 #endif 1154 desc->buf_len = MAX_MRU; 1155 desc->data = dma_map_single(&port->netdev->dev, data, 1156 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1157 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1158 free_buffer(buff); 1159 return -EIO; 1160 } 1161 desc->data += NET_IP_ALIGN; 1162 port->rx_buff_tab[i] = buff; 1163 } 1164 1165 return 0; 1166 } 1167 1168 static void destroy_queues(struct port *port) 1169 { 1170 int i; 1171 1172 if (port->desc_tab) { 1173 for (i = 0; i < RX_DESCS; i++) { 1174 struct desc *desc = rx_desc_ptr(port, i); 1175 buffer_t *buff = port->rx_buff_tab[i]; 1176 if (buff) { 1177 dma_unmap_single(&port->netdev->dev, 1178 desc->data - NET_IP_ALIGN, 1179 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1180 free_buffer(buff); 1181 } 1182 } 1183 for (i = 0; i < TX_DESCS; i++) { 1184 struct desc *desc = tx_desc_ptr(port, i); 1185 buffer_t *buff = port->tx_buff_tab[i]; 1186 if (buff) { 1187 dma_unmap_tx(port, desc); 1188 free_buffer(buff); 1189 } 1190 } 1191 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1192 port->desc_tab = NULL; 1193 } 1194 1195 if (!ports_open && dma_pool) { 1196 dma_pool_destroy(dma_pool); 1197 dma_pool = NULL; 1198 } 1199 } 1200 1201 static int eth_open(struct net_device *dev) 1202 { 1203 struct port *port = netdev_priv(dev); 1204 struct npe *npe = port->npe; 1205 struct msg msg; 1206 int i, err; 1207 1208 if (!npe_running(npe)) { 1209 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1210 if (err) 1211 return err; 1212 1213 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1214 printk(KERN_ERR "%s: %s not responding\n", dev->name, 1215 npe_name(npe)); 1216 return -EIO; 1217 } 1218 port->firmware[0] = msg.byte4; 1219 port->firmware[1] = msg.byte5; 1220 port->firmware[2] = msg.byte6; 1221 port->firmware[3] = msg.byte7; 1222 } 1223 1224 memset(&msg, 0, sizeof(msg)); 1225 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1226 msg.eth_id = port->id; 1227 msg.byte5 = port->plat->rxq | 0x80; 1228 msg.byte7 = port->plat->rxq << 4; 1229 for (i = 0; i < 8; i++) { 1230 msg.byte3 = i; 1231 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1232 return -EIO; 1233 } 1234 1235 msg.cmd = NPE_EDB_SETPORTADDRESS; 1236 msg.eth_id = PHYSICAL_ID(port->id); 1237 msg.byte2 = dev->dev_addr[0]; 1238 msg.byte3 = dev->dev_addr[1]; 1239 msg.byte4 = dev->dev_addr[2]; 1240 msg.byte5 = dev->dev_addr[3]; 1241 msg.byte6 = dev->dev_addr[4]; 1242 msg.byte7 = dev->dev_addr[5]; 1243 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1244 return -EIO; 1245 1246 memset(&msg, 0, sizeof(msg)); 1247 msg.cmd = NPE_FW_SETFIREWALLMODE; 1248 msg.eth_id = port->id; 1249 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1250 return -EIO; 1251 1252 if ((err = request_queues(port)) != 0) 1253 return err; 1254 1255 if ((err = init_queues(port)) != 0) { 1256 destroy_queues(port); 1257 release_queues(port); 1258 return err; 1259 } 1260 1261 port->speed = 0; /* force "link up" message */ 1262 phy_start(port->phydev); 1263 1264 for (i = 0; i < ETH_ALEN; i++) 1265 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1266 __raw_writel(0x08, &port->regs->random_seed); 1267 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1268 __raw_writel(0x30, &port->regs->partial_full_threshold); 1269 __raw_writel(0x08, &port->regs->tx_start_bytes); 1270 __raw_writel(0x15, &port->regs->tx_deferral); 1271 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1272 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1273 __raw_writel(0x80, &port->regs->slot_time); 1274 __raw_writel(0x01, &port->regs->int_clock_threshold); 1275 1276 /* Populate queues with buffers, no failure after this point */ 1277 for (i = 0; i < TX_DESCS; i++) 1278 queue_put_desc(port->plat->txreadyq, 1279 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1280 1281 for (i = 0; i < RX_DESCS; i++) 1282 queue_put_desc(RXFREE_QUEUE(port->id), 1283 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1284 1285 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1286 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1287 __raw_writel(0, &port->regs->rx_control[1]); 1288 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1289 1290 napi_enable(&port->napi); 1291 eth_set_mcast_list(dev); 1292 netif_start_queue(dev); 1293 1294 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1295 eth_rx_irq, dev); 1296 if (!ports_open) { 1297 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1298 eth_txdone_irq, NULL); 1299 qmgr_enable_irq(TXDONE_QUEUE); 1300 } 1301 ports_open++; 1302 /* we may already have RX data, enables IRQ */ 1303 napi_schedule(&port->napi); 1304 return 0; 1305 } 1306 1307 static int eth_close(struct net_device *dev) 1308 { 1309 struct port *port = netdev_priv(dev); 1310 struct msg msg; 1311 int buffs = RX_DESCS; /* allocated RX buffers */ 1312 int i; 1313 1314 ports_open--; 1315 qmgr_disable_irq(port->plat->rxq); 1316 napi_disable(&port->napi); 1317 netif_stop_queue(dev); 1318 1319 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1320 buffs--; 1321 1322 memset(&msg, 0, sizeof(msg)); 1323 msg.cmd = NPE_SETLOOPBACK_MODE; 1324 msg.eth_id = port->id; 1325 msg.byte3 = 1; 1326 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1327 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); 1328 1329 i = 0; 1330 do { /* drain RX buffers */ 1331 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1332 buffs--; 1333 if (!buffs) 1334 break; 1335 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1336 /* we have to inject some packet */ 1337 struct desc *desc; 1338 u32 phys; 1339 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1340 BUG_ON(n < 0); 1341 desc = tx_desc_ptr(port, n); 1342 phys = tx_desc_phys(port, n); 1343 desc->buf_len = desc->pkt_len = 1; 1344 wmb(); 1345 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1346 } 1347 udelay(1); 1348 } while (++i < MAX_CLOSE_WAIT); 1349 1350 if (buffs) 1351 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" 1352 " left in NPE\n", dev->name, buffs); 1353 #if DEBUG_CLOSE 1354 if (!buffs) 1355 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); 1356 #endif 1357 1358 buffs = TX_DESCS; 1359 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1360 buffs--; /* cancel TX */ 1361 1362 i = 0; 1363 do { 1364 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1365 buffs--; 1366 if (!buffs) 1367 break; 1368 } while (++i < MAX_CLOSE_WAIT); 1369 1370 if (buffs) 1371 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " 1372 "left in NPE\n", dev->name, buffs); 1373 #if DEBUG_CLOSE 1374 if (!buffs) 1375 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); 1376 #endif 1377 1378 msg.byte3 = 0; 1379 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1380 printk(KERN_CRIT "%s: unable to disable loopback\n", 1381 dev->name); 1382 1383 phy_stop(port->phydev); 1384 1385 if (!ports_open) 1386 qmgr_disable_irq(TXDONE_QUEUE); 1387 destroy_queues(port); 1388 release_queues(port); 1389 return 0; 1390 } 1391 1392 static const struct net_device_ops ixp4xx_netdev_ops = { 1393 .ndo_open = eth_open, 1394 .ndo_stop = eth_close, 1395 .ndo_start_xmit = eth_xmit, 1396 .ndo_set_rx_mode = eth_set_mcast_list, 1397 .ndo_do_ioctl = eth_ioctl, 1398 .ndo_change_mtu = eth_change_mtu, 1399 .ndo_set_mac_address = eth_mac_addr, 1400 .ndo_validate_addr = eth_validate_addr, 1401 }; 1402 1403 static int eth_init_one(struct platform_device *pdev) 1404 { 1405 struct port *port; 1406 struct net_device *dev; 1407 struct eth_plat_info *plat = dev_get_platdata(&pdev->dev); 1408 u32 regs_phys; 1409 char phy_id[MII_BUS_ID_SIZE + 3]; 1410 int err; 1411 1412 if (!(dev = alloc_etherdev(sizeof(struct port)))) 1413 return -ENOMEM; 1414 1415 SET_NETDEV_DEV(dev, &pdev->dev); 1416 port = netdev_priv(dev); 1417 port->netdev = dev; 1418 port->id = pdev->id; 1419 1420 switch (port->id) { 1421 case IXP4XX_ETH_NPEA: 1422 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; 1423 regs_phys = IXP4XX_EthA_BASE_PHYS; 1424 break; 1425 case IXP4XX_ETH_NPEB: 1426 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; 1427 regs_phys = IXP4XX_EthB_BASE_PHYS; 1428 break; 1429 case IXP4XX_ETH_NPEC: 1430 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; 1431 regs_phys = IXP4XX_EthC_BASE_PHYS; 1432 break; 1433 default: 1434 err = -ENODEV; 1435 goto err_free; 1436 } 1437 1438 dev->netdev_ops = &ixp4xx_netdev_ops; 1439 dev->ethtool_ops = &ixp4xx_ethtool_ops; 1440 dev->tx_queue_len = 100; 1441 1442 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); 1443 1444 if (!(port->npe = npe_request(NPE_ID(port->id)))) { 1445 err = -EIO; 1446 goto err_free; 1447 } 1448 1449 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); 1450 if (!port->mem_res) { 1451 err = -EBUSY; 1452 goto err_npe_rel; 1453 } 1454 1455 port->plat = plat; 1456 npe_port_tab[NPE_ID(port->id)] = port; 1457 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); 1458 1459 platform_set_drvdata(pdev, dev); 1460 1461 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1462 &port->regs->core_control); 1463 udelay(50); 1464 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1465 udelay(50); 1466 1467 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, 1468 mdio_bus->id, plat->phy); 1469 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 1470 PHY_INTERFACE_MODE_MII); 1471 if (IS_ERR(port->phydev)) { 1472 err = PTR_ERR(port->phydev); 1473 goto err_free_mem; 1474 } 1475 1476 port->phydev->irq = PHY_POLL; 1477 1478 if ((err = register_netdev(dev))) 1479 goto err_phy_dis; 1480 1481 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, 1482 npe_name(port->npe)); 1483 1484 return 0; 1485 1486 err_phy_dis: 1487 phy_disconnect(port->phydev); 1488 err_free_mem: 1489 npe_port_tab[NPE_ID(port->id)] = NULL; 1490 release_resource(port->mem_res); 1491 err_npe_rel: 1492 npe_release(port->npe); 1493 err_free: 1494 free_netdev(dev); 1495 return err; 1496 } 1497 1498 static int eth_remove_one(struct platform_device *pdev) 1499 { 1500 struct net_device *dev = platform_get_drvdata(pdev); 1501 struct port *port = netdev_priv(dev); 1502 1503 unregister_netdev(dev); 1504 phy_disconnect(port->phydev); 1505 npe_port_tab[NPE_ID(port->id)] = NULL; 1506 npe_release(port->npe); 1507 release_resource(port->mem_res); 1508 free_netdev(dev); 1509 return 0; 1510 } 1511 1512 static struct platform_driver ixp4xx_eth_driver = { 1513 .driver.name = DRV_NAME, 1514 .probe = eth_init_one, 1515 .remove = eth_remove_one, 1516 }; 1517 1518 static int __init eth_init_module(void) 1519 { 1520 int err; 1521 if ((err = ixp4xx_mdio_register())) 1522 return err; 1523 return platform_driver_register(&ixp4xx_eth_driver); 1524 } 1525 1526 static void __exit eth_cleanup_module(void) 1527 { 1528 platform_driver_unregister(&ixp4xx_eth_driver); 1529 ixp4xx_mdio_remove(); 1530 } 1531 1532 MODULE_AUTHOR("Krzysztof Halasa"); 1533 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1534 MODULE_LICENSE("GPL v2"); 1535 MODULE_ALIAS("platform:ixp4xx_eth"); 1536 module_init(eth_init_module); 1537 module_exit(eth_cleanup_module); 1538