1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx Ethernet driver for Linux 4 * 5 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Ethernet port config (0x00 is not present on IXP42X): 8 * 9 * logical port 0x00 0x10 0x20 10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 11 * physical PortId 2 0 1 12 * TX queue 23 24 25 13 * RX-free queue 26 27 28 14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 15 * 16 * Queue entries: 17 * bits 0 -> 1 - NPE ID (RX and TX-done) 18 * bits 0 -> 2 - priority (TX, per 802.1D) 19 * bits 3 -> 4 - port ID (user-set?) 20 * bits 5 -> 31 - physical descriptor address 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmapool.h> 26 #include <linux/etherdevice.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/net_tstamp.h> 30 #include <linux/of.h> 31 #include <linux/of_mdio.h> 32 #include <linux/phy.h> 33 #include <linux/platform_data/eth_ixp4xx.h> 34 #include <linux/platform_device.h> 35 #include <linux/ptp_classify.h> 36 #include <linux/slab.h> 37 #include <linux/module.h> 38 #include <linux/soc/ixp4xx/npe.h> 39 #include <linux/soc/ixp4xx/qmgr.h> 40 #include <linux/soc/ixp4xx/cpu.h> 41 42 #include "ixp46x_ts.h" 43 44 #define DEBUG_DESC 0 45 #define DEBUG_RX 0 46 #define DEBUG_TX 0 47 #define DEBUG_PKT_BYTES 0 48 #define DEBUG_MDIO 0 49 #define DEBUG_CLOSE 0 50 51 #define DRV_NAME "ixp4xx_eth" 52 53 #define MAX_NPES 3 54 55 #define RX_DESCS 64 /* also length of all RX queues */ 56 #define TX_DESCS 16 /* also length of all TX queues */ 57 #define TXDONE_QUEUE_LEN 64 /* dwords */ 58 59 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 60 #define REGS_SIZE 0x1000 61 #define MAX_MRU 1536 /* 0x600 */ 62 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 63 64 #define NAPI_WEIGHT 16 65 #define MDIO_INTERVAL (3 * HZ) 66 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 67 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 68 69 #define NPE_ID(port_id) ((port_id) >> 4) 70 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 71 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 72 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 73 #define TXDONE_QUEUE 31 74 75 #define PTP_SLAVE_MODE 1 76 #define PTP_MASTER_MODE 2 77 #define PORT2CHANNEL(p) NPE_ID(p->id) 78 79 /* TX Control Registers */ 80 #define TX_CNTRL0_TX_EN 0x01 81 #define TX_CNTRL0_HALFDUPLEX 0x02 82 #define TX_CNTRL0_RETRY 0x04 83 #define TX_CNTRL0_PAD_EN 0x08 84 #define TX_CNTRL0_APPEND_FCS 0x10 85 #define TX_CNTRL0_2DEFER 0x20 86 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 87 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 88 89 /* RX Control Registers */ 90 #define RX_CNTRL0_RX_EN 0x01 91 #define RX_CNTRL0_PADSTRIP_EN 0x02 92 #define RX_CNTRL0_SEND_FCS 0x04 93 #define RX_CNTRL0_PAUSE_EN 0x08 94 #define RX_CNTRL0_LOOP_EN 0x10 95 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 96 #define RX_CNTRL0_RX_RUNT_EN 0x40 97 #define RX_CNTRL0_BCAST_DIS 0x80 98 #define RX_CNTRL1_DEFER_EN 0x01 99 100 /* Core Control Register */ 101 #define CORE_RESET 0x01 102 #define CORE_RX_FIFO_FLUSH 0x02 103 #define CORE_TX_FIFO_FLUSH 0x04 104 #define CORE_SEND_JAM 0x08 105 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 106 107 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 108 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 109 TX_CNTRL0_2DEFER) 110 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 111 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 112 113 114 /* NPE message codes */ 115 #define NPE_GETSTATUS 0x00 116 #define NPE_EDB_SETPORTADDRESS 0x01 117 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 118 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 119 #define NPE_GETSTATS 0x04 120 #define NPE_RESETSTATS 0x05 121 #define NPE_SETMAXFRAMELENGTHS 0x06 122 #define NPE_VLAN_SETRXTAGMODE 0x07 123 #define NPE_VLAN_SETDEFAULTRXVID 0x08 124 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 125 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 126 #define NPE_VLAN_SETRXQOSENTRY 0x0B 127 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 128 #define NPE_STP_SETBLOCKINGSTATE 0x0D 129 #define NPE_FW_SETFIREWALLMODE 0x0E 130 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 131 #define NPE_PC_SETAPMACTABLE 0x11 132 #define NPE_SETLOOPBACK_MODE 0x12 133 #define NPE_PC_SETBSSIDTABLE 0x13 134 #define NPE_ADDRESS_FILTER_CONFIG 0x14 135 #define NPE_APPENDFCSCONFIG 0x15 136 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 137 #define NPE_MAC_RECOVERY_START 0x17 138 139 140 #ifdef __ARMEB__ 141 typedef struct sk_buff buffer_t; 142 #define free_buffer dev_kfree_skb 143 #define free_buffer_irq dev_consume_skb_irq 144 #else 145 typedef void buffer_t; 146 #define free_buffer kfree 147 #define free_buffer_irq kfree 148 #endif 149 150 struct eth_regs { 151 u32 tx_control[2], __res1[2]; /* 000 */ 152 u32 rx_control[2], __res2[2]; /* 010 */ 153 u32 random_seed, __res3[3]; /* 020 */ 154 u32 partial_empty_threshold, __res4; /* 030 */ 155 u32 partial_full_threshold, __res5; /* 038 */ 156 u32 tx_start_bytes, __res6[3]; /* 040 */ 157 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 158 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 159 u32 slot_time, __res9[3]; /* 070 */ 160 u32 mdio_command[4]; /* 080 */ 161 u32 mdio_status[4]; /* 090 */ 162 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 163 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 164 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 165 u32 hw_addr[6], __res13[61]; /* 0F0 */ 166 u32 core_control; /* 1FC */ 167 }; 168 169 struct port { 170 struct eth_regs __iomem *regs; 171 struct ixp46x_ts_regs __iomem *timesync_regs; 172 int phc_index; 173 struct npe *npe; 174 struct net_device *netdev; 175 struct napi_struct napi; 176 struct eth_plat_info *plat; 177 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 178 struct desc *desc_tab; /* coherent */ 179 dma_addr_t desc_tab_phys; 180 int id; /* logical port ID */ 181 int speed, duplex; 182 u8 firmware[4]; 183 int hwts_tx_en; 184 int hwts_rx_en; 185 }; 186 187 /* NPE message structure */ 188 struct msg { 189 #ifdef __ARMEB__ 190 u8 cmd, eth_id, byte2, byte3; 191 u8 byte4, byte5, byte6, byte7; 192 #else 193 u8 byte3, byte2, eth_id, cmd; 194 u8 byte7, byte6, byte5, byte4; 195 #endif 196 }; 197 198 /* Ethernet packet descriptor */ 199 struct desc { 200 u32 next; /* pointer to next buffer, unused */ 201 202 #ifdef __ARMEB__ 203 u16 buf_len; /* buffer length */ 204 u16 pkt_len; /* packet length */ 205 u32 data; /* pointer to data buffer in RAM */ 206 u8 dest_id; 207 u8 src_id; 208 u16 flags; 209 u8 qos; 210 u8 padlen; 211 u16 vlan_tci; 212 #else 213 u16 pkt_len; /* packet length */ 214 u16 buf_len; /* buffer length */ 215 u32 data; /* pointer to data buffer in RAM */ 216 u16 flags; 217 u8 src_id; 218 u8 dest_id; 219 u16 vlan_tci; 220 u8 padlen; 221 u8 qos; 222 #endif 223 224 #ifdef __ARMEB__ 225 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 226 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 227 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 228 #else 229 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 230 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 231 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 232 #endif 233 }; 234 235 236 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 237 (n) * sizeof(struct desc)) 238 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 239 240 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 241 ((n) + RX_DESCS) * sizeof(struct desc)) 242 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 243 244 #ifndef __ARMEB__ 245 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 246 { 247 int i; 248 for (i = 0; i < cnt; i++) 249 dest[i] = swab32(src[i]); 250 } 251 #endif 252 253 static DEFINE_SPINLOCK(mdio_lock); 254 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 255 static struct mii_bus *mdio_bus; 256 static struct device_node *mdio_bus_np; 257 static int ports_open; 258 static struct port *npe_port_tab[MAX_NPES]; 259 static struct dma_pool *dma_pool; 260 261 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 262 { 263 u8 *data = skb->data; 264 unsigned int offset; 265 u16 *hi, *id; 266 u32 lo; 267 268 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 269 return 0; 270 271 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 272 273 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 274 return 0; 275 276 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 277 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 278 279 memcpy(&lo, &hi[1], sizeof(lo)); 280 281 return (uid_hi == ntohs(*hi) && 282 uid_lo == ntohl(lo) && 283 seqid == ntohs(*id)); 284 } 285 286 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 287 { 288 struct skb_shared_hwtstamps *shhwtstamps; 289 struct ixp46x_ts_regs *regs; 290 u64 ns; 291 u32 ch, hi, lo, val; 292 u16 uid, seq; 293 294 if (!port->hwts_rx_en) 295 return; 296 297 ch = PORT2CHANNEL(port); 298 299 regs = port->timesync_regs; 300 301 val = __raw_readl(®s->channel[ch].ch_event); 302 303 if (!(val & RX_SNAPSHOT_LOCKED)) 304 return; 305 306 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 307 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 308 309 uid = hi & 0xffff; 310 seq = (hi >> 16) & 0xffff; 311 312 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 313 goto out; 314 315 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 316 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 317 ns = ((u64) hi) << 32; 318 ns |= lo; 319 ns <<= TICKS_NS_SHIFT; 320 321 shhwtstamps = skb_hwtstamps(skb); 322 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 323 shhwtstamps->hwtstamp = ns_to_ktime(ns); 324 out: 325 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 326 } 327 328 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 329 { 330 struct skb_shared_hwtstamps shhwtstamps; 331 struct ixp46x_ts_regs *regs; 332 struct skb_shared_info *shtx; 333 u64 ns; 334 u32 ch, cnt, hi, lo, val; 335 336 shtx = skb_shinfo(skb); 337 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 338 shtx->tx_flags |= SKBTX_IN_PROGRESS; 339 else 340 return; 341 342 ch = PORT2CHANNEL(port); 343 344 regs = port->timesync_regs; 345 346 /* 347 * This really stinks, but we have to poll for the Tx time stamp. 348 * Usually, the time stamp is ready after 4 to 6 microseconds. 349 */ 350 for (cnt = 0; cnt < 100; cnt++) { 351 val = __raw_readl(®s->channel[ch].ch_event); 352 if (val & TX_SNAPSHOT_LOCKED) 353 break; 354 udelay(1); 355 } 356 if (!(val & TX_SNAPSHOT_LOCKED)) { 357 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 358 return; 359 } 360 361 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 362 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 363 ns = ((u64) hi) << 32; 364 ns |= lo; 365 ns <<= TICKS_NS_SHIFT; 366 367 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 368 shhwtstamps.hwtstamp = ns_to_ktime(ns); 369 skb_tstamp_tx(skb, &shhwtstamps); 370 371 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 372 } 373 374 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 375 { 376 struct hwtstamp_config cfg; 377 struct ixp46x_ts_regs *regs; 378 struct port *port = netdev_priv(netdev); 379 int ret; 380 int ch; 381 382 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 383 return -EFAULT; 384 385 ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 386 if (ret) 387 return ret; 388 389 ch = PORT2CHANNEL(port); 390 regs = port->timesync_regs; 391 392 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 393 return -ERANGE; 394 395 switch (cfg.rx_filter) { 396 case HWTSTAMP_FILTER_NONE: 397 port->hwts_rx_en = 0; 398 break; 399 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 400 port->hwts_rx_en = PTP_SLAVE_MODE; 401 __raw_writel(0, ®s->channel[ch].ch_control); 402 break; 403 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 404 port->hwts_rx_en = PTP_MASTER_MODE; 405 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 406 break; 407 default: 408 return -ERANGE; 409 } 410 411 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 412 413 /* Clear out any old time stamps. */ 414 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 415 ®s->channel[ch].ch_event); 416 417 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 418 } 419 420 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 421 { 422 struct hwtstamp_config cfg; 423 struct port *port = netdev_priv(netdev); 424 425 cfg.flags = 0; 426 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 427 428 switch (port->hwts_rx_en) { 429 case 0: 430 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 431 break; 432 case PTP_SLAVE_MODE: 433 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 434 break; 435 case PTP_MASTER_MODE: 436 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 437 break; 438 default: 439 WARN_ON_ONCE(1); 440 return -ERANGE; 441 } 442 443 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 444 } 445 446 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 447 int write, u16 cmd) 448 { 449 int cycles = 0; 450 451 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 452 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 453 return -1; 454 } 455 456 if (write) { 457 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 458 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 459 } 460 __raw_writel(((phy_id << 5) | location) & 0xFF, 461 &mdio_regs->mdio_command[2]); 462 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 463 &mdio_regs->mdio_command[3]); 464 465 while ((cycles < MAX_MDIO_RETRIES) && 466 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 467 udelay(1); 468 cycles++; 469 } 470 471 if (cycles == MAX_MDIO_RETRIES) { 472 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 473 phy_id); 474 return -1; 475 } 476 477 #if DEBUG_MDIO 478 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 479 phy_id, write ? "write" : "read", cycles); 480 #endif 481 482 if (write) 483 return 0; 484 485 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 486 #if DEBUG_MDIO 487 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 488 phy_id); 489 #endif 490 return 0xFFFF; /* don't return error */ 491 } 492 493 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 494 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 495 } 496 497 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 498 { 499 unsigned long flags; 500 int ret; 501 502 spin_lock_irqsave(&mdio_lock, flags); 503 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 504 spin_unlock_irqrestore(&mdio_lock, flags); 505 #if DEBUG_MDIO 506 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 507 phy_id, location, ret); 508 #endif 509 return ret; 510 } 511 512 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 513 u16 val) 514 { 515 unsigned long flags; 516 int ret; 517 518 spin_lock_irqsave(&mdio_lock, flags); 519 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 520 spin_unlock_irqrestore(&mdio_lock, flags); 521 #if DEBUG_MDIO 522 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 523 bus->name, phy_id, location, val, ret); 524 #endif 525 return ret; 526 } 527 528 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) 529 { 530 int err; 531 532 if (!(mdio_bus = mdiobus_alloc())) 533 return -ENOMEM; 534 535 mdio_regs = regs; 536 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 537 mdio_bus->name = "IXP4xx MII Bus"; 538 mdio_bus->read = &ixp4xx_mdio_read; 539 mdio_bus->write = &ixp4xx_mdio_write; 540 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 541 542 err = of_mdiobus_register(mdio_bus, mdio_bus_np); 543 if (err) 544 mdiobus_free(mdio_bus); 545 return err; 546 } 547 548 static void ixp4xx_mdio_remove(void) 549 { 550 mdiobus_unregister(mdio_bus); 551 mdiobus_free(mdio_bus); 552 } 553 554 555 static void ixp4xx_adjust_link(struct net_device *dev) 556 { 557 struct port *port = netdev_priv(dev); 558 struct phy_device *phydev = dev->phydev; 559 560 if (!phydev->link) { 561 if (port->speed) { 562 port->speed = 0; 563 printk(KERN_INFO "%s: link down\n", dev->name); 564 } 565 return; 566 } 567 568 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 569 return; 570 571 port->speed = phydev->speed; 572 port->duplex = phydev->duplex; 573 574 if (port->duplex) 575 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 576 &port->regs->tx_control[0]); 577 else 578 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 579 &port->regs->tx_control[0]); 580 581 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n", 582 dev->name, port->speed, port->duplex ? "full" : "half"); 583 } 584 585 586 static inline void debug_pkt(struct net_device *dev, const char *func, 587 u8 *data, int len) 588 { 589 #if DEBUG_PKT_BYTES 590 int i; 591 592 netdev_debug(dev, "%s(%i) ", func, len); 593 for (i = 0; i < len; i++) { 594 if (i >= DEBUG_PKT_BYTES) 595 break; 596 printk("%s%02X", 597 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 598 data[i]); 599 } 600 printk("\n"); 601 #endif 602 } 603 604 605 static inline void debug_desc(u32 phys, struct desc *desc) 606 { 607 #if DEBUG_DESC 608 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 609 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 610 phys, desc->next, desc->buf_len, desc->pkt_len, 611 desc->data, desc->dest_id, desc->src_id, desc->flags, 612 desc->qos, desc->padlen, desc->vlan_tci, 613 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 614 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 615 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 616 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 617 #endif 618 } 619 620 static inline int queue_get_desc(unsigned int queue, struct port *port, 621 int is_tx) 622 { 623 u32 phys, tab_phys, n_desc; 624 struct desc *tab; 625 626 if (!(phys = qmgr_get_entry(queue))) 627 return -1; 628 629 phys &= ~0x1F; /* mask out non-address bits */ 630 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 631 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 632 n_desc = (phys - tab_phys) / sizeof(struct desc); 633 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 634 debug_desc(phys, &tab[n_desc]); 635 BUG_ON(tab[n_desc].next); 636 return n_desc; 637 } 638 639 static inline void queue_put_desc(unsigned int queue, u32 phys, 640 struct desc *desc) 641 { 642 debug_desc(phys, desc); 643 BUG_ON(phys & 0x1F); 644 qmgr_put_entry(queue, phys); 645 /* Don't check for queue overflow here, we've allocated sufficient 646 length and queues >= 32 don't support this check anyway. */ 647 } 648 649 650 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 651 { 652 #ifdef __ARMEB__ 653 dma_unmap_single(&port->netdev->dev, desc->data, 654 desc->buf_len, DMA_TO_DEVICE); 655 #else 656 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 657 ALIGN((desc->data & 3) + desc->buf_len, 4), 658 DMA_TO_DEVICE); 659 #endif 660 } 661 662 663 static void eth_rx_irq(void *pdev) 664 { 665 struct net_device *dev = pdev; 666 struct port *port = netdev_priv(dev); 667 668 #if DEBUG_RX 669 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 670 #endif 671 qmgr_disable_irq(port->plat->rxq); 672 napi_schedule(&port->napi); 673 } 674 675 static int eth_poll(struct napi_struct *napi, int budget) 676 { 677 struct port *port = container_of(napi, struct port, napi); 678 struct net_device *dev = port->netdev; 679 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 680 int received = 0; 681 682 #if DEBUG_RX 683 netdev_debug(dev, "eth_poll\n"); 684 #endif 685 686 while (received < budget) { 687 struct sk_buff *skb; 688 struct desc *desc; 689 int n; 690 #ifdef __ARMEB__ 691 struct sk_buff *temp; 692 u32 phys; 693 #endif 694 695 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 696 #if DEBUG_RX 697 netdev_debug(dev, "eth_poll napi_complete\n"); 698 #endif 699 napi_complete(napi); 700 qmgr_enable_irq(rxq); 701 if (!qmgr_stat_below_low_watermark(rxq) && 702 napi_reschedule(napi)) { /* not empty again */ 703 #if DEBUG_RX 704 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n"); 705 #endif 706 qmgr_disable_irq(rxq); 707 continue; 708 } 709 #if DEBUG_RX 710 netdev_debug(dev, "eth_poll all done\n"); 711 #endif 712 return received; /* all work done */ 713 } 714 715 desc = rx_desc_ptr(port, n); 716 717 #ifdef __ARMEB__ 718 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 719 phys = dma_map_single(&dev->dev, skb->data, 720 RX_BUFF_SIZE, DMA_FROM_DEVICE); 721 if (dma_mapping_error(&dev->dev, phys)) { 722 dev_kfree_skb(skb); 723 skb = NULL; 724 } 725 } 726 #else 727 skb = netdev_alloc_skb(dev, 728 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 729 #endif 730 731 if (!skb) { 732 dev->stats.rx_dropped++; 733 /* put the desc back on RX-ready queue */ 734 desc->buf_len = MAX_MRU; 735 desc->pkt_len = 0; 736 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 737 continue; 738 } 739 740 /* process received frame */ 741 #ifdef __ARMEB__ 742 temp = skb; 743 skb = port->rx_buff_tab[n]; 744 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 745 RX_BUFF_SIZE, DMA_FROM_DEVICE); 746 #else 747 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 748 RX_BUFF_SIZE, DMA_FROM_DEVICE); 749 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 750 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 751 #endif 752 skb_reserve(skb, NET_IP_ALIGN); 753 skb_put(skb, desc->pkt_len); 754 755 debug_pkt(dev, "eth_poll", skb->data, skb->len); 756 757 ixp_rx_timestamp(port, skb); 758 skb->protocol = eth_type_trans(skb, dev); 759 dev->stats.rx_packets++; 760 dev->stats.rx_bytes += skb->len; 761 netif_receive_skb(skb); 762 763 /* put the new buffer on RX-free queue */ 764 #ifdef __ARMEB__ 765 port->rx_buff_tab[n] = temp; 766 desc->data = phys + NET_IP_ALIGN; 767 #endif 768 desc->buf_len = MAX_MRU; 769 desc->pkt_len = 0; 770 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 771 received++; 772 } 773 774 #if DEBUG_RX 775 netdev_debug(dev, "eth_poll(): end, not all work done\n"); 776 #endif 777 return received; /* not all work done */ 778 } 779 780 781 static void eth_txdone_irq(void *unused) 782 { 783 u32 phys; 784 785 #if DEBUG_TX 786 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 787 #endif 788 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 789 u32 npe_id, n_desc; 790 struct port *port; 791 struct desc *desc; 792 int start; 793 794 npe_id = phys & 3; 795 BUG_ON(npe_id >= MAX_NPES); 796 port = npe_port_tab[npe_id]; 797 BUG_ON(!port); 798 phys &= ~0x1F; /* mask out non-address bits */ 799 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 800 BUG_ON(n_desc >= TX_DESCS); 801 desc = tx_desc_ptr(port, n_desc); 802 debug_desc(phys, desc); 803 804 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 805 port->netdev->stats.tx_packets++; 806 port->netdev->stats.tx_bytes += desc->pkt_len; 807 808 dma_unmap_tx(port, desc); 809 #if DEBUG_TX 810 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 811 port->netdev->name, port->tx_buff_tab[n_desc]); 812 #endif 813 free_buffer_irq(port->tx_buff_tab[n_desc]); 814 port->tx_buff_tab[n_desc] = NULL; 815 } 816 817 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 818 queue_put_desc(port->plat->txreadyq, phys, desc); 819 if (start) { /* TX-ready queue was empty */ 820 #if DEBUG_TX 821 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 822 port->netdev->name); 823 #endif 824 netif_wake_queue(port->netdev); 825 } 826 } 827 } 828 829 static int eth_xmit(struct sk_buff *skb, struct net_device *dev) 830 { 831 struct port *port = netdev_priv(dev); 832 unsigned int txreadyq = port->plat->txreadyq; 833 int len, offset, bytes, n; 834 void *mem; 835 u32 phys; 836 struct desc *desc; 837 838 #if DEBUG_TX 839 netdev_debug(dev, "eth_xmit\n"); 840 #endif 841 842 if (unlikely(skb->len > MAX_MRU)) { 843 dev_kfree_skb(skb); 844 dev->stats.tx_errors++; 845 return NETDEV_TX_OK; 846 } 847 848 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 849 850 len = skb->len; 851 #ifdef __ARMEB__ 852 offset = 0; /* no need to keep alignment */ 853 bytes = len; 854 mem = skb->data; 855 #else 856 offset = (uintptr_t)skb->data & 3; /* keep 32-bit alignment */ 857 bytes = ALIGN(offset + len, 4); 858 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 859 dev_kfree_skb(skb); 860 dev->stats.tx_dropped++; 861 return NETDEV_TX_OK; 862 } 863 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4); 864 #endif 865 866 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 867 if (dma_mapping_error(&dev->dev, phys)) { 868 dev_kfree_skb(skb); 869 #ifndef __ARMEB__ 870 kfree(mem); 871 #endif 872 dev->stats.tx_dropped++; 873 return NETDEV_TX_OK; 874 } 875 876 n = queue_get_desc(txreadyq, port, 1); 877 BUG_ON(n < 0); 878 desc = tx_desc_ptr(port, n); 879 880 #ifdef __ARMEB__ 881 port->tx_buff_tab[n] = skb; 882 #else 883 port->tx_buff_tab[n] = mem; 884 #endif 885 desc->data = phys + offset; 886 desc->buf_len = desc->pkt_len = len; 887 888 /* NPE firmware pads short frames with zeros internally */ 889 wmb(); 890 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 891 892 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 893 #if DEBUG_TX 894 netdev_debug(dev, "eth_xmit queue full\n"); 895 #endif 896 netif_stop_queue(dev); 897 /* we could miss TX ready interrupt */ 898 /* really empty in fact */ 899 if (!qmgr_stat_below_low_watermark(txreadyq)) { 900 #if DEBUG_TX 901 netdev_debug(dev, "eth_xmit ready again\n"); 902 #endif 903 netif_wake_queue(dev); 904 } 905 } 906 907 #if DEBUG_TX 908 netdev_debug(dev, "eth_xmit end\n"); 909 #endif 910 911 ixp_tx_timestamp(port, skb); 912 skb_tx_timestamp(skb); 913 914 #ifndef __ARMEB__ 915 dev_kfree_skb(skb); 916 #endif 917 return NETDEV_TX_OK; 918 } 919 920 921 static void eth_set_mcast_list(struct net_device *dev) 922 { 923 struct port *port = netdev_priv(dev); 924 struct netdev_hw_addr *ha; 925 u8 diffs[ETH_ALEN], *addr; 926 int i; 927 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 928 929 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) { 930 for (i = 0; i < ETH_ALEN; i++) { 931 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 932 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 933 } 934 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 935 &port->regs->rx_control[0]); 936 return; 937 } 938 939 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 940 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 941 &port->regs->rx_control[0]); 942 return; 943 } 944 945 eth_zero_addr(diffs); 946 947 addr = NULL; 948 netdev_for_each_mc_addr(ha, dev) { 949 if (!addr) 950 addr = ha->addr; /* first MAC address */ 951 for (i = 0; i < ETH_ALEN; i++) 952 diffs[i] |= addr[i] ^ ha->addr[i]; 953 } 954 955 for (i = 0; i < ETH_ALEN; i++) { 956 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 957 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 958 } 959 960 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 961 &port->regs->rx_control[0]); 962 } 963 964 965 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 966 { 967 if (!netif_running(dev)) 968 return -EINVAL; 969 970 if (cpu_is_ixp46x()) { 971 if (cmd == SIOCSHWTSTAMP) 972 return hwtstamp_set(dev, req); 973 if (cmd == SIOCGHWTSTAMP) 974 return hwtstamp_get(dev, req); 975 } 976 977 return phy_mii_ioctl(dev->phydev, req, cmd); 978 } 979 980 /* ethtool support */ 981 982 static void ixp4xx_get_drvinfo(struct net_device *dev, 983 struct ethtool_drvinfo *info) 984 { 985 struct port *port = netdev_priv(dev); 986 987 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 988 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 989 port->firmware[0], port->firmware[1], 990 port->firmware[2], port->firmware[3]); 991 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 992 } 993 994 static int ixp4xx_get_ts_info(struct net_device *dev, 995 struct ethtool_ts_info *info) 996 { 997 struct port *port = netdev_priv(dev); 998 999 if (port->phc_index < 0) 1000 ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 1001 1002 info->phc_index = port->phc_index; 1003 1004 if (info->phc_index < 0) { 1005 info->so_timestamping = 1006 SOF_TIMESTAMPING_TX_SOFTWARE | 1007 SOF_TIMESTAMPING_RX_SOFTWARE | 1008 SOF_TIMESTAMPING_SOFTWARE; 1009 return 0; 1010 } 1011 info->so_timestamping = 1012 SOF_TIMESTAMPING_TX_HARDWARE | 1013 SOF_TIMESTAMPING_RX_HARDWARE | 1014 SOF_TIMESTAMPING_RAW_HARDWARE; 1015 info->tx_types = 1016 (1 << HWTSTAMP_TX_OFF) | 1017 (1 << HWTSTAMP_TX_ON); 1018 info->rx_filters = 1019 (1 << HWTSTAMP_FILTER_NONE) | 1020 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1021 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1022 return 0; 1023 } 1024 1025 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1026 .get_drvinfo = ixp4xx_get_drvinfo, 1027 .nway_reset = phy_ethtool_nway_reset, 1028 .get_link = ethtool_op_get_link, 1029 .get_ts_info = ixp4xx_get_ts_info, 1030 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1031 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1032 }; 1033 1034 1035 static int request_queues(struct port *port) 1036 { 1037 int err; 1038 1039 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1040 "%s:RX-free", port->netdev->name); 1041 if (err) 1042 return err; 1043 1044 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1045 "%s:RX", port->netdev->name); 1046 if (err) 1047 goto rel_rxfree; 1048 1049 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1050 "%s:TX", port->netdev->name); 1051 if (err) 1052 goto rel_rx; 1053 1054 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1055 "%s:TX-ready", port->netdev->name); 1056 if (err) 1057 goto rel_tx; 1058 1059 /* TX-done queue handles skbs sent out by the NPEs */ 1060 if (!ports_open) { 1061 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1062 "%s:TX-done", DRV_NAME); 1063 if (err) 1064 goto rel_txready; 1065 } 1066 return 0; 1067 1068 rel_txready: 1069 qmgr_release_queue(port->plat->txreadyq); 1070 rel_tx: 1071 qmgr_release_queue(TX_QUEUE(port->id)); 1072 rel_rx: 1073 qmgr_release_queue(port->plat->rxq); 1074 rel_rxfree: 1075 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1076 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1077 port->netdev->name); 1078 return err; 1079 } 1080 1081 static void release_queues(struct port *port) 1082 { 1083 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1084 qmgr_release_queue(port->plat->rxq); 1085 qmgr_release_queue(TX_QUEUE(port->id)); 1086 qmgr_release_queue(port->plat->txreadyq); 1087 1088 if (!ports_open) 1089 qmgr_release_queue(TXDONE_QUEUE); 1090 } 1091 1092 static int init_queues(struct port *port) 1093 { 1094 int i; 1095 1096 if (!ports_open) { 1097 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1098 POOL_ALLOC_SIZE, 32, 0); 1099 if (!dma_pool) 1100 return -ENOMEM; 1101 } 1102 1103 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys); 1104 if (!port->desc_tab) 1105 return -ENOMEM; 1106 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1107 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1108 1109 /* Setup RX buffers */ 1110 for (i = 0; i < RX_DESCS; i++) { 1111 struct desc *desc = rx_desc_ptr(port, i); 1112 buffer_t *buff; /* skb or kmalloc()ated memory */ 1113 void *data; 1114 #ifdef __ARMEB__ 1115 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1116 return -ENOMEM; 1117 data = buff->data; 1118 #else 1119 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1120 return -ENOMEM; 1121 data = buff; 1122 #endif 1123 desc->buf_len = MAX_MRU; 1124 desc->data = dma_map_single(&port->netdev->dev, data, 1125 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1126 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1127 free_buffer(buff); 1128 return -EIO; 1129 } 1130 desc->data += NET_IP_ALIGN; 1131 port->rx_buff_tab[i] = buff; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static void destroy_queues(struct port *port) 1138 { 1139 int i; 1140 1141 if (port->desc_tab) { 1142 for (i = 0; i < RX_DESCS; i++) { 1143 struct desc *desc = rx_desc_ptr(port, i); 1144 buffer_t *buff = port->rx_buff_tab[i]; 1145 if (buff) { 1146 dma_unmap_single(&port->netdev->dev, 1147 desc->data - NET_IP_ALIGN, 1148 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1149 free_buffer(buff); 1150 } 1151 } 1152 for (i = 0; i < TX_DESCS; i++) { 1153 struct desc *desc = tx_desc_ptr(port, i); 1154 buffer_t *buff = port->tx_buff_tab[i]; 1155 if (buff) { 1156 dma_unmap_tx(port, desc); 1157 free_buffer(buff); 1158 } 1159 } 1160 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1161 port->desc_tab = NULL; 1162 } 1163 1164 if (!ports_open && dma_pool) { 1165 dma_pool_destroy(dma_pool); 1166 dma_pool = NULL; 1167 } 1168 } 1169 1170 static int eth_open(struct net_device *dev) 1171 { 1172 struct port *port = netdev_priv(dev); 1173 struct npe *npe = port->npe; 1174 struct msg msg; 1175 int i, err; 1176 1177 if (!npe_running(npe)) { 1178 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1179 if (err) 1180 return err; 1181 1182 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1183 netdev_err(dev, "%s not responding\n", npe_name(npe)); 1184 return -EIO; 1185 } 1186 port->firmware[0] = msg.byte4; 1187 port->firmware[1] = msg.byte5; 1188 port->firmware[2] = msg.byte6; 1189 port->firmware[3] = msg.byte7; 1190 } 1191 1192 memset(&msg, 0, sizeof(msg)); 1193 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1194 msg.eth_id = port->id; 1195 msg.byte5 = port->plat->rxq | 0x80; 1196 msg.byte7 = port->plat->rxq << 4; 1197 for (i = 0; i < 8; i++) { 1198 msg.byte3 = i; 1199 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1200 return -EIO; 1201 } 1202 1203 msg.cmd = NPE_EDB_SETPORTADDRESS; 1204 msg.eth_id = PHYSICAL_ID(port->id); 1205 msg.byte2 = dev->dev_addr[0]; 1206 msg.byte3 = dev->dev_addr[1]; 1207 msg.byte4 = dev->dev_addr[2]; 1208 msg.byte5 = dev->dev_addr[3]; 1209 msg.byte6 = dev->dev_addr[4]; 1210 msg.byte7 = dev->dev_addr[5]; 1211 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1212 return -EIO; 1213 1214 memset(&msg, 0, sizeof(msg)); 1215 msg.cmd = NPE_FW_SETFIREWALLMODE; 1216 msg.eth_id = port->id; 1217 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1218 return -EIO; 1219 1220 if ((err = request_queues(port)) != 0) 1221 return err; 1222 1223 if ((err = init_queues(port)) != 0) { 1224 destroy_queues(port); 1225 release_queues(port); 1226 return err; 1227 } 1228 1229 port->speed = 0; /* force "link up" message */ 1230 phy_start(dev->phydev); 1231 1232 for (i = 0; i < ETH_ALEN; i++) 1233 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1234 __raw_writel(0x08, &port->regs->random_seed); 1235 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1236 __raw_writel(0x30, &port->regs->partial_full_threshold); 1237 __raw_writel(0x08, &port->regs->tx_start_bytes); 1238 __raw_writel(0x15, &port->regs->tx_deferral); 1239 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1240 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1241 __raw_writel(0x80, &port->regs->slot_time); 1242 __raw_writel(0x01, &port->regs->int_clock_threshold); 1243 1244 /* Populate queues with buffers, no failure after this point */ 1245 for (i = 0; i < TX_DESCS; i++) 1246 queue_put_desc(port->plat->txreadyq, 1247 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1248 1249 for (i = 0; i < RX_DESCS; i++) 1250 queue_put_desc(RXFREE_QUEUE(port->id), 1251 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1252 1253 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1254 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1255 __raw_writel(0, &port->regs->rx_control[1]); 1256 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1257 1258 napi_enable(&port->napi); 1259 eth_set_mcast_list(dev); 1260 netif_start_queue(dev); 1261 1262 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1263 eth_rx_irq, dev); 1264 if (!ports_open) { 1265 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1266 eth_txdone_irq, NULL); 1267 qmgr_enable_irq(TXDONE_QUEUE); 1268 } 1269 ports_open++; 1270 /* we may already have RX data, enables IRQ */ 1271 napi_schedule(&port->napi); 1272 return 0; 1273 } 1274 1275 static int eth_close(struct net_device *dev) 1276 { 1277 struct port *port = netdev_priv(dev); 1278 struct msg msg; 1279 int buffs = RX_DESCS; /* allocated RX buffers */ 1280 int i; 1281 1282 ports_open--; 1283 qmgr_disable_irq(port->plat->rxq); 1284 napi_disable(&port->napi); 1285 netif_stop_queue(dev); 1286 1287 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1288 buffs--; 1289 1290 memset(&msg, 0, sizeof(msg)); 1291 msg.cmd = NPE_SETLOOPBACK_MODE; 1292 msg.eth_id = port->id; 1293 msg.byte3 = 1; 1294 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1295 netdev_crit(dev, "unable to enable loopback\n"); 1296 1297 i = 0; 1298 do { /* drain RX buffers */ 1299 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1300 buffs--; 1301 if (!buffs) 1302 break; 1303 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1304 /* we have to inject some packet */ 1305 struct desc *desc; 1306 u32 phys; 1307 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1308 BUG_ON(n < 0); 1309 desc = tx_desc_ptr(port, n); 1310 phys = tx_desc_phys(port, n); 1311 desc->buf_len = desc->pkt_len = 1; 1312 wmb(); 1313 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1314 } 1315 udelay(1); 1316 } while (++i < MAX_CLOSE_WAIT); 1317 1318 if (buffs) 1319 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)" 1320 " left in NPE\n", buffs); 1321 #if DEBUG_CLOSE 1322 if (!buffs) 1323 netdev_debug(dev, "draining RX queue took %i cycles\n", i); 1324 #endif 1325 1326 buffs = TX_DESCS; 1327 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1328 buffs--; /* cancel TX */ 1329 1330 i = 0; 1331 do { 1332 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1333 buffs--; 1334 if (!buffs) 1335 break; 1336 } while (++i < MAX_CLOSE_WAIT); 1337 1338 if (buffs) 1339 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) " 1340 "left in NPE\n", buffs); 1341 #if DEBUG_CLOSE 1342 if (!buffs) 1343 netdev_debug(dev, "draining TX queues took %i cycles\n", i); 1344 #endif 1345 1346 msg.byte3 = 0; 1347 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1348 netdev_crit(dev, "unable to disable loopback\n"); 1349 1350 phy_stop(dev->phydev); 1351 1352 if (!ports_open) 1353 qmgr_disable_irq(TXDONE_QUEUE); 1354 destroy_queues(port); 1355 release_queues(port); 1356 return 0; 1357 } 1358 1359 static const struct net_device_ops ixp4xx_netdev_ops = { 1360 .ndo_open = eth_open, 1361 .ndo_stop = eth_close, 1362 .ndo_start_xmit = eth_xmit, 1363 .ndo_set_rx_mode = eth_set_mcast_list, 1364 .ndo_eth_ioctl = eth_ioctl, 1365 .ndo_set_mac_address = eth_mac_addr, 1366 .ndo_validate_addr = eth_validate_addr, 1367 }; 1368 1369 #ifdef CONFIG_OF 1370 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1371 { 1372 struct device_node *np = dev->of_node; 1373 struct of_phandle_args queue_spec; 1374 struct of_phandle_args npe_spec; 1375 struct device_node *mdio_np; 1376 struct eth_plat_info *plat; 1377 int ret; 1378 1379 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); 1380 if (!plat) 1381 return NULL; 1382 1383 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, 1384 &npe_spec); 1385 if (ret) { 1386 dev_err(dev, "no NPE engine specified\n"); 1387 return NULL; 1388 } 1389 /* NPE ID 0x00, 0x10, 0x20... */ 1390 plat->npe = (npe_spec.args[0] << 4); 1391 1392 /* Check if this device has an MDIO bus */ 1393 mdio_np = of_get_child_by_name(np, "mdio"); 1394 if (mdio_np) { 1395 plat->has_mdio = true; 1396 mdio_bus_np = mdio_np; 1397 /* DO NOT put the mdio_np, it will be used */ 1398 } 1399 1400 /* Get the rx queue as a resource from queue manager */ 1401 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, 1402 &queue_spec); 1403 if (ret) { 1404 dev_err(dev, "no rx queue phandle\n"); 1405 return NULL; 1406 } 1407 plat->rxq = queue_spec.args[0]; 1408 1409 /* Get the txready queue as resource from queue manager */ 1410 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, 1411 &queue_spec); 1412 if (ret) { 1413 dev_err(dev, "no txready queue phandle\n"); 1414 return NULL; 1415 } 1416 plat->txreadyq = queue_spec.args[0]; 1417 1418 return plat; 1419 } 1420 #else 1421 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1422 { 1423 return NULL; 1424 } 1425 #endif 1426 1427 static int ixp4xx_eth_probe(struct platform_device *pdev) 1428 { 1429 struct phy_device *phydev = NULL; 1430 struct device *dev = &pdev->dev; 1431 struct device_node *np = dev->of_node; 1432 struct eth_plat_info *plat; 1433 struct net_device *ndev; 1434 struct port *port; 1435 int err; 1436 1437 if (np) { 1438 plat = ixp4xx_of_get_platdata(dev); 1439 if (!plat) 1440 return -ENODEV; 1441 } else { 1442 plat = dev_get_platdata(dev); 1443 if (!plat) 1444 return -ENODEV; 1445 plat->npe = pdev->id; 1446 switch (plat->npe) { 1447 case IXP4XX_ETH_NPEA: 1448 /* If the MDIO bus is not up yet, defer probe */ 1449 break; 1450 case IXP4XX_ETH_NPEB: 1451 /* On all except IXP43x, NPE-B is used for the MDIO bus. 1452 * If there is no NPE-B in the feature set, bail out, 1453 * else we have the MDIO bus here. 1454 */ 1455 if (!cpu_is_ixp43x()) { 1456 if (!(ixp4xx_read_feature_bits() & 1457 IXP4XX_FEATURE_NPEB_ETH0)) 1458 return -ENODEV; 1459 /* Else register the MDIO bus on NPE-B */ 1460 plat->has_mdio = true; 1461 } 1462 break; 1463 case IXP4XX_ETH_NPEC: 1464 /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus 1465 * access, if there is no NPE-C, no bus, nothing works, 1466 * so bail out. 1467 */ 1468 if (cpu_is_ixp43x()) { 1469 if (!(ixp4xx_read_feature_bits() & 1470 IXP4XX_FEATURE_NPEC_ETH)) 1471 return -ENODEV; 1472 /* Else register the MDIO bus on NPE-B */ 1473 plat->has_mdio = true; 1474 } 1475 break; 1476 default: 1477 return -ENODEV; 1478 } 1479 } 1480 1481 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) 1482 return -ENOMEM; 1483 1484 SET_NETDEV_DEV(ndev, dev); 1485 port = netdev_priv(ndev); 1486 port->netdev = ndev; 1487 port->id = plat->npe; 1488 port->phc_index = -1; 1489 1490 /* Get the port resource and remap */ 1491 port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1492 if (IS_ERR(port->regs)) 1493 return PTR_ERR(port->regs); 1494 1495 /* Register the MDIO bus if we have it */ 1496 if (plat->has_mdio) { 1497 err = ixp4xx_mdio_register(port->regs); 1498 if (err) { 1499 dev_err(dev, "failed to register MDIO bus\n"); 1500 return err; 1501 } 1502 } 1503 /* If the instance with the MDIO bus has not yet appeared, 1504 * defer probing until it gets probed. 1505 */ 1506 if (!mdio_bus) 1507 return -EPROBE_DEFER; 1508 1509 ndev->netdev_ops = &ixp4xx_netdev_ops; 1510 ndev->ethtool_ops = &ixp4xx_ethtool_ops; 1511 ndev->tx_queue_len = 100; 1512 /* Inherit the DMA masks from the platform device */ 1513 ndev->dev.dma_mask = dev->dma_mask; 1514 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask; 1515 1516 netif_napi_add(ndev, &port->napi, eth_poll, NAPI_WEIGHT); 1517 1518 if (!(port->npe = npe_request(NPE_ID(port->id)))) 1519 return -EIO; 1520 1521 port->plat = plat; 1522 npe_port_tab[NPE_ID(port->id)] = port; 1523 eth_hw_addr_set(ndev, plat->hwaddr); 1524 1525 platform_set_drvdata(pdev, ndev); 1526 1527 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1528 &port->regs->core_control); 1529 udelay(50); 1530 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1531 udelay(50); 1532 1533 if (np) { 1534 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); 1535 } else { 1536 phydev = mdiobus_get_phy(mdio_bus, plat->phy); 1537 if (!phydev) { 1538 err = -ENODEV; 1539 dev_err(dev, "could not connect phydev (%d)\n", err); 1540 goto err_free_mem; 1541 } 1542 err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, 1543 PHY_INTERFACE_MODE_MII); 1544 if (err) 1545 goto err_free_mem; 1546 1547 } 1548 if (!phydev) { 1549 err = -ENODEV; 1550 dev_err(dev, "no phydev\n"); 1551 goto err_free_mem; 1552 } 1553 1554 phydev->irq = PHY_POLL; 1555 1556 if ((err = register_netdev(ndev))) 1557 goto err_phy_dis; 1558 1559 netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy, 1560 npe_name(port->npe)); 1561 1562 return 0; 1563 1564 err_phy_dis: 1565 phy_disconnect(phydev); 1566 err_free_mem: 1567 npe_port_tab[NPE_ID(port->id)] = NULL; 1568 npe_release(port->npe); 1569 return err; 1570 } 1571 1572 static int ixp4xx_eth_remove(struct platform_device *pdev) 1573 { 1574 struct net_device *ndev = platform_get_drvdata(pdev); 1575 struct phy_device *phydev = ndev->phydev; 1576 struct port *port = netdev_priv(ndev); 1577 1578 unregister_netdev(ndev); 1579 phy_disconnect(phydev); 1580 ixp4xx_mdio_remove(); 1581 npe_port_tab[NPE_ID(port->id)] = NULL; 1582 npe_release(port->npe); 1583 return 0; 1584 } 1585 1586 static const struct of_device_id ixp4xx_eth_of_match[] = { 1587 { 1588 .compatible = "intel,ixp4xx-ethernet", 1589 }, 1590 { }, 1591 }; 1592 1593 static struct platform_driver ixp4xx_eth_driver = { 1594 .driver = { 1595 .name = DRV_NAME, 1596 .of_match_table = of_match_ptr(ixp4xx_eth_of_match), 1597 }, 1598 .probe = ixp4xx_eth_probe, 1599 .remove = ixp4xx_eth_remove, 1600 }; 1601 module_platform_driver(ixp4xx_eth_driver); 1602 1603 MODULE_AUTHOR("Krzysztof Halasa"); 1604 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1605 MODULE_LICENSE("GPL v2"); 1606 MODULE_ALIAS("platform:ixp4xx_eth"); 1607