1 /* 2 * Intel IXP4xx Ethernet driver for Linux 3 * 4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Ethernet port config (0x00 is not present on IXP42X): 11 * 12 * logical port 0x00 0x10 0x20 13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 14 * physical PortId 2 0 1 15 * TX queue 23 24 25 16 * RX-free queue 26 27 28 17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 18 * 19 * 20 * Queue entries: 21 * bits 0 -> 1 - NPE ID (RX and TX-done) 22 * bits 0 -> 2 - priority (TX, per 802.1D) 23 * bits 3 -> 4 - port ID (user-set?) 24 * bits 5 -> 31 - physical descriptor address 25 */ 26 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/dmapool.h> 30 #include <linux/etherdevice.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/of.h> 35 #include <linux/phy.h> 36 #include <linux/platform_device.h> 37 #include <linux/ptp_classify.h> 38 #include <linux/slab.h> 39 #include <linux/module.h> 40 #include <mach/ixp46x_ts.h> 41 #include <linux/soc/ixp4xx/npe.h> 42 #include <linux/soc/ixp4xx/qmgr.h> 43 44 #define DEBUG_DESC 0 45 #define DEBUG_RX 0 46 #define DEBUG_TX 0 47 #define DEBUG_PKT_BYTES 0 48 #define DEBUG_MDIO 0 49 #define DEBUG_CLOSE 0 50 51 #define DRV_NAME "ixp4xx_eth" 52 53 #define MAX_NPES 3 54 55 #define RX_DESCS 64 /* also length of all RX queues */ 56 #define TX_DESCS 16 /* also length of all TX queues */ 57 #define TXDONE_QUEUE_LEN 64 /* dwords */ 58 59 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 60 #define REGS_SIZE 0x1000 61 #define MAX_MRU 1536 /* 0x600 */ 62 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 63 64 #define NAPI_WEIGHT 16 65 #define MDIO_INTERVAL (3 * HZ) 66 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 67 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 68 69 #define NPE_ID(port_id) ((port_id) >> 4) 70 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 71 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 72 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 73 #define TXDONE_QUEUE 31 74 75 #define PTP_SLAVE_MODE 1 76 #define PTP_MASTER_MODE 2 77 #define PORT2CHANNEL(p) NPE_ID(p->id) 78 79 /* TX Control Registers */ 80 #define TX_CNTRL0_TX_EN 0x01 81 #define TX_CNTRL0_HALFDUPLEX 0x02 82 #define TX_CNTRL0_RETRY 0x04 83 #define TX_CNTRL0_PAD_EN 0x08 84 #define TX_CNTRL0_APPEND_FCS 0x10 85 #define TX_CNTRL0_2DEFER 0x20 86 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 87 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 88 89 /* RX Control Registers */ 90 #define RX_CNTRL0_RX_EN 0x01 91 #define RX_CNTRL0_PADSTRIP_EN 0x02 92 #define RX_CNTRL0_SEND_FCS 0x04 93 #define RX_CNTRL0_PAUSE_EN 0x08 94 #define RX_CNTRL0_LOOP_EN 0x10 95 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 96 #define RX_CNTRL0_RX_RUNT_EN 0x40 97 #define RX_CNTRL0_BCAST_DIS 0x80 98 #define RX_CNTRL1_DEFER_EN 0x01 99 100 /* Core Control Register */ 101 #define CORE_RESET 0x01 102 #define CORE_RX_FIFO_FLUSH 0x02 103 #define CORE_TX_FIFO_FLUSH 0x04 104 #define CORE_SEND_JAM 0x08 105 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 106 107 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 108 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 109 TX_CNTRL0_2DEFER) 110 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 111 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 112 113 114 /* NPE message codes */ 115 #define NPE_GETSTATUS 0x00 116 #define NPE_EDB_SETPORTADDRESS 0x01 117 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 118 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 119 #define NPE_GETSTATS 0x04 120 #define NPE_RESETSTATS 0x05 121 #define NPE_SETMAXFRAMELENGTHS 0x06 122 #define NPE_VLAN_SETRXTAGMODE 0x07 123 #define NPE_VLAN_SETDEFAULTRXVID 0x08 124 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 125 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 126 #define NPE_VLAN_SETRXQOSENTRY 0x0B 127 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 128 #define NPE_STP_SETBLOCKINGSTATE 0x0D 129 #define NPE_FW_SETFIREWALLMODE 0x0E 130 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 131 #define NPE_PC_SETAPMACTABLE 0x11 132 #define NPE_SETLOOPBACK_MODE 0x12 133 #define NPE_PC_SETBSSIDTABLE 0x13 134 #define NPE_ADDRESS_FILTER_CONFIG 0x14 135 #define NPE_APPENDFCSCONFIG 0x15 136 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 137 #define NPE_MAC_RECOVERY_START 0x17 138 139 140 #ifdef __ARMEB__ 141 typedef struct sk_buff buffer_t; 142 #define free_buffer dev_kfree_skb 143 #define free_buffer_irq dev_consume_skb_irq 144 #else 145 typedef void buffer_t; 146 #define free_buffer kfree 147 #define free_buffer_irq kfree 148 #endif 149 150 struct eth_regs { 151 u32 tx_control[2], __res1[2]; /* 000 */ 152 u32 rx_control[2], __res2[2]; /* 010 */ 153 u32 random_seed, __res3[3]; /* 020 */ 154 u32 partial_empty_threshold, __res4; /* 030 */ 155 u32 partial_full_threshold, __res5; /* 038 */ 156 u32 tx_start_bytes, __res6[3]; /* 040 */ 157 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 158 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 159 u32 slot_time, __res9[3]; /* 070 */ 160 u32 mdio_command[4]; /* 080 */ 161 u32 mdio_status[4]; /* 090 */ 162 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 163 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 164 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 165 u32 hw_addr[6], __res13[61]; /* 0F0 */ 166 u32 core_control; /* 1FC */ 167 }; 168 169 struct port { 170 struct resource *mem_res; 171 struct eth_regs __iomem *regs; 172 struct npe *npe; 173 struct net_device *netdev; 174 struct napi_struct napi; 175 struct eth_plat_info *plat; 176 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 177 struct desc *desc_tab; /* coherent */ 178 u32 desc_tab_phys; 179 int id; /* logical port ID */ 180 int speed, duplex; 181 u8 firmware[4]; 182 int hwts_tx_en; 183 int hwts_rx_en; 184 }; 185 186 /* NPE message structure */ 187 struct msg { 188 #ifdef __ARMEB__ 189 u8 cmd, eth_id, byte2, byte3; 190 u8 byte4, byte5, byte6, byte7; 191 #else 192 u8 byte3, byte2, eth_id, cmd; 193 u8 byte7, byte6, byte5, byte4; 194 #endif 195 }; 196 197 /* Ethernet packet descriptor */ 198 struct desc { 199 u32 next; /* pointer to next buffer, unused */ 200 201 #ifdef __ARMEB__ 202 u16 buf_len; /* buffer length */ 203 u16 pkt_len; /* packet length */ 204 u32 data; /* pointer to data buffer in RAM */ 205 u8 dest_id; 206 u8 src_id; 207 u16 flags; 208 u8 qos; 209 u8 padlen; 210 u16 vlan_tci; 211 #else 212 u16 pkt_len; /* packet length */ 213 u16 buf_len; /* buffer length */ 214 u32 data; /* pointer to data buffer in RAM */ 215 u16 flags; 216 u8 src_id; 217 u8 dest_id; 218 u16 vlan_tci; 219 u8 padlen; 220 u8 qos; 221 #endif 222 223 #ifdef __ARMEB__ 224 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 225 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 226 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 227 #else 228 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 229 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 230 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 231 #endif 232 }; 233 234 235 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 236 (n) * sizeof(struct desc)) 237 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 238 239 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 240 ((n) + RX_DESCS) * sizeof(struct desc)) 241 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 242 243 #ifndef __ARMEB__ 244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 245 { 246 int i; 247 for (i = 0; i < cnt; i++) 248 dest[i] = swab32(src[i]); 249 } 250 #endif 251 252 static spinlock_t mdio_lock; 253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 254 static struct mii_bus *mdio_bus; 255 static int ports_open; 256 static struct port *npe_port_tab[MAX_NPES]; 257 static struct dma_pool *dma_pool; 258 259 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 260 { 261 u8 *data = skb->data; 262 unsigned int offset; 263 u16 *hi, *id; 264 u32 lo; 265 266 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 267 return 0; 268 269 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 270 271 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 272 return 0; 273 274 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 275 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 276 277 memcpy(&lo, &hi[1], sizeof(lo)); 278 279 return (uid_hi == ntohs(*hi) && 280 uid_lo == ntohl(lo) && 281 seqid == ntohs(*id)); 282 } 283 284 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 285 { 286 struct skb_shared_hwtstamps *shhwtstamps; 287 struct ixp46x_ts_regs *regs; 288 u64 ns; 289 u32 ch, hi, lo, val; 290 u16 uid, seq; 291 292 if (!port->hwts_rx_en) 293 return; 294 295 ch = PORT2CHANNEL(port); 296 297 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 298 299 val = __raw_readl(®s->channel[ch].ch_event); 300 301 if (!(val & RX_SNAPSHOT_LOCKED)) 302 return; 303 304 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 305 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 306 307 uid = hi & 0xffff; 308 seq = (hi >> 16) & 0xffff; 309 310 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 311 goto out; 312 313 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 314 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 315 ns = ((u64) hi) << 32; 316 ns |= lo; 317 ns <<= TICKS_NS_SHIFT; 318 319 shhwtstamps = skb_hwtstamps(skb); 320 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 321 shhwtstamps->hwtstamp = ns_to_ktime(ns); 322 out: 323 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 324 } 325 326 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 327 { 328 struct skb_shared_hwtstamps shhwtstamps; 329 struct ixp46x_ts_regs *regs; 330 struct skb_shared_info *shtx; 331 u64 ns; 332 u32 ch, cnt, hi, lo, val; 333 334 shtx = skb_shinfo(skb); 335 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 336 shtx->tx_flags |= SKBTX_IN_PROGRESS; 337 else 338 return; 339 340 ch = PORT2CHANNEL(port); 341 342 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 343 344 /* 345 * This really stinks, but we have to poll for the Tx time stamp. 346 * Usually, the time stamp is ready after 4 to 6 microseconds. 347 */ 348 for (cnt = 0; cnt < 100; cnt++) { 349 val = __raw_readl(®s->channel[ch].ch_event); 350 if (val & TX_SNAPSHOT_LOCKED) 351 break; 352 udelay(1); 353 } 354 if (!(val & TX_SNAPSHOT_LOCKED)) { 355 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 356 return; 357 } 358 359 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 360 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 361 ns = ((u64) hi) << 32; 362 ns |= lo; 363 ns <<= TICKS_NS_SHIFT; 364 365 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 366 shhwtstamps.hwtstamp = ns_to_ktime(ns); 367 skb_tstamp_tx(skb, &shhwtstamps); 368 369 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 370 } 371 372 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 373 { 374 struct hwtstamp_config cfg; 375 struct ixp46x_ts_regs *regs; 376 struct port *port = netdev_priv(netdev); 377 int ch; 378 379 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 380 return -EFAULT; 381 382 if (cfg.flags) /* reserved for future extensions */ 383 return -EINVAL; 384 385 ch = PORT2CHANNEL(port); 386 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 387 388 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 389 return -ERANGE; 390 391 switch (cfg.rx_filter) { 392 case HWTSTAMP_FILTER_NONE: 393 port->hwts_rx_en = 0; 394 break; 395 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 396 port->hwts_rx_en = PTP_SLAVE_MODE; 397 __raw_writel(0, ®s->channel[ch].ch_control); 398 break; 399 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 400 port->hwts_rx_en = PTP_MASTER_MODE; 401 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 402 break; 403 default: 404 return -ERANGE; 405 } 406 407 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 408 409 /* Clear out any old time stamps. */ 410 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 411 ®s->channel[ch].ch_event); 412 413 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 414 } 415 416 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 417 { 418 struct hwtstamp_config cfg; 419 struct port *port = netdev_priv(netdev); 420 421 cfg.flags = 0; 422 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 423 424 switch (port->hwts_rx_en) { 425 case 0: 426 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 427 break; 428 case PTP_SLAVE_MODE: 429 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 430 break; 431 case PTP_MASTER_MODE: 432 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 433 break; 434 default: 435 WARN_ON_ONCE(1); 436 return -ERANGE; 437 } 438 439 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 440 } 441 442 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 443 int write, u16 cmd) 444 { 445 int cycles = 0; 446 447 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 448 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 449 return -1; 450 } 451 452 if (write) { 453 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 454 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 455 } 456 __raw_writel(((phy_id << 5) | location) & 0xFF, 457 &mdio_regs->mdio_command[2]); 458 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 459 &mdio_regs->mdio_command[3]); 460 461 while ((cycles < MAX_MDIO_RETRIES) && 462 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 463 udelay(1); 464 cycles++; 465 } 466 467 if (cycles == MAX_MDIO_RETRIES) { 468 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 469 phy_id); 470 return -1; 471 } 472 473 #if DEBUG_MDIO 474 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 475 phy_id, write ? "write" : "read", cycles); 476 #endif 477 478 if (write) 479 return 0; 480 481 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 482 #if DEBUG_MDIO 483 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 484 phy_id); 485 #endif 486 return 0xFFFF; /* don't return error */ 487 } 488 489 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 490 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 491 } 492 493 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 494 { 495 unsigned long flags; 496 int ret; 497 498 spin_lock_irqsave(&mdio_lock, flags); 499 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 500 spin_unlock_irqrestore(&mdio_lock, flags); 501 #if DEBUG_MDIO 502 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 503 phy_id, location, ret); 504 #endif 505 return ret; 506 } 507 508 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 509 u16 val) 510 { 511 unsigned long flags; 512 int ret; 513 514 spin_lock_irqsave(&mdio_lock, flags); 515 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 516 spin_unlock_irqrestore(&mdio_lock, flags); 517 #if DEBUG_MDIO 518 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 519 bus->name, phy_id, location, val, ret); 520 #endif 521 return ret; 522 } 523 524 static int ixp4xx_mdio_register(void) 525 { 526 int err; 527 528 if (!(mdio_bus = mdiobus_alloc())) 529 return -ENOMEM; 530 531 if (cpu_is_ixp43x()) { 532 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ 533 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) 534 return -ENODEV; 535 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; 536 } else { 537 /* All MII PHY accesses use NPE-B Ethernet registers */ 538 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) 539 return -ENODEV; 540 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; 541 } 542 543 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 544 spin_lock_init(&mdio_lock); 545 mdio_bus->name = "IXP4xx MII Bus"; 546 mdio_bus->read = &ixp4xx_mdio_read; 547 mdio_bus->write = &ixp4xx_mdio_write; 548 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 549 550 if ((err = mdiobus_register(mdio_bus))) 551 mdiobus_free(mdio_bus); 552 return err; 553 } 554 555 static void ixp4xx_mdio_remove(void) 556 { 557 mdiobus_unregister(mdio_bus); 558 mdiobus_free(mdio_bus); 559 } 560 561 562 static void ixp4xx_adjust_link(struct net_device *dev) 563 { 564 struct port *port = netdev_priv(dev); 565 struct phy_device *phydev = dev->phydev; 566 567 if (!phydev->link) { 568 if (port->speed) { 569 port->speed = 0; 570 printk(KERN_INFO "%s: link down\n", dev->name); 571 } 572 return; 573 } 574 575 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 576 return; 577 578 port->speed = phydev->speed; 579 port->duplex = phydev->duplex; 580 581 if (port->duplex) 582 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 583 &port->regs->tx_control[0]); 584 else 585 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 586 &port->regs->tx_control[0]); 587 588 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", 589 dev->name, port->speed, port->duplex ? "full" : "half"); 590 } 591 592 593 static inline void debug_pkt(struct net_device *dev, const char *func, 594 u8 *data, int len) 595 { 596 #if DEBUG_PKT_BYTES 597 int i; 598 599 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); 600 for (i = 0; i < len; i++) { 601 if (i >= DEBUG_PKT_BYTES) 602 break; 603 printk("%s%02X", 604 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 605 data[i]); 606 } 607 printk("\n"); 608 #endif 609 } 610 611 612 static inline void debug_desc(u32 phys, struct desc *desc) 613 { 614 #if DEBUG_DESC 615 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 616 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 617 phys, desc->next, desc->buf_len, desc->pkt_len, 618 desc->data, desc->dest_id, desc->src_id, desc->flags, 619 desc->qos, desc->padlen, desc->vlan_tci, 620 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 621 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 622 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 623 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 624 #endif 625 } 626 627 static inline int queue_get_desc(unsigned int queue, struct port *port, 628 int is_tx) 629 { 630 u32 phys, tab_phys, n_desc; 631 struct desc *tab; 632 633 if (!(phys = qmgr_get_entry(queue))) 634 return -1; 635 636 phys &= ~0x1F; /* mask out non-address bits */ 637 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 638 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 639 n_desc = (phys - tab_phys) / sizeof(struct desc); 640 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 641 debug_desc(phys, &tab[n_desc]); 642 BUG_ON(tab[n_desc].next); 643 return n_desc; 644 } 645 646 static inline void queue_put_desc(unsigned int queue, u32 phys, 647 struct desc *desc) 648 { 649 debug_desc(phys, desc); 650 BUG_ON(phys & 0x1F); 651 qmgr_put_entry(queue, phys); 652 /* Don't check for queue overflow here, we've allocated sufficient 653 length and queues >= 32 don't support this check anyway. */ 654 } 655 656 657 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 658 { 659 #ifdef __ARMEB__ 660 dma_unmap_single(&port->netdev->dev, desc->data, 661 desc->buf_len, DMA_TO_DEVICE); 662 #else 663 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 664 ALIGN((desc->data & 3) + desc->buf_len, 4), 665 DMA_TO_DEVICE); 666 #endif 667 } 668 669 670 static void eth_rx_irq(void *pdev) 671 { 672 struct net_device *dev = pdev; 673 struct port *port = netdev_priv(dev); 674 675 #if DEBUG_RX 676 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 677 #endif 678 qmgr_disable_irq(port->plat->rxq); 679 napi_schedule(&port->napi); 680 } 681 682 static int eth_poll(struct napi_struct *napi, int budget) 683 { 684 struct port *port = container_of(napi, struct port, napi); 685 struct net_device *dev = port->netdev; 686 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 687 int received = 0; 688 689 #if DEBUG_RX 690 printk(KERN_DEBUG "%s: eth_poll\n", dev->name); 691 #endif 692 693 while (received < budget) { 694 struct sk_buff *skb; 695 struct desc *desc; 696 int n; 697 #ifdef __ARMEB__ 698 struct sk_buff *temp; 699 u32 phys; 700 #endif 701 702 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 703 #if DEBUG_RX 704 printk(KERN_DEBUG "%s: eth_poll napi_complete\n", 705 dev->name); 706 #endif 707 napi_complete(napi); 708 qmgr_enable_irq(rxq); 709 if (!qmgr_stat_below_low_watermark(rxq) && 710 napi_reschedule(napi)) { /* not empty again */ 711 #if DEBUG_RX 712 printk(KERN_DEBUG "%s: eth_poll napi_reschedule succeeded\n", 713 dev->name); 714 #endif 715 qmgr_disable_irq(rxq); 716 continue; 717 } 718 #if DEBUG_RX 719 printk(KERN_DEBUG "%s: eth_poll all done\n", 720 dev->name); 721 #endif 722 return received; /* all work done */ 723 } 724 725 desc = rx_desc_ptr(port, n); 726 727 #ifdef __ARMEB__ 728 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 729 phys = dma_map_single(&dev->dev, skb->data, 730 RX_BUFF_SIZE, DMA_FROM_DEVICE); 731 if (dma_mapping_error(&dev->dev, phys)) { 732 dev_kfree_skb(skb); 733 skb = NULL; 734 } 735 } 736 #else 737 skb = netdev_alloc_skb(dev, 738 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 739 #endif 740 741 if (!skb) { 742 dev->stats.rx_dropped++; 743 /* put the desc back on RX-ready queue */ 744 desc->buf_len = MAX_MRU; 745 desc->pkt_len = 0; 746 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 747 continue; 748 } 749 750 /* process received frame */ 751 #ifdef __ARMEB__ 752 temp = skb; 753 skb = port->rx_buff_tab[n]; 754 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 755 RX_BUFF_SIZE, DMA_FROM_DEVICE); 756 #else 757 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 758 RX_BUFF_SIZE, DMA_FROM_DEVICE); 759 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 760 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 761 #endif 762 skb_reserve(skb, NET_IP_ALIGN); 763 skb_put(skb, desc->pkt_len); 764 765 debug_pkt(dev, "eth_poll", skb->data, skb->len); 766 767 ixp_rx_timestamp(port, skb); 768 skb->protocol = eth_type_trans(skb, dev); 769 dev->stats.rx_packets++; 770 dev->stats.rx_bytes += skb->len; 771 netif_receive_skb(skb); 772 773 /* put the new buffer on RX-free queue */ 774 #ifdef __ARMEB__ 775 port->rx_buff_tab[n] = temp; 776 desc->data = phys + NET_IP_ALIGN; 777 #endif 778 desc->buf_len = MAX_MRU; 779 desc->pkt_len = 0; 780 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 781 received++; 782 } 783 784 #if DEBUG_RX 785 printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); 786 #endif 787 return received; /* not all work done */ 788 } 789 790 791 static void eth_txdone_irq(void *unused) 792 { 793 u32 phys; 794 795 #if DEBUG_TX 796 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 797 #endif 798 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 799 u32 npe_id, n_desc; 800 struct port *port; 801 struct desc *desc; 802 int start; 803 804 npe_id = phys & 3; 805 BUG_ON(npe_id >= MAX_NPES); 806 port = npe_port_tab[npe_id]; 807 BUG_ON(!port); 808 phys &= ~0x1F; /* mask out non-address bits */ 809 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 810 BUG_ON(n_desc >= TX_DESCS); 811 desc = tx_desc_ptr(port, n_desc); 812 debug_desc(phys, desc); 813 814 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 815 port->netdev->stats.tx_packets++; 816 port->netdev->stats.tx_bytes += desc->pkt_len; 817 818 dma_unmap_tx(port, desc); 819 #if DEBUG_TX 820 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 821 port->netdev->name, port->tx_buff_tab[n_desc]); 822 #endif 823 free_buffer_irq(port->tx_buff_tab[n_desc]); 824 port->tx_buff_tab[n_desc] = NULL; 825 } 826 827 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 828 queue_put_desc(port->plat->txreadyq, phys, desc); 829 if (start) { /* TX-ready queue was empty */ 830 #if DEBUG_TX 831 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 832 port->netdev->name); 833 #endif 834 netif_wake_queue(port->netdev); 835 } 836 } 837 } 838 839 static int eth_xmit(struct sk_buff *skb, struct net_device *dev) 840 { 841 struct port *port = netdev_priv(dev); 842 unsigned int txreadyq = port->plat->txreadyq; 843 int len, offset, bytes, n; 844 void *mem; 845 u32 phys; 846 struct desc *desc; 847 848 #if DEBUG_TX 849 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); 850 #endif 851 852 if (unlikely(skb->len > MAX_MRU)) { 853 dev_kfree_skb(skb); 854 dev->stats.tx_errors++; 855 return NETDEV_TX_OK; 856 } 857 858 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 859 860 len = skb->len; 861 #ifdef __ARMEB__ 862 offset = 0; /* no need to keep alignment */ 863 bytes = len; 864 mem = skb->data; 865 #else 866 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 867 bytes = ALIGN(offset + len, 4); 868 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 869 dev_kfree_skb(skb); 870 dev->stats.tx_dropped++; 871 return NETDEV_TX_OK; 872 } 873 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); 874 #endif 875 876 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 877 if (dma_mapping_error(&dev->dev, phys)) { 878 dev_kfree_skb(skb); 879 #ifndef __ARMEB__ 880 kfree(mem); 881 #endif 882 dev->stats.tx_dropped++; 883 return NETDEV_TX_OK; 884 } 885 886 n = queue_get_desc(txreadyq, port, 1); 887 BUG_ON(n < 0); 888 desc = tx_desc_ptr(port, n); 889 890 #ifdef __ARMEB__ 891 port->tx_buff_tab[n] = skb; 892 #else 893 port->tx_buff_tab[n] = mem; 894 #endif 895 desc->data = phys + offset; 896 desc->buf_len = desc->pkt_len = len; 897 898 /* NPE firmware pads short frames with zeros internally */ 899 wmb(); 900 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 901 902 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 903 #if DEBUG_TX 904 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); 905 #endif 906 netif_stop_queue(dev); 907 /* we could miss TX ready interrupt */ 908 /* really empty in fact */ 909 if (!qmgr_stat_below_low_watermark(txreadyq)) { 910 #if DEBUG_TX 911 printk(KERN_DEBUG "%s: eth_xmit ready again\n", 912 dev->name); 913 #endif 914 netif_wake_queue(dev); 915 } 916 } 917 918 #if DEBUG_TX 919 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); 920 #endif 921 922 ixp_tx_timestamp(port, skb); 923 skb_tx_timestamp(skb); 924 925 #ifndef __ARMEB__ 926 dev_kfree_skb(skb); 927 #endif 928 return NETDEV_TX_OK; 929 } 930 931 932 static void eth_set_mcast_list(struct net_device *dev) 933 { 934 struct port *port = netdev_priv(dev); 935 struct netdev_hw_addr *ha; 936 u8 diffs[ETH_ALEN], *addr; 937 int i; 938 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 939 940 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) { 941 for (i = 0; i < ETH_ALEN; i++) { 942 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 943 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 944 } 945 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 946 &port->regs->rx_control[0]); 947 return; 948 } 949 950 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 951 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 952 &port->regs->rx_control[0]); 953 return; 954 } 955 956 eth_zero_addr(diffs); 957 958 addr = NULL; 959 netdev_for_each_mc_addr(ha, dev) { 960 if (!addr) 961 addr = ha->addr; /* first MAC address */ 962 for (i = 0; i < ETH_ALEN; i++) 963 diffs[i] |= addr[i] ^ ha->addr[i]; 964 } 965 966 for (i = 0; i < ETH_ALEN; i++) { 967 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 968 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 969 } 970 971 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 972 &port->regs->rx_control[0]); 973 } 974 975 976 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 977 { 978 if (!netif_running(dev)) 979 return -EINVAL; 980 981 if (cpu_is_ixp46x()) { 982 if (cmd == SIOCSHWTSTAMP) 983 return hwtstamp_set(dev, req); 984 if (cmd == SIOCGHWTSTAMP) 985 return hwtstamp_get(dev, req); 986 } 987 988 return phy_mii_ioctl(dev->phydev, req, cmd); 989 } 990 991 /* ethtool support */ 992 993 static void ixp4xx_get_drvinfo(struct net_device *dev, 994 struct ethtool_drvinfo *info) 995 { 996 struct port *port = netdev_priv(dev); 997 998 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 999 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 1000 port->firmware[0], port->firmware[1], 1001 port->firmware[2], port->firmware[3]); 1002 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 1003 } 1004 1005 int ixp46x_phc_index = -1; 1006 EXPORT_SYMBOL_GPL(ixp46x_phc_index); 1007 1008 static int ixp4xx_get_ts_info(struct net_device *dev, 1009 struct ethtool_ts_info *info) 1010 { 1011 if (!cpu_is_ixp46x()) { 1012 info->so_timestamping = 1013 SOF_TIMESTAMPING_TX_SOFTWARE | 1014 SOF_TIMESTAMPING_RX_SOFTWARE | 1015 SOF_TIMESTAMPING_SOFTWARE; 1016 info->phc_index = -1; 1017 return 0; 1018 } 1019 info->so_timestamping = 1020 SOF_TIMESTAMPING_TX_HARDWARE | 1021 SOF_TIMESTAMPING_RX_HARDWARE | 1022 SOF_TIMESTAMPING_RAW_HARDWARE; 1023 info->phc_index = ixp46x_phc_index; 1024 info->tx_types = 1025 (1 << HWTSTAMP_TX_OFF) | 1026 (1 << HWTSTAMP_TX_ON); 1027 info->rx_filters = 1028 (1 << HWTSTAMP_FILTER_NONE) | 1029 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1030 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1031 return 0; 1032 } 1033 1034 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1035 .get_drvinfo = ixp4xx_get_drvinfo, 1036 .nway_reset = phy_ethtool_nway_reset, 1037 .get_link = ethtool_op_get_link, 1038 .get_ts_info = ixp4xx_get_ts_info, 1039 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1040 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1041 }; 1042 1043 1044 static int request_queues(struct port *port) 1045 { 1046 int err; 1047 1048 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1049 "%s:RX-free", port->netdev->name); 1050 if (err) 1051 return err; 1052 1053 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1054 "%s:RX", port->netdev->name); 1055 if (err) 1056 goto rel_rxfree; 1057 1058 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1059 "%s:TX", port->netdev->name); 1060 if (err) 1061 goto rel_rx; 1062 1063 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1064 "%s:TX-ready", port->netdev->name); 1065 if (err) 1066 goto rel_tx; 1067 1068 /* TX-done queue handles skbs sent out by the NPEs */ 1069 if (!ports_open) { 1070 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1071 "%s:TX-done", DRV_NAME); 1072 if (err) 1073 goto rel_txready; 1074 } 1075 return 0; 1076 1077 rel_txready: 1078 qmgr_release_queue(port->plat->txreadyq); 1079 rel_tx: 1080 qmgr_release_queue(TX_QUEUE(port->id)); 1081 rel_rx: 1082 qmgr_release_queue(port->plat->rxq); 1083 rel_rxfree: 1084 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1085 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1086 port->netdev->name); 1087 return err; 1088 } 1089 1090 static void release_queues(struct port *port) 1091 { 1092 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1093 qmgr_release_queue(port->plat->rxq); 1094 qmgr_release_queue(TX_QUEUE(port->id)); 1095 qmgr_release_queue(port->plat->txreadyq); 1096 1097 if (!ports_open) 1098 qmgr_release_queue(TXDONE_QUEUE); 1099 } 1100 1101 static int init_queues(struct port *port) 1102 { 1103 int i; 1104 1105 if (!ports_open) { 1106 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1107 POOL_ALLOC_SIZE, 32, 0); 1108 if (!dma_pool) 1109 return -ENOMEM; 1110 } 1111 1112 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, 1113 &port->desc_tab_phys))) 1114 return -ENOMEM; 1115 memset(port->desc_tab, 0, POOL_ALLOC_SIZE); 1116 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1117 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1118 1119 /* Setup RX buffers */ 1120 for (i = 0; i < RX_DESCS; i++) { 1121 struct desc *desc = rx_desc_ptr(port, i); 1122 buffer_t *buff; /* skb or kmalloc()ated memory */ 1123 void *data; 1124 #ifdef __ARMEB__ 1125 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1126 return -ENOMEM; 1127 data = buff->data; 1128 #else 1129 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1130 return -ENOMEM; 1131 data = buff; 1132 #endif 1133 desc->buf_len = MAX_MRU; 1134 desc->data = dma_map_single(&port->netdev->dev, data, 1135 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1136 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1137 free_buffer(buff); 1138 return -EIO; 1139 } 1140 desc->data += NET_IP_ALIGN; 1141 port->rx_buff_tab[i] = buff; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static void destroy_queues(struct port *port) 1148 { 1149 int i; 1150 1151 if (port->desc_tab) { 1152 for (i = 0; i < RX_DESCS; i++) { 1153 struct desc *desc = rx_desc_ptr(port, i); 1154 buffer_t *buff = port->rx_buff_tab[i]; 1155 if (buff) { 1156 dma_unmap_single(&port->netdev->dev, 1157 desc->data - NET_IP_ALIGN, 1158 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1159 free_buffer(buff); 1160 } 1161 } 1162 for (i = 0; i < TX_DESCS; i++) { 1163 struct desc *desc = tx_desc_ptr(port, i); 1164 buffer_t *buff = port->tx_buff_tab[i]; 1165 if (buff) { 1166 dma_unmap_tx(port, desc); 1167 free_buffer(buff); 1168 } 1169 } 1170 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1171 port->desc_tab = NULL; 1172 } 1173 1174 if (!ports_open && dma_pool) { 1175 dma_pool_destroy(dma_pool); 1176 dma_pool = NULL; 1177 } 1178 } 1179 1180 static int eth_open(struct net_device *dev) 1181 { 1182 struct port *port = netdev_priv(dev); 1183 struct npe *npe = port->npe; 1184 struct msg msg; 1185 int i, err; 1186 1187 if (!npe_running(npe)) { 1188 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1189 if (err) 1190 return err; 1191 1192 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1193 printk(KERN_ERR "%s: %s not responding\n", dev->name, 1194 npe_name(npe)); 1195 return -EIO; 1196 } 1197 port->firmware[0] = msg.byte4; 1198 port->firmware[1] = msg.byte5; 1199 port->firmware[2] = msg.byte6; 1200 port->firmware[3] = msg.byte7; 1201 } 1202 1203 memset(&msg, 0, sizeof(msg)); 1204 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1205 msg.eth_id = port->id; 1206 msg.byte5 = port->plat->rxq | 0x80; 1207 msg.byte7 = port->plat->rxq << 4; 1208 for (i = 0; i < 8; i++) { 1209 msg.byte3 = i; 1210 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1211 return -EIO; 1212 } 1213 1214 msg.cmd = NPE_EDB_SETPORTADDRESS; 1215 msg.eth_id = PHYSICAL_ID(port->id); 1216 msg.byte2 = dev->dev_addr[0]; 1217 msg.byte3 = dev->dev_addr[1]; 1218 msg.byte4 = dev->dev_addr[2]; 1219 msg.byte5 = dev->dev_addr[3]; 1220 msg.byte6 = dev->dev_addr[4]; 1221 msg.byte7 = dev->dev_addr[5]; 1222 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1223 return -EIO; 1224 1225 memset(&msg, 0, sizeof(msg)); 1226 msg.cmd = NPE_FW_SETFIREWALLMODE; 1227 msg.eth_id = port->id; 1228 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1229 return -EIO; 1230 1231 if ((err = request_queues(port)) != 0) 1232 return err; 1233 1234 if ((err = init_queues(port)) != 0) { 1235 destroy_queues(port); 1236 release_queues(port); 1237 return err; 1238 } 1239 1240 port->speed = 0; /* force "link up" message */ 1241 phy_start(dev->phydev); 1242 1243 for (i = 0; i < ETH_ALEN; i++) 1244 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1245 __raw_writel(0x08, &port->regs->random_seed); 1246 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1247 __raw_writel(0x30, &port->regs->partial_full_threshold); 1248 __raw_writel(0x08, &port->regs->tx_start_bytes); 1249 __raw_writel(0x15, &port->regs->tx_deferral); 1250 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1251 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1252 __raw_writel(0x80, &port->regs->slot_time); 1253 __raw_writel(0x01, &port->regs->int_clock_threshold); 1254 1255 /* Populate queues with buffers, no failure after this point */ 1256 for (i = 0; i < TX_DESCS; i++) 1257 queue_put_desc(port->plat->txreadyq, 1258 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1259 1260 for (i = 0; i < RX_DESCS; i++) 1261 queue_put_desc(RXFREE_QUEUE(port->id), 1262 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1263 1264 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1265 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1266 __raw_writel(0, &port->regs->rx_control[1]); 1267 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1268 1269 napi_enable(&port->napi); 1270 eth_set_mcast_list(dev); 1271 netif_start_queue(dev); 1272 1273 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1274 eth_rx_irq, dev); 1275 if (!ports_open) { 1276 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1277 eth_txdone_irq, NULL); 1278 qmgr_enable_irq(TXDONE_QUEUE); 1279 } 1280 ports_open++; 1281 /* we may already have RX data, enables IRQ */ 1282 napi_schedule(&port->napi); 1283 return 0; 1284 } 1285 1286 static int eth_close(struct net_device *dev) 1287 { 1288 struct port *port = netdev_priv(dev); 1289 struct msg msg; 1290 int buffs = RX_DESCS; /* allocated RX buffers */ 1291 int i; 1292 1293 ports_open--; 1294 qmgr_disable_irq(port->plat->rxq); 1295 napi_disable(&port->napi); 1296 netif_stop_queue(dev); 1297 1298 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1299 buffs--; 1300 1301 memset(&msg, 0, sizeof(msg)); 1302 msg.cmd = NPE_SETLOOPBACK_MODE; 1303 msg.eth_id = port->id; 1304 msg.byte3 = 1; 1305 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1306 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); 1307 1308 i = 0; 1309 do { /* drain RX buffers */ 1310 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1311 buffs--; 1312 if (!buffs) 1313 break; 1314 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1315 /* we have to inject some packet */ 1316 struct desc *desc; 1317 u32 phys; 1318 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1319 BUG_ON(n < 0); 1320 desc = tx_desc_ptr(port, n); 1321 phys = tx_desc_phys(port, n); 1322 desc->buf_len = desc->pkt_len = 1; 1323 wmb(); 1324 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1325 } 1326 udelay(1); 1327 } while (++i < MAX_CLOSE_WAIT); 1328 1329 if (buffs) 1330 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" 1331 " left in NPE\n", dev->name, buffs); 1332 #if DEBUG_CLOSE 1333 if (!buffs) 1334 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); 1335 #endif 1336 1337 buffs = TX_DESCS; 1338 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1339 buffs--; /* cancel TX */ 1340 1341 i = 0; 1342 do { 1343 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1344 buffs--; 1345 if (!buffs) 1346 break; 1347 } while (++i < MAX_CLOSE_WAIT); 1348 1349 if (buffs) 1350 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " 1351 "left in NPE\n", dev->name, buffs); 1352 #if DEBUG_CLOSE 1353 if (!buffs) 1354 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); 1355 #endif 1356 1357 msg.byte3 = 0; 1358 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1359 printk(KERN_CRIT "%s: unable to disable loopback\n", 1360 dev->name); 1361 1362 phy_stop(dev->phydev); 1363 1364 if (!ports_open) 1365 qmgr_disable_irq(TXDONE_QUEUE); 1366 destroy_queues(port); 1367 release_queues(port); 1368 return 0; 1369 } 1370 1371 static const struct net_device_ops ixp4xx_netdev_ops = { 1372 .ndo_open = eth_open, 1373 .ndo_stop = eth_close, 1374 .ndo_start_xmit = eth_xmit, 1375 .ndo_set_rx_mode = eth_set_mcast_list, 1376 .ndo_do_ioctl = eth_ioctl, 1377 .ndo_set_mac_address = eth_mac_addr, 1378 .ndo_validate_addr = eth_validate_addr, 1379 }; 1380 1381 static int eth_init_one(struct platform_device *pdev) 1382 { 1383 struct port *port; 1384 struct net_device *dev; 1385 struct eth_plat_info *plat = dev_get_platdata(&pdev->dev); 1386 struct phy_device *phydev = NULL; 1387 u32 regs_phys; 1388 char phy_id[MII_BUS_ID_SIZE + 3]; 1389 int err; 1390 1391 if (!(dev = alloc_etherdev(sizeof(struct port)))) 1392 return -ENOMEM; 1393 1394 SET_NETDEV_DEV(dev, &pdev->dev); 1395 port = netdev_priv(dev); 1396 port->netdev = dev; 1397 port->id = pdev->id; 1398 1399 switch (port->id) { 1400 case IXP4XX_ETH_NPEA: 1401 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; 1402 regs_phys = IXP4XX_EthA_BASE_PHYS; 1403 break; 1404 case IXP4XX_ETH_NPEB: 1405 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; 1406 regs_phys = IXP4XX_EthB_BASE_PHYS; 1407 break; 1408 case IXP4XX_ETH_NPEC: 1409 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; 1410 regs_phys = IXP4XX_EthC_BASE_PHYS; 1411 break; 1412 default: 1413 err = -ENODEV; 1414 goto err_free; 1415 } 1416 1417 dev->netdev_ops = &ixp4xx_netdev_ops; 1418 dev->ethtool_ops = &ixp4xx_ethtool_ops; 1419 dev->tx_queue_len = 100; 1420 1421 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); 1422 1423 if (!(port->npe = npe_request(NPE_ID(port->id)))) { 1424 err = -EIO; 1425 goto err_free; 1426 } 1427 1428 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); 1429 if (!port->mem_res) { 1430 err = -EBUSY; 1431 goto err_npe_rel; 1432 } 1433 1434 port->plat = plat; 1435 npe_port_tab[NPE_ID(port->id)] = port; 1436 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); 1437 1438 platform_set_drvdata(pdev, dev); 1439 1440 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1441 &port->regs->core_control); 1442 udelay(50); 1443 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1444 udelay(50); 1445 1446 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, 1447 mdio_bus->id, plat->phy); 1448 phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 1449 PHY_INTERFACE_MODE_MII); 1450 if (IS_ERR(phydev)) { 1451 err = PTR_ERR(phydev); 1452 goto err_free_mem; 1453 } 1454 1455 phydev->irq = PHY_POLL; 1456 1457 if ((err = register_netdev(dev))) 1458 goto err_phy_dis; 1459 1460 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, 1461 npe_name(port->npe)); 1462 1463 return 0; 1464 1465 err_phy_dis: 1466 phy_disconnect(phydev); 1467 err_free_mem: 1468 npe_port_tab[NPE_ID(port->id)] = NULL; 1469 release_resource(port->mem_res); 1470 err_npe_rel: 1471 npe_release(port->npe); 1472 err_free: 1473 free_netdev(dev); 1474 return err; 1475 } 1476 1477 static int eth_remove_one(struct platform_device *pdev) 1478 { 1479 struct net_device *dev = platform_get_drvdata(pdev); 1480 struct phy_device *phydev = dev->phydev; 1481 struct port *port = netdev_priv(dev); 1482 1483 unregister_netdev(dev); 1484 phy_disconnect(phydev); 1485 npe_port_tab[NPE_ID(port->id)] = NULL; 1486 npe_release(port->npe); 1487 release_resource(port->mem_res); 1488 free_netdev(dev); 1489 return 0; 1490 } 1491 1492 static struct platform_driver ixp4xx_eth_driver = { 1493 .driver.name = DRV_NAME, 1494 .probe = eth_init_one, 1495 .remove = eth_remove_one, 1496 }; 1497 1498 static int __init eth_init_module(void) 1499 { 1500 int err; 1501 1502 /* 1503 * FIXME: we bail out on device tree boot but this really needs 1504 * to be fixed in a nicer way: this registers the MDIO bus before 1505 * even matching the driver infrastructure, we should only probe 1506 * detected hardware. 1507 */ 1508 if (of_have_populated_dt()) 1509 return -ENODEV; 1510 if ((err = ixp4xx_mdio_register())) 1511 return err; 1512 return platform_driver_register(&ixp4xx_eth_driver); 1513 } 1514 1515 static void __exit eth_cleanup_module(void) 1516 { 1517 platform_driver_unregister(&ixp4xx_eth_driver); 1518 ixp4xx_mdio_remove(); 1519 } 1520 1521 MODULE_AUTHOR("Krzysztof Halasa"); 1522 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1523 MODULE_LICENSE("GPL v2"); 1524 MODULE_ALIAS("platform:ixp4xx_eth"); 1525 module_init(eth_init_module); 1526 module_exit(eth_cleanup_module); 1527