1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx Ethernet driver for Linux 4 * 5 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Ethernet port config (0x00 is not present on IXP42X): 8 * 9 * logical port 0x00 0x10 0x20 10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 11 * physical PortId 2 0 1 12 * TX queue 23 24 25 13 * RX-free queue 26 27 28 14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 15 * 16 * Queue entries: 17 * bits 0 -> 1 - NPE ID (RX and TX-done) 18 * bits 0 -> 2 - priority (TX, per 802.1D) 19 * bits 3 -> 4 - port ID (user-set?) 20 * bits 5 -> 31 - physical descriptor address 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmapool.h> 26 #include <linux/etherdevice.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/net_tstamp.h> 30 #include <linux/of.h> 31 #include <linux/of_mdio.h> 32 #include <linux/phy.h> 33 #include <linux/platform_data/eth_ixp4xx.h> 34 #include <linux/platform_device.h> 35 #include <linux/ptp_classify.h> 36 #include <linux/slab.h> 37 #include <linux/module.h> 38 #include <linux/soc/ixp4xx/npe.h> 39 #include <linux/soc/ixp4xx/qmgr.h> 40 #include <mach/hardware.h> 41 #include <linux/soc/ixp4xx/cpu.h> 42 43 #include "ixp46x_ts.h" 44 45 #define DEBUG_DESC 0 46 #define DEBUG_RX 0 47 #define DEBUG_TX 0 48 #define DEBUG_PKT_BYTES 0 49 #define DEBUG_MDIO 0 50 #define DEBUG_CLOSE 0 51 52 #define DRV_NAME "ixp4xx_eth" 53 54 #define MAX_NPES 3 55 56 #define RX_DESCS 64 /* also length of all RX queues */ 57 #define TX_DESCS 16 /* also length of all TX queues */ 58 #define TXDONE_QUEUE_LEN 64 /* dwords */ 59 60 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 61 #define REGS_SIZE 0x1000 62 #define MAX_MRU 1536 /* 0x600 */ 63 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 64 65 #define NAPI_WEIGHT 16 66 #define MDIO_INTERVAL (3 * HZ) 67 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 68 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 69 70 #define NPE_ID(port_id) ((port_id) >> 4) 71 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 72 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 73 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 74 #define TXDONE_QUEUE 31 75 76 #define PTP_SLAVE_MODE 1 77 #define PTP_MASTER_MODE 2 78 #define PORT2CHANNEL(p) NPE_ID(p->id) 79 80 /* TX Control Registers */ 81 #define TX_CNTRL0_TX_EN 0x01 82 #define TX_CNTRL0_HALFDUPLEX 0x02 83 #define TX_CNTRL0_RETRY 0x04 84 #define TX_CNTRL0_PAD_EN 0x08 85 #define TX_CNTRL0_APPEND_FCS 0x10 86 #define TX_CNTRL0_2DEFER 0x20 87 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 88 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 89 90 /* RX Control Registers */ 91 #define RX_CNTRL0_RX_EN 0x01 92 #define RX_CNTRL0_PADSTRIP_EN 0x02 93 #define RX_CNTRL0_SEND_FCS 0x04 94 #define RX_CNTRL0_PAUSE_EN 0x08 95 #define RX_CNTRL0_LOOP_EN 0x10 96 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 97 #define RX_CNTRL0_RX_RUNT_EN 0x40 98 #define RX_CNTRL0_BCAST_DIS 0x80 99 #define RX_CNTRL1_DEFER_EN 0x01 100 101 /* Core Control Register */ 102 #define CORE_RESET 0x01 103 #define CORE_RX_FIFO_FLUSH 0x02 104 #define CORE_TX_FIFO_FLUSH 0x04 105 #define CORE_SEND_JAM 0x08 106 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 107 108 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 109 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 110 TX_CNTRL0_2DEFER) 111 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 112 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 113 114 115 /* NPE message codes */ 116 #define NPE_GETSTATUS 0x00 117 #define NPE_EDB_SETPORTADDRESS 0x01 118 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 119 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 120 #define NPE_GETSTATS 0x04 121 #define NPE_RESETSTATS 0x05 122 #define NPE_SETMAXFRAMELENGTHS 0x06 123 #define NPE_VLAN_SETRXTAGMODE 0x07 124 #define NPE_VLAN_SETDEFAULTRXVID 0x08 125 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 126 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 127 #define NPE_VLAN_SETRXQOSENTRY 0x0B 128 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 129 #define NPE_STP_SETBLOCKINGSTATE 0x0D 130 #define NPE_FW_SETFIREWALLMODE 0x0E 131 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 132 #define NPE_PC_SETAPMACTABLE 0x11 133 #define NPE_SETLOOPBACK_MODE 0x12 134 #define NPE_PC_SETBSSIDTABLE 0x13 135 #define NPE_ADDRESS_FILTER_CONFIG 0x14 136 #define NPE_APPENDFCSCONFIG 0x15 137 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 138 #define NPE_MAC_RECOVERY_START 0x17 139 140 141 #ifdef __ARMEB__ 142 typedef struct sk_buff buffer_t; 143 #define free_buffer dev_kfree_skb 144 #define free_buffer_irq dev_consume_skb_irq 145 #else 146 typedef void buffer_t; 147 #define free_buffer kfree 148 #define free_buffer_irq kfree 149 #endif 150 151 struct eth_regs { 152 u32 tx_control[2], __res1[2]; /* 000 */ 153 u32 rx_control[2], __res2[2]; /* 010 */ 154 u32 random_seed, __res3[3]; /* 020 */ 155 u32 partial_empty_threshold, __res4; /* 030 */ 156 u32 partial_full_threshold, __res5; /* 038 */ 157 u32 tx_start_bytes, __res6[3]; /* 040 */ 158 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 159 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 160 u32 slot_time, __res9[3]; /* 070 */ 161 u32 mdio_command[4]; /* 080 */ 162 u32 mdio_status[4]; /* 090 */ 163 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 164 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 165 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 166 u32 hw_addr[6], __res13[61]; /* 0F0 */ 167 u32 core_control; /* 1FC */ 168 }; 169 170 struct port { 171 struct eth_regs __iomem *regs; 172 struct npe *npe; 173 struct net_device *netdev; 174 struct napi_struct napi; 175 struct eth_plat_info *plat; 176 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 177 struct desc *desc_tab; /* coherent */ 178 u32 desc_tab_phys; 179 int id; /* logical port ID */ 180 int speed, duplex; 181 u8 firmware[4]; 182 int hwts_tx_en; 183 int hwts_rx_en; 184 }; 185 186 /* NPE message structure */ 187 struct msg { 188 #ifdef __ARMEB__ 189 u8 cmd, eth_id, byte2, byte3; 190 u8 byte4, byte5, byte6, byte7; 191 #else 192 u8 byte3, byte2, eth_id, cmd; 193 u8 byte7, byte6, byte5, byte4; 194 #endif 195 }; 196 197 /* Ethernet packet descriptor */ 198 struct desc { 199 u32 next; /* pointer to next buffer, unused */ 200 201 #ifdef __ARMEB__ 202 u16 buf_len; /* buffer length */ 203 u16 pkt_len; /* packet length */ 204 u32 data; /* pointer to data buffer in RAM */ 205 u8 dest_id; 206 u8 src_id; 207 u16 flags; 208 u8 qos; 209 u8 padlen; 210 u16 vlan_tci; 211 #else 212 u16 pkt_len; /* packet length */ 213 u16 buf_len; /* buffer length */ 214 u32 data; /* pointer to data buffer in RAM */ 215 u16 flags; 216 u8 src_id; 217 u8 dest_id; 218 u16 vlan_tci; 219 u8 padlen; 220 u8 qos; 221 #endif 222 223 #ifdef __ARMEB__ 224 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 225 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 226 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 227 #else 228 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 229 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 230 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 231 #endif 232 }; 233 234 235 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 236 (n) * sizeof(struct desc)) 237 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 238 239 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 240 ((n) + RX_DESCS) * sizeof(struct desc)) 241 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 242 243 #ifndef __ARMEB__ 244 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 245 { 246 int i; 247 for (i = 0; i < cnt; i++) 248 dest[i] = swab32(src[i]); 249 } 250 #endif 251 252 static DEFINE_SPINLOCK(mdio_lock); 253 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 254 static struct mii_bus *mdio_bus; 255 static struct device_node *mdio_bus_np; 256 static int ports_open; 257 static struct port *npe_port_tab[MAX_NPES]; 258 static struct dma_pool *dma_pool; 259 260 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 261 { 262 u8 *data = skb->data; 263 unsigned int offset; 264 u16 *hi, *id; 265 u32 lo; 266 267 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 268 return 0; 269 270 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 271 272 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 273 return 0; 274 275 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 276 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 277 278 memcpy(&lo, &hi[1], sizeof(lo)); 279 280 return (uid_hi == ntohs(*hi) && 281 uid_lo == ntohl(lo) && 282 seqid == ntohs(*id)); 283 } 284 285 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 286 { 287 struct skb_shared_hwtstamps *shhwtstamps; 288 struct ixp46x_ts_regs *regs; 289 u64 ns; 290 u32 ch, hi, lo, val; 291 u16 uid, seq; 292 293 if (!port->hwts_rx_en) 294 return; 295 296 ch = PORT2CHANNEL(port); 297 298 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 299 300 val = __raw_readl(®s->channel[ch].ch_event); 301 302 if (!(val & RX_SNAPSHOT_LOCKED)) 303 return; 304 305 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 306 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 307 308 uid = hi & 0xffff; 309 seq = (hi >> 16) & 0xffff; 310 311 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 312 goto out; 313 314 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 315 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 316 ns = ((u64) hi) << 32; 317 ns |= lo; 318 ns <<= TICKS_NS_SHIFT; 319 320 shhwtstamps = skb_hwtstamps(skb); 321 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 322 shhwtstamps->hwtstamp = ns_to_ktime(ns); 323 out: 324 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 325 } 326 327 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 328 { 329 struct skb_shared_hwtstamps shhwtstamps; 330 struct ixp46x_ts_regs *regs; 331 struct skb_shared_info *shtx; 332 u64 ns; 333 u32 ch, cnt, hi, lo, val; 334 335 shtx = skb_shinfo(skb); 336 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 337 shtx->tx_flags |= SKBTX_IN_PROGRESS; 338 else 339 return; 340 341 ch = PORT2CHANNEL(port); 342 343 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 344 345 /* 346 * This really stinks, but we have to poll for the Tx time stamp. 347 * Usually, the time stamp is ready after 4 to 6 microseconds. 348 */ 349 for (cnt = 0; cnt < 100; cnt++) { 350 val = __raw_readl(®s->channel[ch].ch_event); 351 if (val & TX_SNAPSHOT_LOCKED) 352 break; 353 udelay(1); 354 } 355 if (!(val & TX_SNAPSHOT_LOCKED)) { 356 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 357 return; 358 } 359 360 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 361 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 362 ns = ((u64) hi) << 32; 363 ns |= lo; 364 ns <<= TICKS_NS_SHIFT; 365 366 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 367 shhwtstamps.hwtstamp = ns_to_ktime(ns); 368 skb_tstamp_tx(skb, &shhwtstamps); 369 370 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 371 } 372 373 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 374 { 375 struct hwtstamp_config cfg; 376 struct ixp46x_ts_regs *regs; 377 struct port *port = netdev_priv(netdev); 378 int ch; 379 380 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 381 return -EFAULT; 382 383 if (cfg.flags) /* reserved for future extensions */ 384 return -EINVAL; 385 386 ch = PORT2CHANNEL(port); 387 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; 388 389 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 390 return -ERANGE; 391 392 switch (cfg.rx_filter) { 393 case HWTSTAMP_FILTER_NONE: 394 port->hwts_rx_en = 0; 395 break; 396 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 397 port->hwts_rx_en = PTP_SLAVE_MODE; 398 __raw_writel(0, ®s->channel[ch].ch_control); 399 break; 400 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 401 port->hwts_rx_en = PTP_MASTER_MODE; 402 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 403 break; 404 default: 405 return -ERANGE; 406 } 407 408 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 409 410 /* Clear out any old time stamps. */ 411 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 412 ®s->channel[ch].ch_event); 413 414 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 415 } 416 417 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 418 { 419 struct hwtstamp_config cfg; 420 struct port *port = netdev_priv(netdev); 421 422 cfg.flags = 0; 423 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 424 425 switch (port->hwts_rx_en) { 426 case 0: 427 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 428 break; 429 case PTP_SLAVE_MODE: 430 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 431 break; 432 case PTP_MASTER_MODE: 433 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 434 break; 435 default: 436 WARN_ON_ONCE(1); 437 return -ERANGE; 438 } 439 440 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 441 } 442 443 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 444 int write, u16 cmd) 445 { 446 int cycles = 0; 447 448 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 449 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 450 return -1; 451 } 452 453 if (write) { 454 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 455 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 456 } 457 __raw_writel(((phy_id << 5) | location) & 0xFF, 458 &mdio_regs->mdio_command[2]); 459 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 460 &mdio_regs->mdio_command[3]); 461 462 while ((cycles < MAX_MDIO_RETRIES) && 463 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 464 udelay(1); 465 cycles++; 466 } 467 468 if (cycles == MAX_MDIO_RETRIES) { 469 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 470 phy_id); 471 return -1; 472 } 473 474 #if DEBUG_MDIO 475 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 476 phy_id, write ? "write" : "read", cycles); 477 #endif 478 479 if (write) 480 return 0; 481 482 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 483 #if DEBUG_MDIO 484 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 485 phy_id); 486 #endif 487 return 0xFFFF; /* don't return error */ 488 } 489 490 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 491 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 492 } 493 494 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 495 { 496 unsigned long flags; 497 int ret; 498 499 spin_lock_irqsave(&mdio_lock, flags); 500 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 501 spin_unlock_irqrestore(&mdio_lock, flags); 502 #if DEBUG_MDIO 503 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 504 phy_id, location, ret); 505 #endif 506 return ret; 507 } 508 509 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 510 u16 val) 511 { 512 unsigned long flags; 513 int ret; 514 515 spin_lock_irqsave(&mdio_lock, flags); 516 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 517 spin_unlock_irqrestore(&mdio_lock, flags); 518 #if DEBUG_MDIO 519 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 520 bus->name, phy_id, location, val, ret); 521 #endif 522 return ret; 523 } 524 525 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) 526 { 527 int err; 528 529 if (!(mdio_bus = mdiobus_alloc())) 530 return -ENOMEM; 531 532 mdio_regs = regs; 533 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 534 mdio_bus->name = "IXP4xx MII Bus"; 535 mdio_bus->read = &ixp4xx_mdio_read; 536 mdio_bus->write = &ixp4xx_mdio_write; 537 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 538 539 err = of_mdiobus_register(mdio_bus, mdio_bus_np); 540 if (err) 541 mdiobus_free(mdio_bus); 542 return err; 543 } 544 545 static void ixp4xx_mdio_remove(void) 546 { 547 mdiobus_unregister(mdio_bus); 548 mdiobus_free(mdio_bus); 549 } 550 551 552 static void ixp4xx_adjust_link(struct net_device *dev) 553 { 554 struct port *port = netdev_priv(dev); 555 struct phy_device *phydev = dev->phydev; 556 557 if (!phydev->link) { 558 if (port->speed) { 559 port->speed = 0; 560 printk(KERN_INFO "%s: link down\n", dev->name); 561 } 562 return; 563 } 564 565 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 566 return; 567 568 port->speed = phydev->speed; 569 port->duplex = phydev->duplex; 570 571 if (port->duplex) 572 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 573 &port->regs->tx_control[0]); 574 else 575 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 576 &port->regs->tx_control[0]); 577 578 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n", 579 dev->name, port->speed, port->duplex ? "full" : "half"); 580 } 581 582 583 static inline void debug_pkt(struct net_device *dev, const char *func, 584 u8 *data, int len) 585 { 586 #if DEBUG_PKT_BYTES 587 int i; 588 589 netdev_debug(dev, "%s(%i) ", func, len); 590 for (i = 0; i < len; i++) { 591 if (i >= DEBUG_PKT_BYTES) 592 break; 593 printk("%s%02X", 594 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 595 data[i]); 596 } 597 printk("\n"); 598 #endif 599 } 600 601 602 static inline void debug_desc(u32 phys, struct desc *desc) 603 { 604 #if DEBUG_DESC 605 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 606 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 607 phys, desc->next, desc->buf_len, desc->pkt_len, 608 desc->data, desc->dest_id, desc->src_id, desc->flags, 609 desc->qos, desc->padlen, desc->vlan_tci, 610 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 611 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 612 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 613 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 614 #endif 615 } 616 617 static inline int queue_get_desc(unsigned int queue, struct port *port, 618 int is_tx) 619 { 620 u32 phys, tab_phys, n_desc; 621 struct desc *tab; 622 623 if (!(phys = qmgr_get_entry(queue))) 624 return -1; 625 626 phys &= ~0x1F; /* mask out non-address bits */ 627 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 628 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 629 n_desc = (phys - tab_phys) / sizeof(struct desc); 630 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 631 debug_desc(phys, &tab[n_desc]); 632 BUG_ON(tab[n_desc].next); 633 return n_desc; 634 } 635 636 static inline void queue_put_desc(unsigned int queue, u32 phys, 637 struct desc *desc) 638 { 639 debug_desc(phys, desc); 640 BUG_ON(phys & 0x1F); 641 qmgr_put_entry(queue, phys); 642 /* Don't check for queue overflow here, we've allocated sufficient 643 length and queues >= 32 don't support this check anyway. */ 644 } 645 646 647 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 648 { 649 #ifdef __ARMEB__ 650 dma_unmap_single(&port->netdev->dev, desc->data, 651 desc->buf_len, DMA_TO_DEVICE); 652 #else 653 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 654 ALIGN((desc->data & 3) + desc->buf_len, 4), 655 DMA_TO_DEVICE); 656 #endif 657 } 658 659 660 static void eth_rx_irq(void *pdev) 661 { 662 struct net_device *dev = pdev; 663 struct port *port = netdev_priv(dev); 664 665 #if DEBUG_RX 666 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 667 #endif 668 qmgr_disable_irq(port->plat->rxq); 669 napi_schedule(&port->napi); 670 } 671 672 static int eth_poll(struct napi_struct *napi, int budget) 673 { 674 struct port *port = container_of(napi, struct port, napi); 675 struct net_device *dev = port->netdev; 676 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 677 int received = 0; 678 679 #if DEBUG_RX 680 netdev_debug(dev, "eth_poll\n"); 681 #endif 682 683 while (received < budget) { 684 struct sk_buff *skb; 685 struct desc *desc; 686 int n; 687 #ifdef __ARMEB__ 688 struct sk_buff *temp; 689 u32 phys; 690 #endif 691 692 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 693 #if DEBUG_RX 694 netdev_debug(dev, "eth_poll napi_complete\n"); 695 #endif 696 napi_complete(napi); 697 qmgr_enable_irq(rxq); 698 if (!qmgr_stat_below_low_watermark(rxq) && 699 napi_reschedule(napi)) { /* not empty again */ 700 #if DEBUG_RX 701 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n"); 702 #endif 703 qmgr_disable_irq(rxq); 704 continue; 705 } 706 #if DEBUG_RX 707 netdev_debug(dev, "eth_poll all done\n"); 708 #endif 709 return received; /* all work done */ 710 } 711 712 desc = rx_desc_ptr(port, n); 713 714 #ifdef __ARMEB__ 715 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 716 phys = dma_map_single(&dev->dev, skb->data, 717 RX_BUFF_SIZE, DMA_FROM_DEVICE); 718 if (dma_mapping_error(&dev->dev, phys)) { 719 dev_kfree_skb(skb); 720 skb = NULL; 721 } 722 } 723 #else 724 skb = netdev_alloc_skb(dev, 725 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 726 #endif 727 728 if (!skb) { 729 dev->stats.rx_dropped++; 730 /* put the desc back on RX-ready queue */ 731 desc->buf_len = MAX_MRU; 732 desc->pkt_len = 0; 733 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 734 continue; 735 } 736 737 /* process received frame */ 738 #ifdef __ARMEB__ 739 temp = skb; 740 skb = port->rx_buff_tab[n]; 741 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 742 RX_BUFF_SIZE, DMA_FROM_DEVICE); 743 #else 744 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 745 RX_BUFF_SIZE, DMA_FROM_DEVICE); 746 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 747 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 748 #endif 749 skb_reserve(skb, NET_IP_ALIGN); 750 skb_put(skb, desc->pkt_len); 751 752 debug_pkt(dev, "eth_poll", skb->data, skb->len); 753 754 ixp_rx_timestamp(port, skb); 755 skb->protocol = eth_type_trans(skb, dev); 756 dev->stats.rx_packets++; 757 dev->stats.rx_bytes += skb->len; 758 netif_receive_skb(skb); 759 760 /* put the new buffer on RX-free queue */ 761 #ifdef __ARMEB__ 762 port->rx_buff_tab[n] = temp; 763 desc->data = phys + NET_IP_ALIGN; 764 #endif 765 desc->buf_len = MAX_MRU; 766 desc->pkt_len = 0; 767 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 768 received++; 769 } 770 771 #if DEBUG_RX 772 netdev_debug(dev, "eth_poll(): end, not all work done\n"); 773 #endif 774 return received; /* not all work done */ 775 } 776 777 778 static void eth_txdone_irq(void *unused) 779 { 780 u32 phys; 781 782 #if DEBUG_TX 783 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 784 #endif 785 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 786 u32 npe_id, n_desc; 787 struct port *port; 788 struct desc *desc; 789 int start; 790 791 npe_id = phys & 3; 792 BUG_ON(npe_id >= MAX_NPES); 793 port = npe_port_tab[npe_id]; 794 BUG_ON(!port); 795 phys &= ~0x1F; /* mask out non-address bits */ 796 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 797 BUG_ON(n_desc >= TX_DESCS); 798 desc = tx_desc_ptr(port, n_desc); 799 debug_desc(phys, desc); 800 801 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 802 port->netdev->stats.tx_packets++; 803 port->netdev->stats.tx_bytes += desc->pkt_len; 804 805 dma_unmap_tx(port, desc); 806 #if DEBUG_TX 807 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 808 port->netdev->name, port->tx_buff_tab[n_desc]); 809 #endif 810 free_buffer_irq(port->tx_buff_tab[n_desc]); 811 port->tx_buff_tab[n_desc] = NULL; 812 } 813 814 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 815 queue_put_desc(port->plat->txreadyq, phys, desc); 816 if (start) { /* TX-ready queue was empty */ 817 #if DEBUG_TX 818 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 819 port->netdev->name); 820 #endif 821 netif_wake_queue(port->netdev); 822 } 823 } 824 } 825 826 static int eth_xmit(struct sk_buff *skb, struct net_device *dev) 827 { 828 struct port *port = netdev_priv(dev); 829 unsigned int txreadyq = port->plat->txreadyq; 830 int len, offset, bytes, n; 831 void *mem; 832 u32 phys; 833 struct desc *desc; 834 835 #if DEBUG_TX 836 netdev_debug(dev, "eth_xmit\n"); 837 #endif 838 839 if (unlikely(skb->len > MAX_MRU)) { 840 dev_kfree_skb(skb); 841 dev->stats.tx_errors++; 842 return NETDEV_TX_OK; 843 } 844 845 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 846 847 len = skb->len; 848 #ifdef __ARMEB__ 849 offset = 0; /* no need to keep alignment */ 850 bytes = len; 851 mem = skb->data; 852 #else 853 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 854 bytes = ALIGN(offset + len, 4); 855 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 856 dev_kfree_skb(skb); 857 dev->stats.tx_dropped++; 858 return NETDEV_TX_OK; 859 } 860 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); 861 #endif 862 863 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 864 if (dma_mapping_error(&dev->dev, phys)) { 865 dev_kfree_skb(skb); 866 #ifndef __ARMEB__ 867 kfree(mem); 868 #endif 869 dev->stats.tx_dropped++; 870 return NETDEV_TX_OK; 871 } 872 873 n = queue_get_desc(txreadyq, port, 1); 874 BUG_ON(n < 0); 875 desc = tx_desc_ptr(port, n); 876 877 #ifdef __ARMEB__ 878 port->tx_buff_tab[n] = skb; 879 #else 880 port->tx_buff_tab[n] = mem; 881 #endif 882 desc->data = phys + offset; 883 desc->buf_len = desc->pkt_len = len; 884 885 /* NPE firmware pads short frames with zeros internally */ 886 wmb(); 887 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 888 889 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 890 #if DEBUG_TX 891 netdev_debug(dev, "eth_xmit queue full\n"); 892 #endif 893 netif_stop_queue(dev); 894 /* we could miss TX ready interrupt */ 895 /* really empty in fact */ 896 if (!qmgr_stat_below_low_watermark(txreadyq)) { 897 #if DEBUG_TX 898 netdev_debug(dev, "eth_xmit ready again\n"); 899 #endif 900 netif_wake_queue(dev); 901 } 902 } 903 904 #if DEBUG_TX 905 netdev_debug(dev, "eth_xmit end\n"); 906 #endif 907 908 ixp_tx_timestamp(port, skb); 909 skb_tx_timestamp(skb); 910 911 #ifndef __ARMEB__ 912 dev_kfree_skb(skb); 913 #endif 914 return NETDEV_TX_OK; 915 } 916 917 918 static void eth_set_mcast_list(struct net_device *dev) 919 { 920 struct port *port = netdev_priv(dev); 921 struct netdev_hw_addr *ha; 922 u8 diffs[ETH_ALEN], *addr; 923 int i; 924 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 925 926 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) { 927 for (i = 0; i < ETH_ALEN; i++) { 928 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 929 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 930 } 931 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 932 &port->regs->rx_control[0]); 933 return; 934 } 935 936 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 937 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 938 &port->regs->rx_control[0]); 939 return; 940 } 941 942 eth_zero_addr(diffs); 943 944 addr = NULL; 945 netdev_for_each_mc_addr(ha, dev) { 946 if (!addr) 947 addr = ha->addr; /* first MAC address */ 948 for (i = 0; i < ETH_ALEN; i++) 949 diffs[i] |= addr[i] ^ ha->addr[i]; 950 } 951 952 for (i = 0; i < ETH_ALEN; i++) { 953 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 954 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 955 } 956 957 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 958 &port->regs->rx_control[0]); 959 } 960 961 962 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 963 { 964 if (!netif_running(dev)) 965 return -EINVAL; 966 967 if (cpu_is_ixp46x()) { 968 if (cmd == SIOCSHWTSTAMP) 969 return hwtstamp_set(dev, req); 970 if (cmd == SIOCGHWTSTAMP) 971 return hwtstamp_get(dev, req); 972 } 973 974 return phy_mii_ioctl(dev->phydev, req, cmd); 975 } 976 977 /* ethtool support */ 978 979 static void ixp4xx_get_drvinfo(struct net_device *dev, 980 struct ethtool_drvinfo *info) 981 { 982 struct port *port = netdev_priv(dev); 983 984 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 985 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 986 port->firmware[0], port->firmware[1], 987 port->firmware[2], port->firmware[3]); 988 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 989 } 990 991 int ixp46x_phc_index = -1; 992 EXPORT_SYMBOL_GPL(ixp46x_phc_index); 993 994 static int ixp4xx_get_ts_info(struct net_device *dev, 995 struct ethtool_ts_info *info) 996 { 997 if (!cpu_is_ixp46x()) { 998 info->so_timestamping = 999 SOF_TIMESTAMPING_TX_SOFTWARE | 1000 SOF_TIMESTAMPING_RX_SOFTWARE | 1001 SOF_TIMESTAMPING_SOFTWARE; 1002 info->phc_index = -1; 1003 return 0; 1004 } 1005 info->so_timestamping = 1006 SOF_TIMESTAMPING_TX_HARDWARE | 1007 SOF_TIMESTAMPING_RX_HARDWARE | 1008 SOF_TIMESTAMPING_RAW_HARDWARE; 1009 info->phc_index = ixp46x_phc_index; 1010 info->tx_types = 1011 (1 << HWTSTAMP_TX_OFF) | 1012 (1 << HWTSTAMP_TX_ON); 1013 info->rx_filters = 1014 (1 << HWTSTAMP_FILTER_NONE) | 1015 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1016 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1017 return 0; 1018 } 1019 1020 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1021 .get_drvinfo = ixp4xx_get_drvinfo, 1022 .nway_reset = phy_ethtool_nway_reset, 1023 .get_link = ethtool_op_get_link, 1024 .get_ts_info = ixp4xx_get_ts_info, 1025 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1026 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1027 }; 1028 1029 1030 static int request_queues(struct port *port) 1031 { 1032 int err; 1033 1034 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1035 "%s:RX-free", port->netdev->name); 1036 if (err) 1037 return err; 1038 1039 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1040 "%s:RX", port->netdev->name); 1041 if (err) 1042 goto rel_rxfree; 1043 1044 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1045 "%s:TX", port->netdev->name); 1046 if (err) 1047 goto rel_rx; 1048 1049 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1050 "%s:TX-ready", port->netdev->name); 1051 if (err) 1052 goto rel_tx; 1053 1054 /* TX-done queue handles skbs sent out by the NPEs */ 1055 if (!ports_open) { 1056 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1057 "%s:TX-done", DRV_NAME); 1058 if (err) 1059 goto rel_txready; 1060 } 1061 return 0; 1062 1063 rel_txready: 1064 qmgr_release_queue(port->plat->txreadyq); 1065 rel_tx: 1066 qmgr_release_queue(TX_QUEUE(port->id)); 1067 rel_rx: 1068 qmgr_release_queue(port->plat->rxq); 1069 rel_rxfree: 1070 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1071 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1072 port->netdev->name); 1073 return err; 1074 } 1075 1076 static void release_queues(struct port *port) 1077 { 1078 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1079 qmgr_release_queue(port->plat->rxq); 1080 qmgr_release_queue(TX_QUEUE(port->id)); 1081 qmgr_release_queue(port->plat->txreadyq); 1082 1083 if (!ports_open) 1084 qmgr_release_queue(TXDONE_QUEUE); 1085 } 1086 1087 static int init_queues(struct port *port) 1088 { 1089 int i; 1090 1091 if (!ports_open) { 1092 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1093 POOL_ALLOC_SIZE, 32, 0); 1094 if (!dma_pool) 1095 return -ENOMEM; 1096 } 1097 1098 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, 1099 &port->desc_tab_phys))) 1100 return -ENOMEM; 1101 memset(port->desc_tab, 0, POOL_ALLOC_SIZE); 1102 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1103 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1104 1105 /* Setup RX buffers */ 1106 for (i = 0; i < RX_DESCS; i++) { 1107 struct desc *desc = rx_desc_ptr(port, i); 1108 buffer_t *buff; /* skb or kmalloc()ated memory */ 1109 void *data; 1110 #ifdef __ARMEB__ 1111 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1112 return -ENOMEM; 1113 data = buff->data; 1114 #else 1115 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1116 return -ENOMEM; 1117 data = buff; 1118 #endif 1119 desc->buf_len = MAX_MRU; 1120 desc->data = dma_map_single(&port->netdev->dev, data, 1121 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1122 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1123 free_buffer(buff); 1124 return -EIO; 1125 } 1126 desc->data += NET_IP_ALIGN; 1127 port->rx_buff_tab[i] = buff; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static void destroy_queues(struct port *port) 1134 { 1135 int i; 1136 1137 if (port->desc_tab) { 1138 for (i = 0; i < RX_DESCS; i++) { 1139 struct desc *desc = rx_desc_ptr(port, i); 1140 buffer_t *buff = port->rx_buff_tab[i]; 1141 if (buff) { 1142 dma_unmap_single(&port->netdev->dev, 1143 desc->data - NET_IP_ALIGN, 1144 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1145 free_buffer(buff); 1146 } 1147 } 1148 for (i = 0; i < TX_DESCS; i++) { 1149 struct desc *desc = tx_desc_ptr(port, i); 1150 buffer_t *buff = port->tx_buff_tab[i]; 1151 if (buff) { 1152 dma_unmap_tx(port, desc); 1153 free_buffer(buff); 1154 } 1155 } 1156 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1157 port->desc_tab = NULL; 1158 } 1159 1160 if (!ports_open && dma_pool) { 1161 dma_pool_destroy(dma_pool); 1162 dma_pool = NULL; 1163 } 1164 } 1165 1166 static int eth_open(struct net_device *dev) 1167 { 1168 struct port *port = netdev_priv(dev); 1169 struct npe *npe = port->npe; 1170 struct msg msg; 1171 int i, err; 1172 1173 if (!npe_running(npe)) { 1174 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1175 if (err) 1176 return err; 1177 1178 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1179 netdev_err(dev, "%s not responding\n", npe_name(npe)); 1180 return -EIO; 1181 } 1182 port->firmware[0] = msg.byte4; 1183 port->firmware[1] = msg.byte5; 1184 port->firmware[2] = msg.byte6; 1185 port->firmware[3] = msg.byte7; 1186 } 1187 1188 memset(&msg, 0, sizeof(msg)); 1189 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1190 msg.eth_id = port->id; 1191 msg.byte5 = port->plat->rxq | 0x80; 1192 msg.byte7 = port->plat->rxq << 4; 1193 for (i = 0; i < 8; i++) { 1194 msg.byte3 = i; 1195 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1196 return -EIO; 1197 } 1198 1199 msg.cmd = NPE_EDB_SETPORTADDRESS; 1200 msg.eth_id = PHYSICAL_ID(port->id); 1201 msg.byte2 = dev->dev_addr[0]; 1202 msg.byte3 = dev->dev_addr[1]; 1203 msg.byte4 = dev->dev_addr[2]; 1204 msg.byte5 = dev->dev_addr[3]; 1205 msg.byte6 = dev->dev_addr[4]; 1206 msg.byte7 = dev->dev_addr[5]; 1207 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1208 return -EIO; 1209 1210 memset(&msg, 0, sizeof(msg)); 1211 msg.cmd = NPE_FW_SETFIREWALLMODE; 1212 msg.eth_id = port->id; 1213 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1214 return -EIO; 1215 1216 if ((err = request_queues(port)) != 0) 1217 return err; 1218 1219 if ((err = init_queues(port)) != 0) { 1220 destroy_queues(port); 1221 release_queues(port); 1222 return err; 1223 } 1224 1225 port->speed = 0; /* force "link up" message */ 1226 phy_start(dev->phydev); 1227 1228 for (i = 0; i < ETH_ALEN; i++) 1229 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1230 __raw_writel(0x08, &port->regs->random_seed); 1231 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1232 __raw_writel(0x30, &port->regs->partial_full_threshold); 1233 __raw_writel(0x08, &port->regs->tx_start_bytes); 1234 __raw_writel(0x15, &port->regs->tx_deferral); 1235 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1236 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1237 __raw_writel(0x80, &port->regs->slot_time); 1238 __raw_writel(0x01, &port->regs->int_clock_threshold); 1239 1240 /* Populate queues with buffers, no failure after this point */ 1241 for (i = 0; i < TX_DESCS; i++) 1242 queue_put_desc(port->plat->txreadyq, 1243 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1244 1245 for (i = 0; i < RX_DESCS; i++) 1246 queue_put_desc(RXFREE_QUEUE(port->id), 1247 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1248 1249 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1250 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1251 __raw_writel(0, &port->regs->rx_control[1]); 1252 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1253 1254 napi_enable(&port->napi); 1255 eth_set_mcast_list(dev); 1256 netif_start_queue(dev); 1257 1258 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1259 eth_rx_irq, dev); 1260 if (!ports_open) { 1261 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1262 eth_txdone_irq, NULL); 1263 qmgr_enable_irq(TXDONE_QUEUE); 1264 } 1265 ports_open++; 1266 /* we may already have RX data, enables IRQ */ 1267 napi_schedule(&port->napi); 1268 return 0; 1269 } 1270 1271 static int eth_close(struct net_device *dev) 1272 { 1273 struct port *port = netdev_priv(dev); 1274 struct msg msg; 1275 int buffs = RX_DESCS; /* allocated RX buffers */ 1276 int i; 1277 1278 ports_open--; 1279 qmgr_disable_irq(port->plat->rxq); 1280 napi_disable(&port->napi); 1281 netif_stop_queue(dev); 1282 1283 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1284 buffs--; 1285 1286 memset(&msg, 0, sizeof(msg)); 1287 msg.cmd = NPE_SETLOOPBACK_MODE; 1288 msg.eth_id = port->id; 1289 msg.byte3 = 1; 1290 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1291 netdev_crit(dev, "unable to enable loopback\n"); 1292 1293 i = 0; 1294 do { /* drain RX buffers */ 1295 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1296 buffs--; 1297 if (!buffs) 1298 break; 1299 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1300 /* we have to inject some packet */ 1301 struct desc *desc; 1302 u32 phys; 1303 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1304 BUG_ON(n < 0); 1305 desc = tx_desc_ptr(port, n); 1306 phys = tx_desc_phys(port, n); 1307 desc->buf_len = desc->pkt_len = 1; 1308 wmb(); 1309 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1310 } 1311 udelay(1); 1312 } while (++i < MAX_CLOSE_WAIT); 1313 1314 if (buffs) 1315 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)" 1316 " left in NPE\n", buffs); 1317 #if DEBUG_CLOSE 1318 if (!buffs) 1319 netdev_debug(dev, "draining RX queue took %i cycles\n", i); 1320 #endif 1321 1322 buffs = TX_DESCS; 1323 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1324 buffs--; /* cancel TX */ 1325 1326 i = 0; 1327 do { 1328 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1329 buffs--; 1330 if (!buffs) 1331 break; 1332 } while (++i < MAX_CLOSE_WAIT); 1333 1334 if (buffs) 1335 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) " 1336 "left in NPE\n", buffs); 1337 #if DEBUG_CLOSE 1338 if (!buffs) 1339 netdev_debug(dev, "draining TX queues took %i cycles\n", i); 1340 #endif 1341 1342 msg.byte3 = 0; 1343 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1344 netdev_crit(dev, "unable to disable loopback\n"); 1345 1346 phy_stop(dev->phydev); 1347 1348 if (!ports_open) 1349 qmgr_disable_irq(TXDONE_QUEUE); 1350 destroy_queues(port); 1351 release_queues(port); 1352 return 0; 1353 } 1354 1355 static const struct net_device_ops ixp4xx_netdev_ops = { 1356 .ndo_open = eth_open, 1357 .ndo_stop = eth_close, 1358 .ndo_start_xmit = eth_xmit, 1359 .ndo_set_rx_mode = eth_set_mcast_list, 1360 .ndo_do_ioctl = eth_ioctl, 1361 .ndo_set_mac_address = eth_mac_addr, 1362 .ndo_validate_addr = eth_validate_addr, 1363 }; 1364 1365 #ifdef CONFIG_OF 1366 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1367 { 1368 struct device_node *np = dev->of_node; 1369 struct of_phandle_args queue_spec; 1370 struct of_phandle_args npe_spec; 1371 struct device_node *mdio_np; 1372 struct eth_plat_info *plat; 1373 int ret; 1374 1375 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); 1376 if (!plat) 1377 return NULL; 1378 1379 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, 1380 &npe_spec); 1381 if (ret) { 1382 dev_err(dev, "no NPE engine specified\n"); 1383 return NULL; 1384 } 1385 /* NPE ID 0x00, 0x10, 0x20... */ 1386 plat->npe = (npe_spec.args[0] << 4); 1387 1388 /* Check if this device has an MDIO bus */ 1389 mdio_np = of_get_child_by_name(np, "mdio"); 1390 if (mdio_np) { 1391 plat->has_mdio = true; 1392 mdio_bus_np = mdio_np; 1393 /* DO NOT put the mdio_np, it will be used */ 1394 } 1395 1396 /* Get the rx queue as a resource from queue manager */ 1397 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, 1398 &queue_spec); 1399 if (ret) { 1400 dev_err(dev, "no rx queue phandle\n"); 1401 return NULL; 1402 } 1403 plat->rxq = queue_spec.args[0]; 1404 1405 /* Get the txready queue as resource from queue manager */ 1406 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, 1407 &queue_spec); 1408 if (ret) { 1409 dev_err(dev, "no txready queue phandle\n"); 1410 return NULL; 1411 } 1412 plat->txreadyq = queue_spec.args[0]; 1413 1414 return plat; 1415 } 1416 #else 1417 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1418 { 1419 return NULL; 1420 } 1421 #endif 1422 1423 static int ixp4xx_eth_probe(struct platform_device *pdev) 1424 { 1425 struct phy_device *phydev = NULL; 1426 struct device *dev = &pdev->dev; 1427 struct device_node *np = dev->of_node; 1428 struct eth_plat_info *plat; 1429 struct net_device *ndev; 1430 struct resource *res; 1431 struct port *port; 1432 int err; 1433 1434 if (np) { 1435 plat = ixp4xx_of_get_platdata(dev); 1436 if (!plat) 1437 return -ENODEV; 1438 } else { 1439 plat = dev_get_platdata(dev); 1440 if (!plat) 1441 return -ENODEV; 1442 plat->npe = pdev->id; 1443 switch (plat->npe) { 1444 case IXP4XX_ETH_NPEA: 1445 /* If the MDIO bus is not up yet, defer probe */ 1446 break; 1447 case IXP4XX_ETH_NPEB: 1448 /* On all except IXP43x, NPE-B is used for the MDIO bus. 1449 * If there is no NPE-B in the feature set, bail out, 1450 * else we have the MDIO bus here. 1451 */ 1452 if (!cpu_is_ixp43x()) { 1453 if (!(ixp4xx_read_feature_bits() & 1454 IXP4XX_FEATURE_NPEB_ETH0)) 1455 return -ENODEV; 1456 /* Else register the MDIO bus on NPE-B */ 1457 plat->has_mdio = true; 1458 } 1459 break; 1460 case IXP4XX_ETH_NPEC: 1461 /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus 1462 * access, if there is no NPE-C, no bus, nothing works, 1463 * so bail out. 1464 */ 1465 if (cpu_is_ixp43x()) { 1466 if (!(ixp4xx_read_feature_bits() & 1467 IXP4XX_FEATURE_NPEC_ETH)) 1468 return -ENODEV; 1469 /* Else register the MDIO bus on NPE-B */ 1470 plat->has_mdio = true; 1471 } 1472 break; 1473 default: 1474 return -ENODEV; 1475 } 1476 } 1477 1478 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) 1479 return -ENOMEM; 1480 1481 SET_NETDEV_DEV(ndev, dev); 1482 port = netdev_priv(ndev); 1483 port->netdev = ndev; 1484 port->id = plat->npe; 1485 1486 /* Get the port resource and remap */ 1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1488 if (!res) 1489 return -ENODEV; 1490 port->regs = devm_ioremap_resource(dev, res); 1491 if (IS_ERR(port->regs)) 1492 return PTR_ERR(port->regs); 1493 1494 /* Register the MDIO bus if we have it */ 1495 if (plat->has_mdio) { 1496 err = ixp4xx_mdio_register(port->regs); 1497 if (err) { 1498 dev_err(dev, "failed to register MDIO bus\n"); 1499 return err; 1500 } 1501 } 1502 /* If the instance with the MDIO bus has not yet appeared, 1503 * defer probing until it gets probed. 1504 */ 1505 if (!mdio_bus) 1506 return -EPROBE_DEFER; 1507 1508 ndev->netdev_ops = &ixp4xx_netdev_ops; 1509 ndev->ethtool_ops = &ixp4xx_ethtool_ops; 1510 ndev->tx_queue_len = 100; 1511 /* Inherit the DMA masks from the platform device */ 1512 ndev->dev.dma_mask = dev->dma_mask; 1513 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask; 1514 1515 netif_napi_add(ndev, &port->napi, eth_poll, NAPI_WEIGHT); 1516 1517 if (!(port->npe = npe_request(NPE_ID(port->id)))) 1518 return -EIO; 1519 1520 port->plat = plat; 1521 npe_port_tab[NPE_ID(port->id)] = port; 1522 memcpy(ndev->dev_addr, plat->hwaddr, ETH_ALEN); 1523 1524 platform_set_drvdata(pdev, ndev); 1525 1526 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1527 &port->regs->core_control); 1528 udelay(50); 1529 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1530 udelay(50); 1531 1532 if (np) { 1533 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); 1534 } else { 1535 phydev = mdiobus_get_phy(mdio_bus, plat->phy); 1536 if (IS_ERR(phydev)) { 1537 err = PTR_ERR(phydev); 1538 dev_err(dev, "could not connect phydev (%d)\n", err); 1539 goto err_free_mem; 1540 } 1541 err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, 1542 PHY_INTERFACE_MODE_MII); 1543 if (err) 1544 goto err_free_mem; 1545 1546 } 1547 if (!phydev) { 1548 err = -ENODEV; 1549 dev_err(dev, "no phydev\n"); 1550 goto err_free_mem; 1551 } 1552 1553 phydev->irq = PHY_POLL; 1554 1555 if ((err = register_netdev(ndev))) 1556 goto err_phy_dis; 1557 1558 netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy, 1559 npe_name(port->npe)); 1560 1561 return 0; 1562 1563 err_phy_dis: 1564 phy_disconnect(phydev); 1565 err_free_mem: 1566 npe_port_tab[NPE_ID(port->id)] = NULL; 1567 npe_release(port->npe); 1568 return err; 1569 } 1570 1571 static int ixp4xx_eth_remove(struct platform_device *pdev) 1572 { 1573 struct net_device *ndev = platform_get_drvdata(pdev); 1574 struct phy_device *phydev = ndev->phydev; 1575 struct port *port = netdev_priv(ndev); 1576 1577 unregister_netdev(ndev); 1578 phy_disconnect(phydev); 1579 ixp4xx_mdio_remove(); 1580 npe_port_tab[NPE_ID(port->id)] = NULL; 1581 npe_release(port->npe); 1582 return 0; 1583 } 1584 1585 static const struct of_device_id ixp4xx_eth_of_match[] = { 1586 { 1587 .compatible = "intel,ixp4xx-ethernet", 1588 }, 1589 { }, 1590 }; 1591 1592 static struct platform_driver ixp4xx_eth_driver = { 1593 .driver = { 1594 .name = DRV_NAME, 1595 .of_match_table = of_match_ptr(ixp4xx_eth_of_match), 1596 }, 1597 .probe = ixp4xx_eth_probe, 1598 .remove = ixp4xx_eth_remove, 1599 }; 1600 module_platform_driver(ixp4xx_eth_driver); 1601 1602 MODULE_AUTHOR("Krzysztof Halasa"); 1603 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1604 MODULE_LICENSE("GPL v2"); 1605 MODULE_ALIAS("platform:ixp4xx_eth"); 1606