1 /* 2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/uaccess.h> 17 #include <linux/init.h> 18 #include <linux/netdevice.h> 19 #include <linux/etherdevice.h> 20 #include <linux/skbuff.h> 21 #include <linux/io.h> 22 #include <linux/slab.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/phy.h> 29 #include <linux/interrupt.h> 30 31 #define DRIVER_NAME "xilinx_emaclite" 32 33 /* Register offsets for the EmacLite Core */ 34 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 35 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 36 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 37 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 38 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 39 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 40 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 41 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 42 43 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 44 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 45 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 46 47 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 48 49 /* MDIO Address Register Bit Masks */ 50 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 51 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 52 #define XEL_MDIOADDR_PHYADR_SHIFT 5 53 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 54 55 /* MDIO Write Data Register Bit Masks */ 56 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 57 58 /* MDIO Read Data Register Bit Masks */ 59 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 60 61 /* MDIO Control Register Bit Masks */ 62 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 63 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 64 65 /* Global Interrupt Enable Register (GIER) Bit Masks */ 66 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 67 68 /* Transmit Status Register (TSR) Bit Masks */ 69 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 70 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 71 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 72 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 73 * only. This is not documented 74 * in the HW spec */ 75 76 /* Define for programming the MAC address into the EmacLite */ 77 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 78 79 /* Receive Status Register (RSR) */ 80 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 81 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 82 83 /* Transmit Packet Length Register (TPLR) */ 84 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 85 86 /* Receive Packet Length Register (RPLR) */ 87 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 88 89 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 90 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 91 92 /* General Ethernet Definitions */ 93 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 94 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 95 96 97 98 #define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */ 99 #define ALIGNMENT 4 100 101 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 102 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT) 103 104 /** 105 * struct net_local - Our private per device data 106 * @ndev: instance of the network device 107 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 108 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 109 * @next_tx_buf_to_use: next Tx buffer to write to 110 * @next_rx_buf_to_use: next Rx buffer to read from 111 * @base_addr: base address of the Emaclite device 112 * @reset_lock: lock used for synchronization 113 * @deferred_skb: holds an skb (for transmission at a later time) when the 114 * Tx buffer is not free 115 * @phy_dev: pointer to the PHY device 116 * @phy_node: pointer to the PHY device node 117 * @mii_bus: pointer to the MII bus 118 * @mdio_irqs: IRQs table for MDIO bus 119 * @last_link: last link status 120 * @has_mdio: indicates whether MDIO is included in the HW 121 */ 122 struct net_local { 123 124 struct net_device *ndev; 125 126 bool tx_ping_pong; 127 bool rx_ping_pong; 128 u32 next_tx_buf_to_use; 129 u32 next_rx_buf_to_use; 130 void __iomem *base_addr; 131 132 spinlock_t reset_lock; 133 struct sk_buff *deferred_skb; 134 135 struct phy_device *phy_dev; 136 struct device_node *phy_node; 137 138 struct mii_bus *mii_bus; 139 int mdio_irqs[PHY_MAX_ADDR]; 140 141 int last_link; 142 bool has_mdio; 143 }; 144 145 146 /*************************/ 147 /* EmacLite driver calls */ 148 /*************************/ 149 150 /** 151 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 152 * @drvdata: Pointer to the Emaclite device private data 153 * 154 * This function enables the Tx and Rx interrupts for the Emaclite device along 155 * with the Global Interrupt Enable. 156 */ 157 static void xemaclite_enable_interrupts(struct net_local *drvdata) 158 { 159 u32 reg_data; 160 161 /* Enable the Tx interrupts for the first Buffer */ 162 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); 163 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 164 drvdata->base_addr + XEL_TSR_OFFSET); 165 166 /* Enable the Rx interrupts for the first buffer */ 167 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 168 169 /* Enable the Global Interrupt Enable */ 170 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 171 } 172 173 /** 174 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 175 * @drvdata: Pointer to the Emaclite device private data 176 * 177 * This function disables the Tx and Rx interrupts for the Emaclite device, 178 * along with the Global Interrupt Enable. 179 */ 180 static void xemaclite_disable_interrupts(struct net_local *drvdata) 181 { 182 u32 reg_data; 183 184 /* Disable the Global Interrupt Enable */ 185 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 186 187 /* Disable the Tx interrupts for the first buffer */ 188 reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET); 189 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 190 drvdata->base_addr + XEL_TSR_OFFSET); 191 192 /* Disable the Rx interrupts for the first buffer */ 193 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); 194 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 195 drvdata->base_addr + XEL_RSR_OFFSET); 196 } 197 198 /** 199 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 200 * @src_ptr: Void pointer to the 16-bit aligned source address 201 * @dest_ptr: Pointer to the 32-bit aligned destination address 202 * @length: Number bytes to write from source to destination 203 * 204 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 205 * address in the EmacLite device. 206 */ 207 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 208 unsigned length) 209 { 210 u32 align_buffer; 211 u32 *to_u32_ptr; 212 u16 *from_u16_ptr, *to_u16_ptr; 213 214 to_u32_ptr = dest_ptr; 215 from_u16_ptr = src_ptr; 216 align_buffer = 0; 217 218 for (; length > 3; length -= 4) { 219 to_u16_ptr = (u16 *)&align_buffer; 220 *to_u16_ptr++ = *from_u16_ptr++; 221 *to_u16_ptr++ = *from_u16_ptr++; 222 223 /* This barrier resolves occasional issues seen around 224 * cases where the data is not properly flushed out 225 * from the processor store buffers to the destination 226 * memory locations. 227 */ 228 wmb(); 229 230 /* Output a word */ 231 *to_u32_ptr++ = align_buffer; 232 } 233 if (length) { 234 u8 *from_u8_ptr, *to_u8_ptr; 235 236 /* Set up to output the remaining data */ 237 align_buffer = 0; 238 to_u8_ptr = (u8 *) &align_buffer; 239 from_u8_ptr = (u8 *) from_u16_ptr; 240 241 /* Output the remaining data */ 242 for (; length > 0; length--) 243 *to_u8_ptr++ = *from_u8_ptr++; 244 245 /* This barrier resolves occasional issues seen around 246 * cases where the data is not properly flushed out 247 * from the processor store buffers to the destination 248 * memory locations. 249 */ 250 wmb(); 251 *to_u32_ptr = align_buffer; 252 } 253 } 254 255 /** 256 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 257 * @src_ptr: Pointer to the 32-bit aligned source address 258 * @dest_ptr: Pointer to the 16-bit aligned destination address 259 * @length: Number bytes to read from source to destination 260 * 261 * This function reads data from a 32-bit aligned address in the EmacLite device 262 * to a 16-bit aligned buffer. 263 */ 264 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 265 unsigned length) 266 { 267 u16 *to_u16_ptr, *from_u16_ptr; 268 u32 *from_u32_ptr; 269 u32 align_buffer; 270 271 from_u32_ptr = src_ptr; 272 to_u16_ptr = (u16 *) dest_ptr; 273 274 for (; length > 3; length -= 4) { 275 /* Copy each word into the temporary buffer */ 276 align_buffer = *from_u32_ptr++; 277 from_u16_ptr = (u16 *)&align_buffer; 278 279 /* Read data from source */ 280 *to_u16_ptr++ = *from_u16_ptr++; 281 *to_u16_ptr++ = *from_u16_ptr++; 282 } 283 284 if (length) { 285 u8 *to_u8_ptr, *from_u8_ptr; 286 287 /* Set up to read the remaining data */ 288 to_u8_ptr = (u8 *) to_u16_ptr; 289 align_buffer = *from_u32_ptr++; 290 from_u8_ptr = (u8 *) &align_buffer; 291 292 /* Read the remaining data */ 293 for (; length > 0; length--) 294 *to_u8_ptr = *from_u8_ptr; 295 } 296 } 297 298 /** 299 * xemaclite_send_data - Send an Ethernet frame 300 * @drvdata: Pointer to the Emaclite device private data 301 * @data: Pointer to the data to be sent 302 * @byte_count: Total frame size, including header 303 * 304 * This function checks if the Tx buffer of the Emaclite device is free to send 305 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 306 * returns an error. 307 * 308 * Return: 0 upon success or -1 if the buffer(s) are full. 309 * 310 * Note: The maximum Tx packet size can not be more than Ethernet header 311 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 312 */ 313 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 314 unsigned int byte_count) 315 { 316 u32 reg_data; 317 void __iomem *addr; 318 319 /* Determine the expected Tx buffer address */ 320 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 321 322 /* If the length is too large, truncate it */ 323 if (byte_count > ETH_FRAME_LEN) 324 byte_count = ETH_FRAME_LEN; 325 326 /* Check if the expected buffer is available */ 327 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); 328 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 329 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 330 331 /* Switch to next buffer if configured */ 332 if (drvdata->tx_ping_pong != 0) 333 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 334 } else if (drvdata->tx_ping_pong != 0) { 335 /* If the expected buffer is full, try the other buffer, 336 * if it is configured in HW */ 337 338 addr = (void __iomem __force *)((u32 __force)addr ^ 339 XEL_BUFFER_OFFSET); 340 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); 341 342 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 343 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 344 return -1; /* Buffers were full, return failure */ 345 } else 346 return -1; /* Buffer was full, return failure */ 347 348 /* Write the frame to the buffer */ 349 xemaclite_aligned_write(data, (u32 __force *) addr, byte_count); 350 351 __raw_writel((byte_count & XEL_TPLR_LENGTH_MASK), 352 addr + XEL_TPLR_OFFSET); 353 354 /* Update the Tx Status Register to indicate that there is a 355 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 356 * is used by the interrupt handler to check whether a frame 357 * has been transmitted */ 358 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); 359 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 360 __raw_writel(reg_data, addr + XEL_TSR_OFFSET); 361 362 return 0; 363 } 364 365 /** 366 * xemaclite_recv_data - Receive a frame 367 * @drvdata: Pointer to the Emaclite device private data 368 * @data: Address where the data is to be received 369 * 370 * This function is intended to be called from the interrupt context or 371 * with a wrapper which waits for the receive frame to be available. 372 * 373 * Return: Total number of bytes received 374 */ 375 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data) 376 { 377 void __iomem *addr; 378 u16 length, proto_type; 379 u32 reg_data; 380 381 /* Determine the expected buffer address */ 382 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 383 384 /* Verify which buffer has valid data */ 385 reg_data = __raw_readl(addr + XEL_RSR_OFFSET); 386 387 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 388 if (drvdata->rx_ping_pong != 0) 389 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 390 } else { 391 /* The instance is out of sync, try other buffer if other 392 * buffer is configured, return 0 otherwise. If the instance is 393 * out of sync, do not update the 'next_rx_buf_to_use' since it 394 * will correct on subsequent calls */ 395 if (drvdata->rx_ping_pong != 0) 396 addr = (void __iomem __force *)((u32 __force)addr ^ 397 XEL_BUFFER_OFFSET); 398 else 399 return 0; /* No data was available */ 400 401 /* Verify that buffer has valid data */ 402 reg_data = __raw_readl(addr + XEL_RSR_OFFSET); 403 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 404 XEL_RSR_RECV_DONE_MASK) 405 return 0; /* No data was available */ 406 } 407 408 /* Get the protocol type of the ethernet frame that arrived */ 409 proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET + 410 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 411 XEL_RPLR_LENGTH_MASK); 412 413 /* Check if received ethernet frame is a raw ethernet frame 414 * or an IP packet or an ARP packet */ 415 if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) { 416 417 if (proto_type == ETH_P_IP) { 418 length = ((ntohl(__raw_readl(addr + 419 XEL_HEADER_IP_LENGTH_OFFSET + 420 XEL_RXBUFF_OFFSET)) >> 421 XEL_HEADER_SHIFT) & 422 XEL_RPLR_LENGTH_MASK); 423 length += ETH_HLEN + ETH_FCS_LEN; 424 425 } else if (proto_type == ETH_P_ARP) 426 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 427 else 428 /* Field contains type other than IP or ARP, use max 429 * frame size and let user parse it */ 430 length = ETH_FRAME_LEN + ETH_FCS_LEN; 431 } else 432 /* Use the length in the frame, plus the header and trailer */ 433 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 434 435 /* Read from the EmacLite device */ 436 xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET), 437 data, length); 438 439 /* Acknowledge the frame */ 440 reg_data = __raw_readl(addr + XEL_RSR_OFFSET); 441 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 442 __raw_writel(reg_data, addr + XEL_RSR_OFFSET); 443 444 return length; 445 } 446 447 /** 448 * xemaclite_update_address - Update the MAC address in the device 449 * @drvdata: Pointer to the Emaclite device private data 450 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 451 * 452 * Tx must be idle and Rx should be idle for deterministic results. 453 * It is recommended that this function should be called after the 454 * initialization and before transmission of any packets from the device. 455 * The MAC address can be programmed using any of the two transmit 456 * buffers (if configured). 457 */ 458 static void xemaclite_update_address(struct net_local *drvdata, 459 u8 *address_ptr) 460 { 461 void __iomem *addr; 462 u32 reg_data; 463 464 /* Determine the expected Tx buffer address */ 465 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 466 467 xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN); 468 469 __raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 470 471 /* Update the MAC address in the EmacLite */ 472 reg_data = __raw_readl(addr + XEL_TSR_OFFSET); 473 __raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 474 475 /* Wait for EmacLite to finish with the MAC address update */ 476 while ((__raw_readl(addr + XEL_TSR_OFFSET) & 477 XEL_TSR_PROG_MAC_ADDR) != 0) 478 ; 479 } 480 481 /** 482 * xemaclite_set_mac_address - Set the MAC address for this device 483 * @dev: Pointer to the network device instance 484 * @addr: Void pointer to the sockaddr structure 485 * 486 * This function copies the HW address from the sockaddr strucutre to the 487 * net_device structure and updates the address in HW. 488 * 489 * Return: Error if the net device is busy or 0 if the addr is set 490 * successfully 491 */ 492 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 493 { 494 struct net_local *lp = netdev_priv(dev); 495 struct sockaddr *addr = address; 496 497 if (netif_running(dev)) 498 return -EBUSY; 499 500 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 501 xemaclite_update_address(lp, dev->dev_addr); 502 return 0; 503 } 504 505 /** 506 * xemaclite_tx_timeout - Callback for Tx Timeout 507 * @dev: Pointer to the network device 508 * 509 * This function is called when Tx time out occurs for Emaclite device. 510 */ 511 static void xemaclite_tx_timeout(struct net_device *dev) 512 { 513 struct net_local *lp = netdev_priv(dev); 514 unsigned long flags; 515 516 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 517 TX_TIMEOUT * 1000UL / HZ); 518 519 dev->stats.tx_errors++; 520 521 /* Reset the device */ 522 spin_lock_irqsave(&lp->reset_lock, flags); 523 524 /* Shouldn't really be necessary, but shouldn't hurt */ 525 netif_stop_queue(dev); 526 527 xemaclite_disable_interrupts(lp); 528 xemaclite_enable_interrupts(lp); 529 530 if (lp->deferred_skb) { 531 dev_kfree_skb(lp->deferred_skb); 532 lp->deferred_skb = NULL; 533 dev->stats.tx_errors++; 534 } 535 536 /* To exclude tx timeout */ 537 dev->trans_start = jiffies; /* prevent tx timeout */ 538 539 /* We're all ready to go. Start the queue */ 540 netif_wake_queue(dev); 541 spin_unlock_irqrestore(&lp->reset_lock, flags); 542 } 543 544 /**********************/ 545 /* Interrupt Handlers */ 546 /**********************/ 547 548 /** 549 * xemaclite_tx_handler - Interrupt handler for frames sent 550 * @dev: Pointer to the network device 551 * 552 * This function updates the number of packets transmitted and handles the 553 * deferred skb, if there is one. 554 */ 555 static void xemaclite_tx_handler(struct net_device *dev) 556 { 557 struct net_local *lp = netdev_priv(dev); 558 559 dev->stats.tx_packets++; 560 if (lp->deferred_skb) { 561 if (xemaclite_send_data(lp, 562 (u8 *) lp->deferred_skb->data, 563 lp->deferred_skb->len) != 0) 564 return; 565 else { 566 dev->stats.tx_bytes += lp->deferred_skb->len; 567 dev_kfree_skb_irq(lp->deferred_skb); 568 lp->deferred_skb = NULL; 569 dev->trans_start = jiffies; /* prevent tx timeout */ 570 netif_wake_queue(dev); 571 } 572 } 573 } 574 575 /** 576 * xemaclite_rx_handler- Interrupt handler for frames received 577 * @dev: Pointer to the network device 578 * 579 * This function allocates memory for a socket buffer, fills it with data 580 * received and hands it over to the TCP/IP stack. 581 */ 582 static void xemaclite_rx_handler(struct net_device *dev) 583 { 584 struct net_local *lp = netdev_priv(dev); 585 struct sk_buff *skb; 586 unsigned int align; 587 u32 len; 588 589 len = ETH_FRAME_LEN + ETH_FCS_LEN; 590 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 591 if (!skb) { 592 /* Couldn't get memory. */ 593 dev->stats.rx_dropped++; 594 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 595 return; 596 } 597 598 /* 599 * A new skb should have the data halfword aligned, but this code is 600 * here just in case that isn't true. Calculate how many 601 * bytes we should reserve to get the data to start on a word 602 * boundary */ 603 align = BUFFER_ALIGN(skb->data); 604 if (align) 605 skb_reserve(skb, align); 606 607 skb_reserve(skb, 2); 608 609 len = xemaclite_recv_data(lp, (u8 *) skb->data); 610 611 if (!len) { 612 dev->stats.rx_errors++; 613 dev_kfree_skb_irq(skb); 614 return; 615 } 616 617 skb_put(skb, len); /* Tell the skb how much data we got */ 618 619 skb->protocol = eth_type_trans(skb, dev); 620 skb_checksum_none_assert(skb); 621 622 dev->stats.rx_packets++; 623 dev->stats.rx_bytes += len; 624 625 if (!skb_defer_rx_timestamp(skb)) 626 netif_rx(skb); /* Send the packet upstream */ 627 } 628 629 /** 630 * xemaclite_interrupt - Interrupt handler for this driver 631 * @irq: Irq of the Emaclite device 632 * @dev_id: Void pointer to the network device instance used as callback 633 * reference 634 * 635 * This function handles the Tx and Rx interrupts of the EmacLite device. 636 */ 637 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 638 { 639 bool tx_complete = false; 640 struct net_device *dev = dev_id; 641 struct net_local *lp = netdev_priv(dev); 642 void __iomem *base_addr = lp->base_addr; 643 u32 tx_status; 644 645 /* Check if there is Rx Data available */ 646 if ((__raw_readl(base_addr + XEL_RSR_OFFSET) & 647 XEL_RSR_RECV_DONE_MASK) || 648 (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 649 & XEL_RSR_RECV_DONE_MASK)) 650 651 xemaclite_rx_handler(dev); 652 653 /* Check if the Transmission for the first buffer is completed */ 654 tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET); 655 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 656 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 657 658 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 659 __raw_writel(tx_status, base_addr + XEL_TSR_OFFSET); 660 661 tx_complete = true; 662 } 663 664 /* Check if the Transmission for the second buffer is completed */ 665 tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 666 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 667 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 668 669 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 670 __raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 671 XEL_TSR_OFFSET); 672 673 tx_complete = true; 674 } 675 676 /* If there was a Tx interrupt, call the Tx Handler */ 677 if (tx_complete != 0) 678 xemaclite_tx_handler(dev); 679 680 return IRQ_HANDLED; 681 } 682 683 /**********************/ 684 /* MDIO Bus functions */ 685 /**********************/ 686 687 /** 688 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 689 * @lp: Pointer to the Emaclite device private data 690 * 691 * This function waits till the device is ready to accept a new MDIO 692 * request. 693 * 694 * Return: 0 for success or ETIMEDOUT for a timeout 695 */ 696 697 static int xemaclite_mdio_wait(struct net_local *lp) 698 { 699 long end = jiffies + 2; 700 701 /* wait for the MDIO interface to not be busy or timeout 702 after some time. 703 */ 704 while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) & 705 XEL_MDIOCTRL_MDIOSTS_MASK) { 706 if (end - jiffies <= 0) { 707 WARN_ON(1); 708 return -ETIMEDOUT; 709 } 710 msleep(1); 711 } 712 return 0; 713 } 714 715 /** 716 * xemaclite_mdio_read - Read from a given MII management register 717 * @bus: the mii_bus struct 718 * @phy_id: the phy address 719 * @reg: register number to read from 720 * 721 * This function waits till the device is ready to accept a new MDIO 722 * request and then writes the phy address to the MDIO Address register 723 * and reads data from MDIO Read Data register, when its available. 724 * 725 * Return: Value read from the MII management register 726 */ 727 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 728 { 729 struct net_local *lp = bus->priv; 730 u32 ctrl_reg; 731 u32 rc; 732 733 if (xemaclite_mdio_wait(lp)) 734 return -ETIMEDOUT; 735 736 /* Write the PHY address, register number and set the OP bit in the 737 * MDIO Address register. Set the Status bit in the MDIO Control 738 * register to start a MDIO read transaction. 739 */ 740 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 741 __raw_writel(XEL_MDIOADDR_OP_MASK | 742 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 743 lp->base_addr + XEL_MDIOADDR_OFFSET); 744 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 745 lp->base_addr + XEL_MDIOCTRL_OFFSET); 746 747 if (xemaclite_mdio_wait(lp)) 748 return -ETIMEDOUT; 749 750 rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET); 751 752 dev_dbg(&lp->ndev->dev, 753 "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n", 754 phy_id, reg, rc); 755 756 return rc; 757 } 758 759 /** 760 * xemaclite_mdio_write - Write to a given MII management register 761 * @bus: the mii_bus struct 762 * @phy_id: the phy address 763 * @reg: register number to write to 764 * @val: value to write to the register number specified by reg 765 * 766 * This function waits till the device is ready to accept a new MDIO 767 * request and then writes the val to the MDIO Write Data register. 768 */ 769 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 770 u16 val) 771 { 772 struct net_local *lp = bus->priv; 773 u32 ctrl_reg; 774 775 dev_dbg(&lp->ndev->dev, 776 "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n", 777 phy_id, reg, val); 778 779 if (xemaclite_mdio_wait(lp)) 780 return -ETIMEDOUT; 781 782 /* Write the PHY address, register number and clear the OP bit in the 783 * MDIO Address register and then write the value into the MDIO Write 784 * Data register. Finally, set the Status bit in the MDIO Control 785 * register to start a MDIO write transaction. 786 */ 787 ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 788 __raw_writel(~XEL_MDIOADDR_OP_MASK & 789 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 790 lp->base_addr + XEL_MDIOADDR_OFFSET); 791 __raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 792 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 793 lp->base_addr + XEL_MDIOCTRL_OFFSET); 794 795 return 0; 796 } 797 798 /** 799 * xemaclite_mdio_reset - Reset the mdio bus. 800 * @bus: Pointer to the MII bus 801 * 802 * This function is required(?) as per Documentation/networking/phy.txt. 803 * There is no reset in this device; this function always returns 0. 804 */ 805 static int xemaclite_mdio_reset(struct mii_bus *bus) 806 { 807 return 0; 808 } 809 810 /** 811 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 812 * @lp: Pointer to the Emaclite device private data 813 * @ofdev: Pointer to OF device structure 814 * 815 * This function enables MDIO bus in the Emaclite device and registers a 816 * mii_bus. 817 * 818 * Return: 0 upon success or a negative error upon failure 819 */ 820 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 821 { 822 struct mii_bus *bus; 823 int rc; 824 struct resource res; 825 struct device_node *np = of_get_parent(lp->phy_node); 826 struct device_node *npp; 827 828 /* Don't register the MDIO bus if the phy_node or its parent node 829 * can't be found. 830 */ 831 if (!np) { 832 dev_err(dev, "Failed to register mdio bus.\n"); 833 return -ENODEV; 834 } 835 npp = of_get_parent(np); 836 837 of_address_to_resource(npp, 0, &res); 838 if (lp->ndev->mem_start != res.start) { 839 struct phy_device *phydev; 840 phydev = of_phy_find_device(lp->phy_node); 841 if (!phydev) 842 dev_info(dev, 843 "MDIO of the phy is not registered yet\n"); 844 return 0; 845 } 846 847 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 848 * register. 849 */ 850 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, 851 lp->base_addr + XEL_MDIOCTRL_OFFSET); 852 853 bus = mdiobus_alloc(); 854 if (!bus) { 855 dev_err(dev, "Failed to allocate mdiobus\n"); 856 return -ENOMEM; 857 } 858 859 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 860 (unsigned long long)res.start); 861 bus->priv = lp; 862 bus->name = "Xilinx Emaclite MDIO"; 863 bus->read = xemaclite_mdio_read; 864 bus->write = xemaclite_mdio_write; 865 bus->reset = xemaclite_mdio_reset; 866 bus->parent = dev; 867 bus->irq = lp->mdio_irqs; /* preallocated IRQ table */ 868 869 lp->mii_bus = bus; 870 871 rc = of_mdiobus_register(bus, np); 872 if (rc) { 873 dev_err(dev, "Failed to register mdio bus.\n"); 874 goto err_register; 875 } 876 877 return 0; 878 879 err_register: 880 mdiobus_free(bus); 881 return rc; 882 } 883 884 /** 885 * xemaclite_adjust_link - Link state callback for the Emaclite device 886 * @ndev: pointer to net_device struct 887 * 888 * There's nothing in the Emaclite device to be configured when the link 889 * state changes. We just print the status. 890 */ 891 static void xemaclite_adjust_link(struct net_device *ndev) 892 { 893 struct net_local *lp = netdev_priv(ndev); 894 struct phy_device *phy = lp->phy_dev; 895 int link_state; 896 897 /* hash together the state values to decide if something has changed */ 898 link_state = phy->speed | (phy->duplex << 1) | phy->link; 899 900 if (lp->last_link != link_state) { 901 lp->last_link = link_state; 902 phy_print_status(phy); 903 } 904 } 905 906 /** 907 * xemaclite_open - Open the network device 908 * @dev: Pointer to the network device 909 * 910 * This function sets the MAC address, requests an IRQ and enables interrupts 911 * for the Emaclite device and starts the Tx queue. 912 * It also connects to the phy device, if MDIO is included in Emaclite device. 913 */ 914 static int xemaclite_open(struct net_device *dev) 915 { 916 struct net_local *lp = netdev_priv(dev); 917 int retval; 918 919 /* Just to be safe, stop the device first */ 920 xemaclite_disable_interrupts(lp); 921 922 if (lp->phy_node) { 923 u32 bmcr; 924 925 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 926 xemaclite_adjust_link, 0, 927 PHY_INTERFACE_MODE_MII); 928 if (!lp->phy_dev) { 929 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 930 return -ENODEV; 931 } 932 933 /* EmacLite doesn't support giga-bit speeds */ 934 lp->phy_dev->supported &= (PHY_BASIC_FEATURES); 935 lp->phy_dev->advertising = lp->phy_dev->supported; 936 937 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 938 phy_write(lp->phy_dev, MII_CTRL1000, 0); 939 940 /* Advertise only 10 and 100mbps full/half duplex speeds */ 941 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 942 ADVERTISE_CSMA); 943 944 /* Restart auto negotiation */ 945 bmcr = phy_read(lp->phy_dev, MII_BMCR); 946 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 947 phy_write(lp->phy_dev, MII_BMCR, bmcr); 948 949 phy_start(lp->phy_dev); 950 } 951 952 /* Set the MAC address each time opened */ 953 xemaclite_update_address(lp, dev->dev_addr); 954 955 /* Grab the IRQ */ 956 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 957 if (retval) { 958 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 959 dev->irq); 960 if (lp->phy_dev) 961 phy_disconnect(lp->phy_dev); 962 lp->phy_dev = NULL; 963 964 return retval; 965 } 966 967 /* Enable Interrupts */ 968 xemaclite_enable_interrupts(lp); 969 970 /* We're ready to go */ 971 netif_start_queue(dev); 972 973 return 0; 974 } 975 976 /** 977 * xemaclite_close - Close the network device 978 * @dev: Pointer to the network device 979 * 980 * This function stops the Tx queue, disables interrupts and frees the IRQ for 981 * the Emaclite device. 982 * It also disconnects the phy device associated with the Emaclite device. 983 */ 984 static int xemaclite_close(struct net_device *dev) 985 { 986 struct net_local *lp = netdev_priv(dev); 987 988 netif_stop_queue(dev); 989 xemaclite_disable_interrupts(lp); 990 free_irq(dev->irq, dev); 991 992 if (lp->phy_dev) 993 phy_disconnect(lp->phy_dev); 994 lp->phy_dev = NULL; 995 996 return 0; 997 } 998 999 /** 1000 * xemaclite_send - Transmit a frame 1001 * @orig_skb: Pointer to the socket buffer to be transmitted 1002 * @dev: Pointer to the network device 1003 * 1004 * This function checks if the Tx buffer of the Emaclite device is free to send 1005 * data. If so, it fills the Tx buffer with data from socket buffer data, 1006 * updates the stats and frees the socket buffer. The Tx completion is signaled 1007 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1008 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1009 * be transmitted when the Emaclite device is free to transmit data. 1010 * 1011 * Return: 0, always. 1012 */ 1013 static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1014 { 1015 struct net_local *lp = netdev_priv(dev); 1016 struct sk_buff *new_skb; 1017 unsigned int len; 1018 unsigned long flags; 1019 1020 len = orig_skb->len; 1021 1022 new_skb = orig_skb; 1023 1024 spin_lock_irqsave(&lp->reset_lock, flags); 1025 if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) { 1026 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1027 * defer the skb for transmission during the ISR, after the 1028 * current transmission is complete */ 1029 netif_stop_queue(dev); 1030 lp->deferred_skb = new_skb; 1031 /* Take the time stamp now, since we can't do this in an ISR. */ 1032 skb_tx_timestamp(new_skb); 1033 spin_unlock_irqrestore(&lp->reset_lock, flags); 1034 return 0; 1035 } 1036 spin_unlock_irqrestore(&lp->reset_lock, flags); 1037 1038 skb_tx_timestamp(new_skb); 1039 1040 dev->stats.tx_bytes += len; 1041 dev_kfree_skb(new_skb); 1042 1043 return 0; 1044 } 1045 1046 /** 1047 * xemaclite_remove_ndev - Free the network device 1048 * @ndev: Pointer to the network device to be freed 1049 * 1050 * This function un maps the IO region of the Emaclite device and frees the net 1051 * device. 1052 */ 1053 static void xemaclite_remove_ndev(struct net_device *ndev) 1054 { 1055 if (ndev) { 1056 free_netdev(ndev); 1057 } 1058 } 1059 1060 /** 1061 * get_bool - Get a parameter from the OF device 1062 * @ofdev: Pointer to OF device structure 1063 * @s: Property to be retrieved 1064 * 1065 * This function looks for a property in the device node and returns the value 1066 * of the property if its found or 0 if the property is not found. 1067 * 1068 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1069 */ 1070 static bool get_bool(struct platform_device *ofdev, const char *s) 1071 { 1072 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1073 1074 if (p) { 1075 return (bool)*p; 1076 } else { 1077 dev_warn(&ofdev->dev, "Parameter %s not found," 1078 "defaulting to false\n", s); 1079 return 0; 1080 } 1081 } 1082 1083 static struct net_device_ops xemaclite_netdev_ops; 1084 1085 /** 1086 * xemaclite_of_probe - Probe method for the Emaclite device. 1087 * @ofdev: Pointer to OF device structure 1088 * @match: Pointer to the structure used for matching a device 1089 * 1090 * This function probes for the Emaclite device in the device tree. 1091 * It initializes the driver data structure and the hardware, sets the MAC 1092 * address and registers the network device. 1093 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1094 * in the device. 1095 * 1096 * Return: 0, if the driver is bound to the Emaclite device, or 1097 * a negative error if there is failure. 1098 */ 1099 static int xemaclite_of_probe(struct platform_device *ofdev) 1100 { 1101 struct resource *res; 1102 struct net_device *ndev = NULL; 1103 struct net_local *lp = NULL; 1104 struct device *dev = &ofdev->dev; 1105 const void *mac_address; 1106 1107 int rc = 0; 1108 1109 dev_info(dev, "Device Tree Probing\n"); 1110 1111 /* Create an ethernet device instance */ 1112 ndev = alloc_etherdev(sizeof(struct net_local)); 1113 if (!ndev) 1114 return -ENOMEM; 1115 1116 dev_set_drvdata(dev, ndev); 1117 SET_NETDEV_DEV(ndev, &ofdev->dev); 1118 1119 lp = netdev_priv(ndev); 1120 lp->ndev = ndev; 1121 1122 /* Get IRQ for the device */ 1123 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1124 if (!res) { 1125 dev_err(dev, "no IRQ found\n"); 1126 goto error; 1127 } 1128 1129 ndev->irq = res->start; 1130 1131 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1132 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1133 if (IS_ERR(lp->base_addr)) { 1134 rc = PTR_ERR(lp->base_addr); 1135 goto error; 1136 } 1137 1138 ndev->mem_start = res->start; 1139 ndev->mem_end = res->end; 1140 1141 spin_lock_init(&lp->reset_lock); 1142 lp->next_tx_buf_to_use = 0x0; 1143 lp->next_rx_buf_to_use = 0x0; 1144 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1145 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1146 mac_address = of_get_mac_address(ofdev->dev.of_node); 1147 1148 if (mac_address) 1149 /* Set the MAC address. */ 1150 memcpy(ndev->dev_addr, mac_address, ETH_ALEN); 1151 else 1152 dev_warn(dev, "No MAC address found\n"); 1153 1154 /* Clear the Tx CSR's in case this is a restart */ 1155 __raw_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1156 __raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1157 1158 /* Set the MAC address in the EmacLite device */ 1159 xemaclite_update_address(lp, ndev->dev_addr); 1160 1161 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1162 rc = xemaclite_mdio_setup(lp, &ofdev->dev); 1163 if (rc) 1164 dev_warn(&ofdev->dev, "error registering MDIO bus\n"); 1165 1166 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1167 1168 ndev->netdev_ops = &xemaclite_netdev_ops; 1169 ndev->flags &= ~IFF_MULTICAST; 1170 ndev->watchdog_timeo = TX_TIMEOUT; 1171 1172 /* Finally, register the device */ 1173 rc = register_netdev(ndev); 1174 if (rc) { 1175 dev_err(dev, 1176 "Cannot register network device, aborting\n"); 1177 goto error; 1178 } 1179 1180 dev_info(dev, 1181 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1182 (unsigned int __force)ndev->mem_start, 1183 (unsigned int __force)lp->base_addr, ndev->irq); 1184 return 0; 1185 1186 error: 1187 xemaclite_remove_ndev(ndev); 1188 return rc; 1189 } 1190 1191 /** 1192 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1193 * @of_dev: Pointer to OF device structure 1194 * 1195 * This function is called if a device is physically removed from the system or 1196 * if the driver module is being unloaded. It frees any resources allocated to 1197 * the device. 1198 * 1199 * Return: 0, always. 1200 */ 1201 static int xemaclite_of_remove(struct platform_device *of_dev) 1202 { 1203 struct net_device *ndev = platform_get_drvdata(of_dev); 1204 1205 struct net_local *lp = netdev_priv(ndev); 1206 1207 /* Un-register the mii_bus, if configured */ 1208 if (lp->has_mdio) { 1209 mdiobus_unregister(lp->mii_bus); 1210 kfree(lp->mii_bus->irq); 1211 mdiobus_free(lp->mii_bus); 1212 lp->mii_bus = NULL; 1213 } 1214 1215 unregister_netdev(ndev); 1216 1217 if (lp->phy_node) 1218 of_node_put(lp->phy_node); 1219 lp->phy_node = NULL; 1220 1221 xemaclite_remove_ndev(ndev); 1222 1223 return 0; 1224 } 1225 1226 #ifdef CONFIG_NET_POLL_CONTROLLER 1227 static void 1228 xemaclite_poll_controller(struct net_device *ndev) 1229 { 1230 disable_irq(ndev->irq); 1231 xemaclite_interrupt(ndev->irq, ndev); 1232 enable_irq(ndev->irq); 1233 } 1234 #endif 1235 1236 static struct net_device_ops xemaclite_netdev_ops = { 1237 .ndo_open = xemaclite_open, 1238 .ndo_stop = xemaclite_close, 1239 .ndo_start_xmit = xemaclite_send, 1240 .ndo_set_mac_address = xemaclite_set_mac_address, 1241 .ndo_tx_timeout = xemaclite_tx_timeout, 1242 #ifdef CONFIG_NET_POLL_CONTROLLER 1243 .ndo_poll_controller = xemaclite_poll_controller, 1244 #endif 1245 }; 1246 1247 /* Match table for OF platform binding */ 1248 static struct of_device_id xemaclite_of_match[] = { 1249 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1250 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1251 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1252 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1253 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1254 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1255 { /* end of list */ }, 1256 }; 1257 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1258 1259 static struct platform_driver xemaclite_of_driver = { 1260 .driver = { 1261 .name = DRIVER_NAME, 1262 .owner = THIS_MODULE, 1263 .of_match_table = xemaclite_of_match, 1264 }, 1265 .probe = xemaclite_of_probe, 1266 .remove = xemaclite_of_remove, 1267 }; 1268 1269 module_platform_driver(xemaclite_of_driver); 1270 1271 MODULE_AUTHOR("Xilinx, Inc."); 1272 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1273 MODULE_LICENSE("GPL"); 1274