1 /* 2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/uaccess.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/skbuff.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_mdio.h> 26 #include <linux/of_net.h> 27 #include <linux/phy.h> 28 #include <linux/interrupt.h> 29 30 #define DRIVER_NAME "xilinx_emaclite" 31 32 /* Register offsets for the EmacLite Core */ 33 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 34 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 35 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 36 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 37 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 38 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 39 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 40 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 41 42 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 43 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 44 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 45 46 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 47 48 /* MDIO Address Register Bit Masks */ 49 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 50 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 51 #define XEL_MDIOADDR_PHYADR_SHIFT 5 52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 53 54 /* MDIO Write Data Register Bit Masks */ 55 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 56 57 /* MDIO Read Data Register Bit Masks */ 58 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 59 60 /* MDIO Control Register Bit Masks */ 61 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 62 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 63 64 /* Global Interrupt Enable Register (GIER) Bit Masks */ 65 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 66 67 /* Transmit Status Register (TSR) Bit Masks */ 68 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 69 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 70 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 71 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 72 * only. This is not documented 73 * in the HW spec */ 74 75 /* Define for programming the MAC address into the EmacLite */ 76 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 77 78 /* Receive Status Register (RSR) */ 79 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 80 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 81 82 /* Transmit Packet Length Register (TPLR) */ 83 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 84 85 /* Receive Packet Length Register (RPLR) */ 86 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 87 88 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 89 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 90 91 /* General Ethernet Definitions */ 92 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 93 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 94 95 96 97 #define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */ 98 #define ALIGNMENT 4 99 100 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 101 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT) 102 103 #ifdef __BIG_ENDIAN 104 #define xemaclite_readl ioread32be 105 #define xemaclite_writel iowrite32be 106 #else 107 #define xemaclite_readl ioread32 108 #define xemaclite_writel iowrite32 109 #endif 110 111 /** 112 * struct net_local - Our private per device data 113 * @ndev: instance of the network device 114 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 115 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 116 * @next_tx_buf_to_use: next Tx buffer to write to 117 * @next_rx_buf_to_use: next Rx buffer to read from 118 * @base_addr: base address of the Emaclite device 119 * @reset_lock: lock used for synchronization 120 * @deferred_skb: holds an skb (for transmission at a later time) when the 121 * Tx buffer is not free 122 * @phy_dev: pointer to the PHY device 123 * @phy_node: pointer to the PHY device node 124 * @mii_bus: pointer to the MII bus 125 * @last_link: last link status 126 */ 127 struct net_local { 128 129 struct net_device *ndev; 130 131 bool tx_ping_pong; 132 bool rx_ping_pong; 133 u32 next_tx_buf_to_use; 134 u32 next_rx_buf_to_use; 135 void __iomem *base_addr; 136 137 spinlock_t reset_lock; 138 struct sk_buff *deferred_skb; 139 140 struct phy_device *phy_dev; 141 struct device_node *phy_node; 142 143 struct mii_bus *mii_bus; 144 145 int last_link; 146 }; 147 148 149 /*************************/ 150 /* EmacLite driver calls */ 151 /*************************/ 152 153 /** 154 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 155 * @drvdata: Pointer to the Emaclite device private data 156 * 157 * This function enables the Tx and Rx interrupts for the Emaclite device along 158 * with the Global Interrupt Enable. 159 */ 160 static void xemaclite_enable_interrupts(struct net_local *drvdata) 161 { 162 u32 reg_data; 163 164 /* Enable the Tx interrupts for the first Buffer */ 165 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 166 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 167 drvdata->base_addr + XEL_TSR_OFFSET); 168 169 /* Enable the Rx interrupts for the first buffer */ 170 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 171 172 /* Enable the Global Interrupt Enable */ 173 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 174 } 175 176 /** 177 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 178 * @drvdata: Pointer to the Emaclite device private data 179 * 180 * This function disables the Tx and Rx interrupts for the Emaclite device, 181 * along with the Global Interrupt Enable. 182 */ 183 static void xemaclite_disable_interrupts(struct net_local *drvdata) 184 { 185 u32 reg_data; 186 187 /* Disable the Global Interrupt Enable */ 188 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 189 190 /* Disable the Tx interrupts for the first buffer */ 191 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 192 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 193 drvdata->base_addr + XEL_TSR_OFFSET); 194 195 /* Disable the Rx interrupts for the first buffer */ 196 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 197 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 198 drvdata->base_addr + XEL_RSR_OFFSET); 199 } 200 201 /** 202 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 203 * @src_ptr: Void pointer to the 16-bit aligned source address 204 * @dest_ptr: Pointer to the 32-bit aligned destination address 205 * @length: Number bytes to write from source to destination 206 * 207 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 208 * address in the EmacLite device. 209 */ 210 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 211 unsigned length) 212 { 213 u32 align_buffer; 214 u32 *to_u32_ptr; 215 u16 *from_u16_ptr, *to_u16_ptr; 216 217 to_u32_ptr = dest_ptr; 218 from_u16_ptr = src_ptr; 219 align_buffer = 0; 220 221 for (; length > 3; length -= 4) { 222 to_u16_ptr = (u16 *)&align_buffer; 223 *to_u16_ptr++ = *from_u16_ptr++; 224 *to_u16_ptr++ = *from_u16_ptr++; 225 226 /* This barrier resolves occasional issues seen around 227 * cases where the data is not properly flushed out 228 * from the processor store buffers to the destination 229 * memory locations. 230 */ 231 wmb(); 232 233 /* Output a word */ 234 *to_u32_ptr++ = align_buffer; 235 } 236 if (length) { 237 u8 *from_u8_ptr, *to_u8_ptr; 238 239 /* Set up to output the remaining data */ 240 align_buffer = 0; 241 to_u8_ptr = (u8 *) &align_buffer; 242 from_u8_ptr = (u8 *) from_u16_ptr; 243 244 /* Output the remaining data */ 245 for (; length > 0; length--) 246 *to_u8_ptr++ = *from_u8_ptr++; 247 248 /* This barrier resolves occasional issues seen around 249 * cases where the data is not properly flushed out 250 * from the processor store buffers to the destination 251 * memory locations. 252 */ 253 wmb(); 254 *to_u32_ptr = align_buffer; 255 } 256 } 257 258 /** 259 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 260 * @src_ptr: Pointer to the 32-bit aligned source address 261 * @dest_ptr: Pointer to the 16-bit aligned destination address 262 * @length: Number bytes to read from source to destination 263 * 264 * This function reads data from a 32-bit aligned address in the EmacLite device 265 * to a 16-bit aligned buffer. 266 */ 267 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 268 unsigned length) 269 { 270 u16 *to_u16_ptr, *from_u16_ptr; 271 u32 *from_u32_ptr; 272 u32 align_buffer; 273 274 from_u32_ptr = src_ptr; 275 to_u16_ptr = (u16 *) dest_ptr; 276 277 for (; length > 3; length -= 4) { 278 /* Copy each word into the temporary buffer */ 279 align_buffer = *from_u32_ptr++; 280 from_u16_ptr = (u16 *)&align_buffer; 281 282 /* Read data from source */ 283 *to_u16_ptr++ = *from_u16_ptr++; 284 *to_u16_ptr++ = *from_u16_ptr++; 285 } 286 287 if (length) { 288 u8 *to_u8_ptr, *from_u8_ptr; 289 290 /* Set up to read the remaining data */ 291 to_u8_ptr = (u8 *) to_u16_ptr; 292 align_buffer = *from_u32_ptr++; 293 from_u8_ptr = (u8 *) &align_buffer; 294 295 /* Read the remaining data */ 296 for (; length > 0; length--) 297 *to_u8_ptr = *from_u8_ptr; 298 } 299 } 300 301 /** 302 * xemaclite_send_data - Send an Ethernet frame 303 * @drvdata: Pointer to the Emaclite device private data 304 * @data: Pointer to the data to be sent 305 * @byte_count: Total frame size, including header 306 * 307 * This function checks if the Tx buffer of the Emaclite device is free to send 308 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 309 * returns an error. 310 * 311 * Return: 0 upon success or -1 if the buffer(s) are full. 312 * 313 * Note: The maximum Tx packet size can not be more than Ethernet header 314 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 315 */ 316 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 317 unsigned int byte_count) 318 { 319 u32 reg_data; 320 void __iomem *addr; 321 322 /* Determine the expected Tx buffer address */ 323 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 324 325 /* If the length is too large, truncate it */ 326 if (byte_count > ETH_FRAME_LEN) 327 byte_count = ETH_FRAME_LEN; 328 329 /* Check if the expected buffer is available */ 330 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 331 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 332 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 333 334 /* Switch to next buffer if configured */ 335 if (drvdata->tx_ping_pong != 0) 336 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 337 } else if (drvdata->tx_ping_pong != 0) { 338 /* If the expected buffer is full, try the other buffer, 339 * if it is configured in HW */ 340 341 addr = (void __iomem __force *)((u32 __force)addr ^ 342 XEL_BUFFER_OFFSET); 343 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 344 345 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 346 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 347 return -1; /* Buffers were full, return failure */ 348 } else 349 return -1; /* Buffer was full, return failure */ 350 351 /* Write the frame to the buffer */ 352 xemaclite_aligned_write(data, (u32 __force *) addr, byte_count); 353 354 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 355 addr + XEL_TPLR_OFFSET); 356 357 /* Update the Tx Status Register to indicate that there is a 358 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 359 * is used by the interrupt handler to check whether a frame 360 * has been transmitted */ 361 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 362 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 363 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 364 365 return 0; 366 } 367 368 /** 369 * xemaclite_recv_data - Receive a frame 370 * @drvdata: Pointer to the Emaclite device private data 371 * @data: Address where the data is to be received 372 * 373 * This function is intended to be called from the interrupt context or 374 * with a wrapper which waits for the receive frame to be available. 375 * 376 * Return: Total number of bytes received 377 */ 378 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 379 { 380 void __iomem *addr; 381 u16 length, proto_type; 382 u32 reg_data; 383 384 /* Determine the expected buffer address */ 385 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 386 387 /* Verify which buffer has valid data */ 388 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 389 390 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 391 if (drvdata->rx_ping_pong != 0) 392 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 393 } else { 394 /* The instance is out of sync, try other buffer if other 395 * buffer is configured, return 0 otherwise. If the instance is 396 * out of sync, do not update the 'next_rx_buf_to_use' since it 397 * will correct on subsequent calls */ 398 if (drvdata->rx_ping_pong != 0) 399 addr = (void __iomem __force *)((u32 __force)addr ^ 400 XEL_BUFFER_OFFSET); 401 else 402 return 0; /* No data was available */ 403 404 /* Verify that buffer has valid data */ 405 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 406 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 407 XEL_RSR_RECV_DONE_MASK) 408 return 0; /* No data was available */ 409 } 410 411 /* Get the protocol type of the ethernet frame that arrived */ 412 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 413 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 414 XEL_RPLR_LENGTH_MASK); 415 416 /* Check if received ethernet frame is a raw ethernet frame 417 * or an IP packet or an ARP packet */ 418 if (proto_type > ETH_DATA_LEN) { 419 420 if (proto_type == ETH_P_IP) { 421 length = ((ntohl(xemaclite_readl(addr + 422 XEL_HEADER_IP_LENGTH_OFFSET + 423 XEL_RXBUFF_OFFSET)) >> 424 XEL_HEADER_SHIFT) & 425 XEL_RPLR_LENGTH_MASK); 426 length = min_t(u16, length, ETH_DATA_LEN); 427 length += ETH_HLEN + ETH_FCS_LEN; 428 429 } else if (proto_type == ETH_P_ARP) 430 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 431 else 432 /* Field contains type other than IP or ARP, use max 433 * frame size and let user parse it */ 434 length = ETH_FRAME_LEN + ETH_FCS_LEN; 435 } else 436 /* Use the length in the frame, plus the header and trailer */ 437 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 438 439 if (WARN_ON(length > maxlen)) 440 length = maxlen; 441 442 /* Read from the EmacLite device */ 443 xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET), 444 data, length); 445 446 /* Acknowledge the frame */ 447 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 448 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 449 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 450 451 return length; 452 } 453 454 /** 455 * xemaclite_update_address - Update the MAC address in the device 456 * @drvdata: Pointer to the Emaclite device private data 457 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 458 * 459 * Tx must be idle and Rx should be idle for deterministic results. 460 * It is recommended that this function should be called after the 461 * initialization and before transmission of any packets from the device. 462 * The MAC address can be programmed using any of the two transmit 463 * buffers (if configured). 464 */ 465 static void xemaclite_update_address(struct net_local *drvdata, 466 u8 *address_ptr) 467 { 468 void __iomem *addr; 469 u32 reg_data; 470 471 /* Determine the expected Tx buffer address */ 472 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 473 474 xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN); 475 476 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 477 478 /* Update the MAC address in the EmacLite */ 479 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 480 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 481 482 /* Wait for EmacLite to finish with the MAC address update */ 483 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 484 XEL_TSR_PROG_MAC_ADDR) != 0) 485 ; 486 } 487 488 /** 489 * xemaclite_set_mac_address - Set the MAC address for this device 490 * @dev: Pointer to the network device instance 491 * @addr: Void pointer to the sockaddr structure 492 * 493 * This function copies the HW address from the sockaddr strucutre to the 494 * net_device structure and updates the address in HW. 495 * 496 * Return: Error if the net device is busy or 0 if the addr is set 497 * successfully 498 */ 499 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 500 { 501 struct net_local *lp = netdev_priv(dev); 502 struct sockaddr *addr = address; 503 504 if (netif_running(dev)) 505 return -EBUSY; 506 507 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 508 xemaclite_update_address(lp, dev->dev_addr); 509 return 0; 510 } 511 512 /** 513 * xemaclite_tx_timeout - Callback for Tx Timeout 514 * @dev: Pointer to the network device 515 * 516 * This function is called when Tx time out occurs for Emaclite device. 517 */ 518 static void xemaclite_tx_timeout(struct net_device *dev) 519 { 520 struct net_local *lp = netdev_priv(dev); 521 unsigned long flags; 522 523 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 524 TX_TIMEOUT * 1000UL / HZ); 525 526 dev->stats.tx_errors++; 527 528 /* Reset the device */ 529 spin_lock_irqsave(&lp->reset_lock, flags); 530 531 /* Shouldn't really be necessary, but shouldn't hurt */ 532 netif_stop_queue(dev); 533 534 xemaclite_disable_interrupts(lp); 535 xemaclite_enable_interrupts(lp); 536 537 if (lp->deferred_skb) { 538 dev_kfree_skb(lp->deferred_skb); 539 lp->deferred_skb = NULL; 540 dev->stats.tx_errors++; 541 } 542 543 /* To exclude tx timeout */ 544 netif_trans_update(dev); /* prevent tx timeout */ 545 546 /* We're all ready to go. Start the queue */ 547 netif_wake_queue(dev); 548 spin_unlock_irqrestore(&lp->reset_lock, flags); 549 } 550 551 /**********************/ 552 /* Interrupt Handlers */ 553 /**********************/ 554 555 /** 556 * xemaclite_tx_handler - Interrupt handler for frames sent 557 * @dev: Pointer to the network device 558 * 559 * This function updates the number of packets transmitted and handles the 560 * deferred skb, if there is one. 561 */ 562 static void xemaclite_tx_handler(struct net_device *dev) 563 { 564 struct net_local *lp = netdev_priv(dev); 565 566 dev->stats.tx_packets++; 567 if (lp->deferred_skb) { 568 if (xemaclite_send_data(lp, 569 (u8 *) lp->deferred_skb->data, 570 lp->deferred_skb->len) != 0) 571 return; 572 else { 573 dev->stats.tx_bytes += lp->deferred_skb->len; 574 dev_kfree_skb_irq(lp->deferred_skb); 575 lp->deferred_skb = NULL; 576 netif_trans_update(dev); /* prevent tx timeout */ 577 netif_wake_queue(dev); 578 } 579 } 580 } 581 582 /** 583 * xemaclite_rx_handler- Interrupt handler for frames received 584 * @dev: Pointer to the network device 585 * 586 * This function allocates memory for a socket buffer, fills it with data 587 * received and hands it over to the TCP/IP stack. 588 */ 589 static void xemaclite_rx_handler(struct net_device *dev) 590 { 591 struct net_local *lp = netdev_priv(dev); 592 struct sk_buff *skb; 593 unsigned int align; 594 u32 len; 595 596 len = ETH_FRAME_LEN + ETH_FCS_LEN; 597 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 598 if (!skb) { 599 /* Couldn't get memory. */ 600 dev->stats.rx_dropped++; 601 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 602 return; 603 } 604 605 /* 606 * A new skb should have the data halfword aligned, but this code is 607 * here just in case that isn't true. Calculate how many 608 * bytes we should reserve to get the data to start on a word 609 * boundary */ 610 align = BUFFER_ALIGN(skb->data); 611 if (align) 612 skb_reserve(skb, align); 613 614 skb_reserve(skb, 2); 615 616 len = xemaclite_recv_data(lp, (u8 *) skb->data, len); 617 618 if (!len) { 619 dev->stats.rx_errors++; 620 dev_kfree_skb_irq(skb); 621 return; 622 } 623 624 skb_put(skb, len); /* Tell the skb how much data we got */ 625 626 skb->protocol = eth_type_trans(skb, dev); 627 skb_checksum_none_assert(skb); 628 629 dev->stats.rx_packets++; 630 dev->stats.rx_bytes += len; 631 632 if (!skb_defer_rx_timestamp(skb)) 633 netif_rx(skb); /* Send the packet upstream */ 634 } 635 636 /** 637 * xemaclite_interrupt - Interrupt handler for this driver 638 * @irq: Irq of the Emaclite device 639 * @dev_id: Void pointer to the network device instance used as callback 640 * reference 641 * 642 * This function handles the Tx and Rx interrupts of the EmacLite device. 643 */ 644 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 645 { 646 bool tx_complete = false; 647 struct net_device *dev = dev_id; 648 struct net_local *lp = netdev_priv(dev); 649 void __iomem *base_addr = lp->base_addr; 650 u32 tx_status; 651 652 /* Check if there is Rx Data available */ 653 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 654 XEL_RSR_RECV_DONE_MASK) || 655 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 656 & XEL_RSR_RECV_DONE_MASK)) 657 658 xemaclite_rx_handler(dev); 659 660 /* Check if the Transmission for the first buffer is completed */ 661 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 662 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 663 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 664 665 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 666 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 667 668 tx_complete = true; 669 } 670 671 /* Check if the Transmission for the second buffer is completed */ 672 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 673 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 674 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 675 676 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 677 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 678 XEL_TSR_OFFSET); 679 680 tx_complete = true; 681 } 682 683 /* If there was a Tx interrupt, call the Tx Handler */ 684 if (tx_complete != 0) 685 xemaclite_tx_handler(dev); 686 687 return IRQ_HANDLED; 688 } 689 690 /**********************/ 691 /* MDIO Bus functions */ 692 /**********************/ 693 694 /** 695 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 696 * @lp: Pointer to the Emaclite device private data 697 * 698 * This function waits till the device is ready to accept a new MDIO 699 * request. 700 * 701 * Return: 0 for success or ETIMEDOUT for a timeout 702 */ 703 704 static int xemaclite_mdio_wait(struct net_local *lp) 705 { 706 unsigned long end = jiffies + 2; 707 708 /* wait for the MDIO interface to not be busy or timeout 709 after some time. 710 */ 711 while (xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) & 712 XEL_MDIOCTRL_MDIOSTS_MASK) { 713 if (time_before_eq(end, jiffies)) { 714 WARN_ON(1); 715 return -ETIMEDOUT; 716 } 717 msleep(1); 718 } 719 return 0; 720 } 721 722 /** 723 * xemaclite_mdio_read - Read from a given MII management register 724 * @bus: the mii_bus struct 725 * @phy_id: the phy address 726 * @reg: register number to read from 727 * 728 * This function waits till the device is ready to accept a new MDIO 729 * request and then writes the phy address to the MDIO Address register 730 * and reads data from MDIO Read Data register, when its available. 731 * 732 * Return: Value read from the MII management register 733 */ 734 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 735 { 736 struct net_local *lp = bus->priv; 737 u32 ctrl_reg; 738 u32 rc; 739 740 if (xemaclite_mdio_wait(lp)) 741 return -ETIMEDOUT; 742 743 /* Write the PHY address, register number and set the OP bit in the 744 * MDIO Address register. Set the Status bit in the MDIO Control 745 * register to start a MDIO read transaction. 746 */ 747 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 748 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 749 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 750 lp->base_addr + XEL_MDIOADDR_OFFSET); 751 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 752 lp->base_addr + XEL_MDIOCTRL_OFFSET); 753 754 if (xemaclite_mdio_wait(lp)) 755 return -ETIMEDOUT; 756 757 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 758 759 dev_dbg(&lp->ndev->dev, 760 "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n", 761 phy_id, reg, rc); 762 763 return rc; 764 } 765 766 /** 767 * xemaclite_mdio_write - Write to a given MII management register 768 * @bus: the mii_bus struct 769 * @phy_id: the phy address 770 * @reg: register number to write to 771 * @val: value to write to the register number specified by reg 772 * 773 * This function waits till the device is ready to accept a new MDIO 774 * request and then writes the val to the MDIO Write Data register. 775 */ 776 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 777 u16 val) 778 { 779 struct net_local *lp = bus->priv; 780 u32 ctrl_reg; 781 782 dev_dbg(&lp->ndev->dev, 783 "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n", 784 phy_id, reg, val); 785 786 if (xemaclite_mdio_wait(lp)) 787 return -ETIMEDOUT; 788 789 /* Write the PHY address, register number and clear the OP bit in the 790 * MDIO Address register and then write the value into the MDIO Write 791 * Data register. Finally, set the Status bit in the MDIO Control 792 * register to start a MDIO write transaction. 793 */ 794 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 795 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 796 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 797 lp->base_addr + XEL_MDIOADDR_OFFSET); 798 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 799 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 800 lp->base_addr + XEL_MDIOCTRL_OFFSET); 801 802 return 0; 803 } 804 805 /** 806 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 807 * @lp: Pointer to the Emaclite device private data 808 * @ofdev: Pointer to OF device structure 809 * 810 * This function enables MDIO bus in the Emaclite device and registers a 811 * mii_bus. 812 * 813 * Return: 0 upon success or a negative error upon failure 814 */ 815 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 816 { 817 struct mii_bus *bus; 818 int rc; 819 struct resource res; 820 struct device_node *np = of_get_parent(lp->phy_node); 821 struct device_node *npp; 822 823 /* Don't register the MDIO bus if the phy_node or its parent node 824 * can't be found. 825 */ 826 if (!np) { 827 dev_err(dev, "Failed to register mdio bus.\n"); 828 return -ENODEV; 829 } 830 npp = of_get_parent(np); 831 832 of_address_to_resource(npp, 0, &res); 833 if (lp->ndev->mem_start != res.start) { 834 struct phy_device *phydev; 835 phydev = of_phy_find_device(lp->phy_node); 836 if (!phydev) 837 dev_info(dev, 838 "MDIO of the phy is not registered yet\n"); 839 else 840 put_device(&phydev->mdio.dev); 841 return 0; 842 } 843 844 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 845 * register. 846 */ 847 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 848 lp->base_addr + XEL_MDIOCTRL_OFFSET); 849 850 bus = mdiobus_alloc(); 851 if (!bus) { 852 dev_err(dev, "Failed to allocate mdiobus\n"); 853 return -ENOMEM; 854 } 855 856 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 857 (unsigned long long)res.start); 858 bus->priv = lp; 859 bus->name = "Xilinx Emaclite MDIO"; 860 bus->read = xemaclite_mdio_read; 861 bus->write = xemaclite_mdio_write; 862 bus->parent = dev; 863 864 rc = of_mdiobus_register(bus, np); 865 if (rc) { 866 dev_err(dev, "Failed to register mdio bus.\n"); 867 goto err_register; 868 } 869 870 lp->mii_bus = bus; 871 872 return 0; 873 874 err_register: 875 mdiobus_free(bus); 876 return rc; 877 } 878 879 /** 880 * xemaclite_adjust_link - Link state callback for the Emaclite device 881 * @ndev: pointer to net_device struct 882 * 883 * There's nothing in the Emaclite device to be configured when the link 884 * state changes. We just print the status. 885 */ 886 static void xemaclite_adjust_link(struct net_device *ndev) 887 { 888 struct net_local *lp = netdev_priv(ndev); 889 struct phy_device *phy = lp->phy_dev; 890 int link_state; 891 892 /* hash together the state values to decide if something has changed */ 893 link_state = phy->speed | (phy->duplex << 1) | phy->link; 894 895 if (lp->last_link != link_state) { 896 lp->last_link = link_state; 897 phy_print_status(phy); 898 } 899 } 900 901 /** 902 * xemaclite_open - Open the network device 903 * @dev: Pointer to the network device 904 * 905 * This function sets the MAC address, requests an IRQ and enables interrupts 906 * for the Emaclite device and starts the Tx queue. 907 * It also connects to the phy device, if MDIO is included in Emaclite device. 908 */ 909 static int xemaclite_open(struct net_device *dev) 910 { 911 struct net_local *lp = netdev_priv(dev); 912 int retval; 913 914 /* Just to be safe, stop the device first */ 915 xemaclite_disable_interrupts(lp); 916 917 if (lp->phy_node) { 918 u32 bmcr; 919 920 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 921 xemaclite_adjust_link, 0, 922 PHY_INTERFACE_MODE_MII); 923 if (!lp->phy_dev) { 924 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 925 return -ENODEV; 926 } 927 928 /* EmacLite doesn't support giga-bit speeds */ 929 lp->phy_dev->supported &= (PHY_BASIC_FEATURES); 930 lp->phy_dev->advertising = lp->phy_dev->supported; 931 932 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 933 phy_write(lp->phy_dev, MII_CTRL1000, 0); 934 935 /* Advertise only 10 and 100mbps full/half duplex speeds */ 936 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 937 ADVERTISE_CSMA); 938 939 /* Restart auto negotiation */ 940 bmcr = phy_read(lp->phy_dev, MII_BMCR); 941 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 942 phy_write(lp->phy_dev, MII_BMCR, bmcr); 943 944 phy_start(lp->phy_dev); 945 } 946 947 /* Set the MAC address each time opened */ 948 xemaclite_update_address(lp, dev->dev_addr); 949 950 /* Grab the IRQ */ 951 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 952 if (retval) { 953 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 954 dev->irq); 955 if (lp->phy_dev) 956 phy_disconnect(lp->phy_dev); 957 lp->phy_dev = NULL; 958 959 return retval; 960 } 961 962 /* Enable Interrupts */ 963 xemaclite_enable_interrupts(lp); 964 965 /* We're ready to go */ 966 netif_start_queue(dev); 967 968 return 0; 969 } 970 971 /** 972 * xemaclite_close - Close the network device 973 * @dev: Pointer to the network device 974 * 975 * This function stops the Tx queue, disables interrupts and frees the IRQ for 976 * the Emaclite device. 977 * It also disconnects the phy device associated with the Emaclite device. 978 */ 979 static int xemaclite_close(struct net_device *dev) 980 { 981 struct net_local *lp = netdev_priv(dev); 982 983 netif_stop_queue(dev); 984 xemaclite_disable_interrupts(lp); 985 free_irq(dev->irq, dev); 986 987 if (lp->phy_dev) 988 phy_disconnect(lp->phy_dev); 989 lp->phy_dev = NULL; 990 991 return 0; 992 } 993 994 /** 995 * xemaclite_send - Transmit a frame 996 * @orig_skb: Pointer to the socket buffer to be transmitted 997 * @dev: Pointer to the network device 998 * 999 * This function checks if the Tx buffer of the Emaclite device is free to send 1000 * data. If so, it fills the Tx buffer with data from socket buffer data, 1001 * updates the stats and frees the socket buffer. The Tx completion is signaled 1002 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1003 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1004 * be transmitted when the Emaclite device is free to transmit data. 1005 * 1006 * Return: 0, always. 1007 */ 1008 static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1009 { 1010 struct net_local *lp = netdev_priv(dev); 1011 struct sk_buff *new_skb; 1012 unsigned int len; 1013 unsigned long flags; 1014 1015 len = orig_skb->len; 1016 1017 new_skb = orig_skb; 1018 1019 spin_lock_irqsave(&lp->reset_lock, flags); 1020 if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) { 1021 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1022 * defer the skb for transmission during the ISR, after the 1023 * current transmission is complete */ 1024 netif_stop_queue(dev); 1025 lp->deferred_skb = new_skb; 1026 /* Take the time stamp now, since we can't do this in an ISR. */ 1027 skb_tx_timestamp(new_skb); 1028 spin_unlock_irqrestore(&lp->reset_lock, flags); 1029 return 0; 1030 } 1031 spin_unlock_irqrestore(&lp->reset_lock, flags); 1032 1033 skb_tx_timestamp(new_skb); 1034 1035 dev->stats.tx_bytes += len; 1036 dev_consume_skb_any(new_skb); 1037 1038 return 0; 1039 } 1040 1041 /** 1042 * get_bool - Get a parameter from the OF device 1043 * @ofdev: Pointer to OF device structure 1044 * @s: Property to be retrieved 1045 * 1046 * This function looks for a property in the device node and returns the value 1047 * of the property if its found or 0 if the property is not found. 1048 * 1049 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1050 */ 1051 static bool get_bool(struct platform_device *ofdev, const char *s) 1052 { 1053 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1054 1055 if (p) { 1056 return (bool)*p; 1057 } else { 1058 dev_warn(&ofdev->dev, "Parameter %s not found," 1059 "defaulting to false\n", s); 1060 return false; 1061 } 1062 } 1063 1064 static const struct net_device_ops xemaclite_netdev_ops; 1065 1066 /** 1067 * xemaclite_of_probe - Probe method for the Emaclite device. 1068 * @ofdev: Pointer to OF device structure 1069 * @match: Pointer to the structure used for matching a device 1070 * 1071 * This function probes for the Emaclite device in the device tree. 1072 * It initializes the driver data structure and the hardware, sets the MAC 1073 * address and registers the network device. 1074 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1075 * in the device. 1076 * 1077 * Return: 0, if the driver is bound to the Emaclite device, or 1078 * a negative error if there is failure. 1079 */ 1080 static int xemaclite_of_probe(struct platform_device *ofdev) 1081 { 1082 struct resource *res; 1083 struct net_device *ndev = NULL; 1084 struct net_local *lp = NULL; 1085 struct device *dev = &ofdev->dev; 1086 const void *mac_address; 1087 1088 int rc = 0; 1089 1090 dev_info(dev, "Device Tree Probing\n"); 1091 1092 /* Create an ethernet device instance */ 1093 ndev = alloc_etherdev(sizeof(struct net_local)); 1094 if (!ndev) 1095 return -ENOMEM; 1096 1097 dev_set_drvdata(dev, ndev); 1098 SET_NETDEV_DEV(ndev, &ofdev->dev); 1099 1100 lp = netdev_priv(ndev); 1101 lp->ndev = ndev; 1102 1103 /* Get IRQ for the device */ 1104 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1105 if (!res) { 1106 dev_err(dev, "no IRQ found\n"); 1107 rc = -ENXIO; 1108 goto error; 1109 } 1110 1111 ndev->irq = res->start; 1112 1113 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1114 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1115 if (IS_ERR(lp->base_addr)) { 1116 rc = PTR_ERR(lp->base_addr); 1117 goto error; 1118 } 1119 1120 ndev->mem_start = res->start; 1121 ndev->mem_end = res->end; 1122 1123 spin_lock_init(&lp->reset_lock); 1124 lp->next_tx_buf_to_use = 0x0; 1125 lp->next_rx_buf_to_use = 0x0; 1126 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1127 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1128 mac_address = of_get_mac_address(ofdev->dev.of_node); 1129 1130 if (mac_address) { 1131 /* Set the MAC address. */ 1132 memcpy(ndev->dev_addr, mac_address, ETH_ALEN); 1133 } else { 1134 dev_warn(dev, "No MAC address found, using random\n"); 1135 eth_hw_addr_random(ndev); 1136 } 1137 1138 /* Clear the Tx CSR's in case this is a restart */ 1139 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1140 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1141 1142 /* Set the MAC address in the EmacLite device */ 1143 xemaclite_update_address(lp, ndev->dev_addr); 1144 1145 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1146 xemaclite_mdio_setup(lp, &ofdev->dev); 1147 1148 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1149 1150 ndev->netdev_ops = &xemaclite_netdev_ops; 1151 ndev->flags &= ~IFF_MULTICAST; 1152 ndev->watchdog_timeo = TX_TIMEOUT; 1153 1154 /* Finally, register the device */ 1155 rc = register_netdev(ndev); 1156 if (rc) { 1157 dev_err(dev, 1158 "Cannot register network device, aborting\n"); 1159 goto error; 1160 } 1161 1162 dev_info(dev, 1163 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1164 (unsigned int __force)ndev->mem_start, 1165 (unsigned int __force)lp->base_addr, ndev->irq); 1166 return 0; 1167 1168 error: 1169 free_netdev(ndev); 1170 return rc; 1171 } 1172 1173 /** 1174 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1175 * @of_dev: Pointer to OF device structure 1176 * 1177 * This function is called if a device is physically removed from the system or 1178 * if the driver module is being unloaded. It frees any resources allocated to 1179 * the device. 1180 * 1181 * Return: 0, always. 1182 */ 1183 static int xemaclite_of_remove(struct platform_device *of_dev) 1184 { 1185 struct net_device *ndev = platform_get_drvdata(of_dev); 1186 1187 struct net_local *lp = netdev_priv(ndev); 1188 1189 /* Un-register the mii_bus, if configured */ 1190 if (lp->mii_bus) { 1191 mdiobus_unregister(lp->mii_bus); 1192 mdiobus_free(lp->mii_bus); 1193 lp->mii_bus = NULL; 1194 } 1195 1196 unregister_netdev(ndev); 1197 1198 of_node_put(lp->phy_node); 1199 lp->phy_node = NULL; 1200 1201 free_netdev(ndev); 1202 1203 return 0; 1204 } 1205 1206 #ifdef CONFIG_NET_POLL_CONTROLLER 1207 static void 1208 xemaclite_poll_controller(struct net_device *ndev) 1209 { 1210 disable_irq(ndev->irq); 1211 xemaclite_interrupt(ndev->irq, ndev); 1212 enable_irq(ndev->irq); 1213 } 1214 #endif 1215 1216 static const struct net_device_ops xemaclite_netdev_ops = { 1217 .ndo_open = xemaclite_open, 1218 .ndo_stop = xemaclite_close, 1219 .ndo_start_xmit = xemaclite_send, 1220 .ndo_set_mac_address = xemaclite_set_mac_address, 1221 .ndo_tx_timeout = xemaclite_tx_timeout, 1222 #ifdef CONFIG_NET_POLL_CONTROLLER 1223 .ndo_poll_controller = xemaclite_poll_controller, 1224 #endif 1225 }; 1226 1227 /* Match table for OF platform binding */ 1228 static const struct of_device_id xemaclite_of_match[] = { 1229 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1230 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1231 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1232 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1233 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1234 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1235 { /* end of list */ }, 1236 }; 1237 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1238 1239 static struct platform_driver xemaclite_of_driver = { 1240 .driver = { 1241 .name = DRIVER_NAME, 1242 .of_match_table = xemaclite_of_match, 1243 }, 1244 .probe = xemaclite_of_probe, 1245 .remove = xemaclite_of_remove, 1246 }; 1247 1248 module_platform_driver(xemaclite_of_driver); 1249 1250 MODULE_AUTHOR("Xilinx, Inc."); 1251 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1252 MODULE_LICENSE("GPL"); 1253