1 /* 2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/uaccess.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/skbuff.h> 20 #include <linux/ethtool.h> 21 #include <linux/io.h> 22 #include <linux/slab.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/phy.h> 29 #include <linux/interrupt.h> 30 31 #define DRIVER_NAME "xilinx_emaclite" 32 33 /* Register offsets for the EmacLite Core */ 34 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 35 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 36 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 37 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 38 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 39 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 40 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 41 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 42 43 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 44 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 45 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 46 47 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 48 49 /* MDIO Address Register Bit Masks */ 50 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 51 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 52 #define XEL_MDIOADDR_PHYADR_SHIFT 5 53 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 54 55 /* MDIO Write Data Register Bit Masks */ 56 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 57 58 /* MDIO Read Data Register Bit Masks */ 59 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 60 61 /* MDIO Control Register Bit Masks */ 62 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 63 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 64 65 /* Global Interrupt Enable Register (GIER) Bit Masks */ 66 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 67 68 /* Transmit Status Register (TSR) Bit Masks */ 69 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 70 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 71 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 72 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 73 * only. This is not documented 74 * in the HW spec 75 */ 76 77 /* Define for programming the MAC address into the EmacLite */ 78 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 79 80 /* Receive Status Register (RSR) */ 81 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 82 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 83 84 /* Transmit Packet Length Register (TPLR) */ 85 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 86 87 /* Receive Packet Length Register (RPLR) */ 88 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 89 90 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 91 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 92 93 /* General Ethernet Definitions */ 94 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 95 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 96 97 98 99 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 100 #define ALIGNMENT 4 101 102 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 103 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32)adr)) % ALIGNMENT) 104 105 #ifdef __BIG_ENDIAN 106 #define xemaclite_readl ioread32be 107 #define xemaclite_writel iowrite32be 108 #else 109 #define xemaclite_readl ioread32 110 #define xemaclite_writel iowrite32 111 #endif 112 113 /** 114 * struct net_local - Our private per device data 115 * @ndev: instance of the network device 116 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 117 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 118 * @next_tx_buf_to_use: next Tx buffer to write to 119 * @next_rx_buf_to_use: next Rx buffer to read from 120 * @base_addr: base address of the Emaclite device 121 * @reset_lock: lock used for synchronization 122 * @deferred_skb: holds an skb (for transmission at a later time) when the 123 * Tx buffer is not free 124 * @phy_dev: pointer to the PHY device 125 * @phy_node: pointer to the PHY device node 126 * @mii_bus: pointer to the MII bus 127 * @last_link: last link status 128 */ 129 struct net_local { 130 131 struct net_device *ndev; 132 133 bool tx_ping_pong; 134 bool rx_ping_pong; 135 u32 next_tx_buf_to_use; 136 u32 next_rx_buf_to_use; 137 void __iomem *base_addr; 138 139 spinlock_t reset_lock; 140 struct sk_buff *deferred_skb; 141 142 struct phy_device *phy_dev; 143 struct device_node *phy_node; 144 145 struct mii_bus *mii_bus; 146 147 int last_link; 148 }; 149 150 151 /*************************/ 152 /* EmacLite driver calls */ 153 /*************************/ 154 155 /** 156 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 157 * @drvdata: Pointer to the Emaclite device private data 158 * 159 * This function enables the Tx and Rx interrupts for the Emaclite device along 160 * with the Global Interrupt Enable. 161 */ 162 static void xemaclite_enable_interrupts(struct net_local *drvdata) 163 { 164 u32 reg_data; 165 166 /* Enable the Tx interrupts for the first Buffer */ 167 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 168 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 169 drvdata->base_addr + XEL_TSR_OFFSET); 170 171 /* Enable the Rx interrupts for the first buffer */ 172 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 173 174 /* Enable the Global Interrupt Enable */ 175 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 176 } 177 178 /** 179 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 180 * @drvdata: Pointer to the Emaclite device private data 181 * 182 * This function disables the Tx and Rx interrupts for the Emaclite device, 183 * along with the Global Interrupt Enable. 184 */ 185 static void xemaclite_disable_interrupts(struct net_local *drvdata) 186 { 187 u32 reg_data; 188 189 /* Disable the Global Interrupt Enable */ 190 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 191 192 /* Disable the Tx interrupts for the first buffer */ 193 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 194 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 195 drvdata->base_addr + XEL_TSR_OFFSET); 196 197 /* Disable the Rx interrupts for the first buffer */ 198 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 199 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 200 drvdata->base_addr + XEL_RSR_OFFSET); 201 } 202 203 /** 204 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 205 * @src_ptr: Void pointer to the 16-bit aligned source address 206 * @dest_ptr: Pointer to the 32-bit aligned destination address 207 * @length: Number bytes to write from source to destination 208 * 209 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 210 * address in the EmacLite device. 211 */ 212 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 213 unsigned length) 214 { 215 u32 align_buffer; 216 u32 *to_u32_ptr; 217 u16 *from_u16_ptr, *to_u16_ptr; 218 219 to_u32_ptr = dest_ptr; 220 from_u16_ptr = src_ptr; 221 align_buffer = 0; 222 223 for (; length > 3; length -= 4) { 224 to_u16_ptr = (u16 *)&align_buffer; 225 *to_u16_ptr++ = *from_u16_ptr++; 226 *to_u16_ptr++ = *from_u16_ptr++; 227 228 /* This barrier resolves occasional issues seen around 229 * cases where the data is not properly flushed out 230 * from the processor store buffers to the destination 231 * memory locations. 232 */ 233 wmb(); 234 235 /* Output a word */ 236 *to_u32_ptr++ = align_buffer; 237 } 238 if (length) { 239 u8 *from_u8_ptr, *to_u8_ptr; 240 241 /* Set up to output the remaining data */ 242 align_buffer = 0; 243 to_u8_ptr = (u8 *)&align_buffer; 244 from_u8_ptr = (u8 *)from_u16_ptr; 245 246 /* Output the remaining data */ 247 for (; length > 0; length--) 248 *to_u8_ptr++ = *from_u8_ptr++; 249 250 /* This barrier resolves occasional issues seen around 251 * cases where the data is not properly flushed out 252 * from the processor store buffers to the destination 253 * memory locations. 254 */ 255 wmb(); 256 *to_u32_ptr = align_buffer; 257 } 258 } 259 260 /** 261 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 262 * @src_ptr: Pointer to the 32-bit aligned source address 263 * @dest_ptr: Pointer to the 16-bit aligned destination address 264 * @length: Number bytes to read from source to destination 265 * 266 * This function reads data from a 32-bit aligned address in the EmacLite device 267 * to a 16-bit aligned buffer. 268 */ 269 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 270 unsigned length) 271 { 272 u16 *to_u16_ptr, *from_u16_ptr; 273 u32 *from_u32_ptr; 274 u32 align_buffer; 275 276 from_u32_ptr = src_ptr; 277 to_u16_ptr = (u16 *)dest_ptr; 278 279 for (; length > 3; length -= 4) { 280 /* Copy each word into the temporary buffer */ 281 align_buffer = *from_u32_ptr++; 282 from_u16_ptr = (u16 *)&align_buffer; 283 284 /* Read data from source */ 285 *to_u16_ptr++ = *from_u16_ptr++; 286 *to_u16_ptr++ = *from_u16_ptr++; 287 } 288 289 if (length) { 290 u8 *to_u8_ptr, *from_u8_ptr; 291 292 /* Set up to read the remaining data */ 293 to_u8_ptr = (u8 *)to_u16_ptr; 294 align_buffer = *from_u32_ptr++; 295 from_u8_ptr = (u8 *)&align_buffer; 296 297 /* Read the remaining data */ 298 for (; length > 0; length--) 299 *to_u8_ptr = *from_u8_ptr; 300 } 301 } 302 303 /** 304 * xemaclite_send_data - Send an Ethernet frame 305 * @drvdata: Pointer to the Emaclite device private data 306 * @data: Pointer to the data to be sent 307 * @byte_count: Total frame size, including header 308 * 309 * This function checks if the Tx buffer of the Emaclite device is free to send 310 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 311 * returns an error. 312 * 313 * Return: 0 upon success or -1 if the buffer(s) are full. 314 * 315 * Note: The maximum Tx packet size can not be more than Ethernet header 316 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 317 */ 318 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 319 unsigned int byte_count) 320 { 321 u32 reg_data; 322 void __iomem *addr; 323 324 /* Determine the expected Tx buffer address */ 325 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 326 327 /* If the length is too large, truncate it */ 328 if (byte_count > ETH_FRAME_LEN) 329 byte_count = ETH_FRAME_LEN; 330 331 /* Check if the expected buffer is available */ 332 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 333 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 334 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 335 336 /* Switch to next buffer if configured */ 337 if (drvdata->tx_ping_pong != 0) 338 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 339 } else if (drvdata->tx_ping_pong != 0) { 340 /* If the expected buffer is full, try the other buffer, 341 * if it is configured in HW 342 */ 343 344 addr = (void __iomem __force *)((u32 __force)addr ^ 345 XEL_BUFFER_OFFSET); 346 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 347 348 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 349 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 350 return -1; /* Buffers were full, return failure */ 351 } else 352 return -1; /* Buffer was full, return failure */ 353 354 /* Write the frame to the buffer */ 355 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 356 357 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 358 addr + XEL_TPLR_OFFSET); 359 360 /* Update the Tx Status Register to indicate that there is a 361 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 362 * is used by the interrupt handler to check whether a frame 363 * has been transmitted 364 */ 365 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 366 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 367 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 368 369 return 0; 370 } 371 372 /** 373 * xemaclite_recv_data - Receive a frame 374 * @drvdata: Pointer to the Emaclite device private data 375 * @data: Address where the data is to be received 376 * @maxlen: Maximum supported ethernet packet length 377 * 378 * This function is intended to be called from the interrupt context or 379 * with a wrapper which waits for the receive frame to be available. 380 * 381 * Return: Total number of bytes received 382 */ 383 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 384 { 385 void __iomem *addr; 386 u16 length, proto_type; 387 u32 reg_data; 388 389 /* Determine the expected buffer address */ 390 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 391 392 /* Verify which buffer has valid data */ 393 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 394 395 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 396 if (drvdata->rx_ping_pong != 0) 397 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 398 } else { 399 /* The instance is out of sync, try other buffer if other 400 * buffer is configured, return 0 otherwise. If the instance is 401 * out of sync, do not update the 'next_rx_buf_to_use' since it 402 * will correct on subsequent calls 403 */ 404 if (drvdata->rx_ping_pong != 0) 405 addr = (void __iomem __force *)((u32 __force)addr ^ 406 XEL_BUFFER_OFFSET); 407 else 408 return 0; /* No data was available */ 409 410 /* Verify that buffer has valid data */ 411 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 412 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 413 XEL_RSR_RECV_DONE_MASK) 414 return 0; /* No data was available */ 415 } 416 417 /* Get the protocol type of the ethernet frame that arrived 418 */ 419 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 420 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 421 XEL_RPLR_LENGTH_MASK); 422 423 /* Check if received ethernet frame is a raw ethernet frame 424 * or an IP packet or an ARP packet 425 */ 426 if (proto_type > ETH_DATA_LEN) { 427 428 if (proto_type == ETH_P_IP) { 429 length = ((ntohl(xemaclite_readl(addr + 430 XEL_HEADER_IP_LENGTH_OFFSET + 431 XEL_RXBUFF_OFFSET)) >> 432 XEL_HEADER_SHIFT) & 433 XEL_RPLR_LENGTH_MASK); 434 length = min_t(u16, length, ETH_DATA_LEN); 435 length += ETH_HLEN + ETH_FCS_LEN; 436 437 } else if (proto_type == ETH_P_ARP) 438 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 439 else 440 /* Field contains type other than IP or ARP, use max 441 * frame size and let user parse it 442 */ 443 length = ETH_FRAME_LEN + ETH_FCS_LEN; 444 } else 445 /* Use the length in the frame, plus the header and trailer */ 446 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 447 448 if (WARN_ON(length > maxlen)) 449 length = maxlen; 450 451 /* Read from the EmacLite device */ 452 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 453 data, length); 454 455 /* Acknowledge the frame */ 456 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 457 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 458 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 459 460 return length; 461 } 462 463 /** 464 * xemaclite_update_address - Update the MAC address in the device 465 * @drvdata: Pointer to the Emaclite device private data 466 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 467 * 468 * Tx must be idle and Rx should be idle for deterministic results. 469 * It is recommended that this function should be called after the 470 * initialization and before transmission of any packets from the device. 471 * The MAC address can be programmed using any of the two transmit 472 * buffers (if configured). 473 */ 474 static void xemaclite_update_address(struct net_local *drvdata, 475 u8 *address_ptr) 476 { 477 void __iomem *addr; 478 u32 reg_data; 479 480 /* Determine the expected Tx buffer address */ 481 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 482 483 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 484 485 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 486 487 /* Update the MAC address in the EmacLite */ 488 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 489 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 490 491 /* Wait for EmacLite to finish with the MAC address update */ 492 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 493 XEL_TSR_PROG_MAC_ADDR) != 0) 494 ; 495 } 496 497 /** 498 * xemaclite_set_mac_address - Set the MAC address for this device 499 * @dev: Pointer to the network device instance 500 * @address: Void pointer to the sockaddr structure 501 * 502 * This function copies the HW address from the sockaddr strucutre to the 503 * net_device structure and updates the address in HW. 504 * 505 * Return: Error if the net device is busy or 0 if the addr is set 506 * successfully 507 */ 508 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 509 { 510 struct net_local *lp = netdev_priv(dev); 511 struct sockaddr *addr = address; 512 513 if (netif_running(dev)) 514 return -EBUSY; 515 516 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 517 xemaclite_update_address(lp, dev->dev_addr); 518 return 0; 519 } 520 521 /** 522 * xemaclite_tx_timeout - Callback for Tx Timeout 523 * @dev: Pointer to the network device 524 * 525 * This function is called when Tx time out occurs for Emaclite device. 526 */ 527 static void xemaclite_tx_timeout(struct net_device *dev) 528 { 529 struct net_local *lp = netdev_priv(dev); 530 unsigned long flags; 531 532 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 533 TX_TIMEOUT * 1000UL / HZ); 534 535 dev->stats.tx_errors++; 536 537 /* Reset the device */ 538 spin_lock_irqsave(&lp->reset_lock, flags); 539 540 /* Shouldn't really be necessary, but shouldn't hurt */ 541 netif_stop_queue(dev); 542 543 xemaclite_disable_interrupts(lp); 544 xemaclite_enable_interrupts(lp); 545 546 if (lp->deferred_skb) { 547 dev_kfree_skb(lp->deferred_skb); 548 lp->deferred_skb = NULL; 549 dev->stats.tx_errors++; 550 } 551 552 /* To exclude tx timeout */ 553 netif_trans_update(dev); /* prevent tx timeout */ 554 555 /* We're all ready to go. Start the queue */ 556 netif_wake_queue(dev); 557 spin_unlock_irqrestore(&lp->reset_lock, flags); 558 } 559 560 /**********************/ 561 /* Interrupt Handlers */ 562 /**********************/ 563 564 /** 565 * xemaclite_tx_handler - Interrupt handler for frames sent 566 * @dev: Pointer to the network device 567 * 568 * This function updates the number of packets transmitted and handles the 569 * deferred skb, if there is one. 570 */ 571 static void xemaclite_tx_handler(struct net_device *dev) 572 { 573 struct net_local *lp = netdev_priv(dev); 574 575 dev->stats.tx_packets++; 576 577 if (!lp->deferred_skb) 578 return; 579 580 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 581 lp->deferred_skb->len)) 582 return; 583 584 dev->stats.tx_bytes += lp->deferred_skb->len; 585 dev_consume_skb_irq(lp->deferred_skb); 586 lp->deferred_skb = NULL; 587 netif_trans_update(dev); /* prevent tx timeout */ 588 netif_wake_queue(dev); 589 } 590 591 /** 592 * xemaclite_rx_handler- Interrupt handler for frames received 593 * @dev: Pointer to the network device 594 * 595 * This function allocates memory for a socket buffer, fills it with data 596 * received and hands it over to the TCP/IP stack. 597 */ 598 static void xemaclite_rx_handler(struct net_device *dev) 599 { 600 struct net_local *lp = netdev_priv(dev); 601 struct sk_buff *skb; 602 unsigned int align; 603 u32 len; 604 605 len = ETH_FRAME_LEN + ETH_FCS_LEN; 606 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 607 if (!skb) { 608 /* Couldn't get memory. */ 609 dev->stats.rx_dropped++; 610 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 611 return; 612 } 613 614 /* A new skb should have the data halfword aligned, but this code is 615 * here just in case that isn't true. Calculate how many 616 * bytes we should reserve to get the data to start on a word 617 * boundary 618 */ 619 align = BUFFER_ALIGN(skb->data); 620 if (align) 621 skb_reserve(skb, align); 622 623 skb_reserve(skb, 2); 624 625 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 626 627 if (!len) { 628 dev->stats.rx_errors++; 629 dev_kfree_skb_irq(skb); 630 return; 631 } 632 633 skb_put(skb, len); /* Tell the skb how much data we got */ 634 635 skb->protocol = eth_type_trans(skb, dev); 636 skb_checksum_none_assert(skb); 637 638 dev->stats.rx_packets++; 639 dev->stats.rx_bytes += len; 640 641 if (!skb_defer_rx_timestamp(skb)) 642 netif_rx(skb); /* Send the packet upstream */ 643 } 644 645 /** 646 * xemaclite_interrupt - Interrupt handler for this driver 647 * @irq: Irq of the Emaclite device 648 * @dev_id: Void pointer to the network device instance used as callback 649 * reference 650 * 651 * Return: IRQ_HANDLED 652 * 653 * This function handles the Tx and Rx interrupts of the EmacLite device. 654 */ 655 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 656 { 657 bool tx_complete = false; 658 struct net_device *dev = dev_id; 659 struct net_local *lp = netdev_priv(dev); 660 void __iomem *base_addr = lp->base_addr; 661 u32 tx_status; 662 663 /* Check if there is Rx Data available */ 664 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 665 XEL_RSR_RECV_DONE_MASK) || 666 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 667 & XEL_RSR_RECV_DONE_MASK)) 668 669 xemaclite_rx_handler(dev); 670 671 /* Check if the Transmission for the first buffer is completed */ 672 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 673 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 674 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 675 676 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 677 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 678 679 tx_complete = true; 680 } 681 682 /* Check if the Transmission for the second buffer is completed */ 683 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 684 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 685 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 686 687 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 688 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 689 XEL_TSR_OFFSET); 690 691 tx_complete = true; 692 } 693 694 /* If there was a Tx interrupt, call the Tx Handler */ 695 if (tx_complete != 0) 696 xemaclite_tx_handler(dev); 697 698 return IRQ_HANDLED; 699 } 700 701 /**********************/ 702 /* MDIO Bus functions */ 703 /**********************/ 704 705 /** 706 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 707 * @lp: Pointer to the Emaclite device private data 708 * 709 * This function waits till the device is ready to accept a new MDIO 710 * request. 711 * 712 * Return: 0 for success or ETIMEDOUT for a timeout 713 */ 714 715 static int xemaclite_mdio_wait(struct net_local *lp) 716 { 717 unsigned long end = jiffies + 2; 718 719 /* wait for the MDIO interface to not be busy or timeout 720 * after some time. 721 */ 722 while (xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) & 723 XEL_MDIOCTRL_MDIOSTS_MASK) { 724 if (time_before_eq(end, jiffies)) { 725 WARN_ON(1); 726 return -ETIMEDOUT; 727 } 728 msleep(1); 729 } 730 return 0; 731 } 732 733 /** 734 * xemaclite_mdio_read - Read from a given MII management register 735 * @bus: the mii_bus struct 736 * @phy_id: the phy address 737 * @reg: register number to read from 738 * 739 * This function waits till the device is ready to accept a new MDIO 740 * request and then writes the phy address to the MDIO Address register 741 * and reads data from MDIO Read Data register, when its available. 742 * 743 * Return: Value read from the MII management register 744 */ 745 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 746 { 747 struct net_local *lp = bus->priv; 748 u32 ctrl_reg; 749 u32 rc; 750 751 if (xemaclite_mdio_wait(lp)) 752 return -ETIMEDOUT; 753 754 /* Write the PHY address, register number and set the OP bit in the 755 * MDIO Address register. Set the Status bit in the MDIO Control 756 * register to start a MDIO read transaction. 757 */ 758 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 759 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 760 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 761 lp->base_addr + XEL_MDIOADDR_OFFSET); 762 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 763 lp->base_addr + XEL_MDIOCTRL_OFFSET); 764 765 if (xemaclite_mdio_wait(lp)) 766 return -ETIMEDOUT; 767 768 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 769 770 dev_dbg(&lp->ndev->dev, 771 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 772 phy_id, reg, rc); 773 774 return rc; 775 } 776 777 /** 778 * xemaclite_mdio_write - Write to a given MII management register 779 * @bus: the mii_bus struct 780 * @phy_id: the phy address 781 * @reg: register number to write to 782 * @val: value to write to the register number specified by reg 783 * 784 * This function waits till the device is ready to accept a new MDIO 785 * request and then writes the val to the MDIO Write Data register. 786 * 787 * Return: 0 upon success or a negative error upon failure 788 */ 789 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 790 u16 val) 791 { 792 struct net_local *lp = bus->priv; 793 u32 ctrl_reg; 794 795 dev_dbg(&lp->ndev->dev, 796 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 797 phy_id, reg, val); 798 799 if (xemaclite_mdio_wait(lp)) 800 return -ETIMEDOUT; 801 802 /* Write the PHY address, register number and clear the OP bit in the 803 * MDIO Address register and then write the value into the MDIO Write 804 * Data register. Finally, set the Status bit in the MDIO Control 805 * register to start a MDIO write transaction. 806 */ 807 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 808 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 809 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 810 lp->base_addr + XEL_MDIOADDR_OFFSET); 811 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 812 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 813 lp->base_addr + XEL_MDIOCTRL_OFFSET); 814 815 return 0; 816 } 817 818 /** 819 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 820 * @lp: Pointer to the Emaclite device private data 821 * @dev: Pointer to OF device structure 822 * 823 * This function enables MDIO bus in the Emaclite device and registers a 824 * mii_bus. 825 * 826 * Return: 0 upon success or a negative error upon failure 827 */ 828 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 829 { 830 struct mii_bus *bus; 831 int rc; 832 struct resource res; 833 struct device_node *np = of_get_parent(lp->phy_node); 834 struct device_node *npp; 835 836 /* Don't register the MDIO bus if the phy_node or its parent node 837 * can't be found. 838 */ 839 if (!np) { 840 dev_err(dev, "Failed to register mdio bus.\n"); 841 return -ENODEV; 842 } 843 npp = of_get_parent(np); 844 845 of_address_to_resource(npp, 0, &res); 846 if (lp->ndev->mem_start != res.start) { 847 struct phy_device *phydev; 848 phydev = of_phy_find_device(lp->phy_node); 849 if (!phydev) 850 dev_info(dev, 851 "MDIO of the phy is not registered yet\n"); 852 else 853 put_device(&phydev->mdio.dev); 854 return 0; 855 } 856 857 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 858 * register. 859 */ 860 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 861 lp->base_addr + XEL_MDIOCTRL_OFFSET); 862 863 bus = mdiobus_alloc(); 864 if (!bus) { 865 dev_err(dev, "Failed to allocate mdiobus\n"); 866 return -ENOMEM; 867 } 868 869 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 870 (unsigned long long)res.start); 871 bus->priv = lp; 872 bus->name = "Xilinx Emaclite MDIO"; 873 bus->read = xemaclite_mdio_read; 874 bus->write = xemaclite_mdio_write; 875 bus->parent = dev; 876 877 rc = of_mdiobus_register(bus, np); 878 if (rc) { 879 dev_err(dev, "Failed to register mdio bus.\n"); 880 goto err_register; 881 } 882 883 lp->mii_bus = bus; 884 885 return 0; 886 887 err_register: 888 mdiobus_free(bus); 889 return rc; 890 } 891 892 /** 893 * xemaclite_adjust_link - Link state callback for the Emaclite device 894 * @ndev: pointer to net_device struct 895 * 896 * There's nothing in the Emaclite device to be configured when the link 897 * state changes. We just print the status. 898 */ 899 static void xemaclite_adjust_link(struct net_device *ndev) 900 { 901 struct net_local *lp = netdev_priv(ndev); 902 struct phy_device *phy = lp->phy_dev; 903 int link_state; 904 905 /* hash together the state values to decide if something has changed */ 906 link_state = phy->speed | (phy->duplex << 1) | phy->link; 907 908 if (lp->last_link != link_state) { 909 lp->last_link = link_state; 910 phy_print_status(phy); 911 } 912 } 913 914 /** 915 * xemaclite_open - Open the network device 916 * @dev: Pointer to the network device 917 * 918 * This function sets the MAC address, requests an IRQ and enables interrupts 919 * for the Emaclite device and starts the Tx queue. 920 * It also connects to the phy device, if MDIO is included in Emaclite device. 921 * 922 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 923 * Non-zero error value on failure. 924 */ 925 static int xemaclite_open(struct net_device *dev) 926 { 927 struct net_local *lp = netdev_priv(dev); 928 int retval; 929 930 /* Just to be safe, stop the device first */ 931 xemaclite_disable_interrupts(lp); 932 933 if (lp->phy_node) { 934 u32 bmcr; 935 936 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 937 xemaclite_adjust_link, 0, 938 PHY_INTERFACE_MODE_MII); 939 if (!lp->phy_dev) { 940 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 941 return -ENODEV; 942 } 943 944 /* EmacLite doesn't support giga-bit speeds */ 945 phy_set_max_speed(lp->phy_dev, SPEED_100); 946 947 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 948 phy_write(lp->phy_dev, MII_CTRL1000, 0); 949 950 /* Advertise only 10 and 100mbps full/half duplex speeds */ 951 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 952 ADVERTISE_CSMA); 953 954 /* Restart auto negotiation */ 955 bmcr = phy_read(lp->phy_dev, MII_BMCR); 956 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 957 phy_write(lp->phy_dev, MII_BMCR, bmcr); 958 959 phy_start(lp->phy_dev); 960 } 961 962 /* Set the MAC address each time opened */ 963 xemaclite_update_address(lp, dev->dev_addr); 964 965 /* Grab the IRQ */ 966 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 967 if (retval) { 968 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 969 dev->irq); 970 if (lp->phy_dev) 971 phy_disconnect(lp->phy_dev); 972 lp->phy_dev = NULL; 973 974 return retval; 975 } 976 977 /* Enable Interrupts */ 978 xemaclite_enable_interrupts(lp); 979 980 /* We're ready to go */ 981 netif_start_queue(dev); 982 983 return 0; 984 } 985 986 /** 987 * xemaclite_close - Close the network device 988 * @dev: Pointer to the network device 989 * 990 * This function stops the Tx queue, disables interrupts and frees the IRQ for 991 * the Emaclite device. 992 * It also disconnects the phy device associated with the Emaclite device. 993 * 994 * Return: 0, always. 995 */ 996 static int xemaclite_close(struct net_device *dev) 997 { 998 struct net_local *lp = netdev_priv(dev); 999 1000 netif_stop_queue(dev); 1001 xemaclite_disable_interrupts(lp); 1002 free_irq(dev->irq, dev); 1003 1004 if (lp->phy_dev) 1005 phy_disconnect(lp->phy_dev); 1006 lp->phy_dev = NULL; 1007 1008 return 0; 1009 } 1010 1011 /** 1012 * xemaclite_send - Transmit a frame 1013 * @orig_skb: Pointer to the socket buffer to be transmitted 1014 * @dev: Pointer to the network device 1015 * 1016 * This function checks if the Tx buffer of the Emaclite device is free to send 1017 * data. If so, it fills the Tx buffer with data from socket buffer data, 1018 * updates the stats and frees the socket buffer. The Tx completion is signaled 1019 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1020 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1021 * be transmitted when the Emaclite device is free to transmit data. 1022 * 1023 * Return: NETDEV_TX_OK, always. 1024 */ 1025 static netdev_tx_t 1026 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1027 { 1028 struct net_local *lp = netdev_priv(dev); 1029 struct sk_buff *new_skb; 1030 unsigned int len; 1031 unsigned long flags; 1032 1033 len = orig_skb->len; 1034 1035 new_skb = orig_skb; 1036 1037 spin_lock_irqsave(&lp->reset_lock, flags); 1038 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1039 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1040 * defer the skb for transmission during the ISR, after the 1041 * current transmission is complete 1042 */ 1043 netif_stop_queue(dev); 1044 lp->deferred_skb = new_skb; 1045 /* Take the time stamp now, since we can't do this in an ISR. */ 1046 skb_tx_timestamp(new_skb); 1047 spin_unlock_irqrestore(&lp->reset_lock, flags); 1048 return NETDEV_TX_OK; 1049 } 1050 spin_unlock_irqrestore(&lp->reset_lock, flags); 1051 1052 skb_tx_timestamp(new_skb); 1053 1054 dev->stats.tx_bytes += len; 1055 dev_consume_skb_any(new_skb); 1056 1057 return NETDEV_TX_OK; 1058 } 1059 1060 /** 1061 * get_bool - Get a parameter from the OF device 1062 * @ofdev: Pointer to OF device structure 1063 * @s: Property to be retrieved 1064 * 1065 * This function looks for a property in the device node and returns the value 1066 * of the property if its found or 0 if the property is not found. 1067 * 1068 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1069 */ 1070 static bool get_bool(struct platform_device *ofdev, const char *s) 1071 { 1072 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1073 1074 if (!p) { 1075 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1076 return false; 1077 } 1078 1079 return (bool)*p; 1080 } 1081 1082 /** 1083 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info 1084 * @ndev: Pointer to net_device structure 1085 * @ed: Pointer to ethtool_drvinfo structure 1086 * 1087 * This implements ethtool command for getting the driver information. 1088 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1089 */ 1090 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev, 1091 struct ethtool_drvinfo *ed) 1092 { 1093 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1094 } 1095 1096 static const struct ethtool_ops xemaclite_ethtool_ops = { 1097 .get_drvinfo = xemaclite_ethtools_get_drvinfo, 1098 .get_link = ethtool_op_get_link, 1099 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1100 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1101 }; 1102 1103 static const struct net_device_ops xemaclite_netdev_ops; 1104 1105 /** 1106 * xemaclite_of_probe - Probe method for the Emaclite device. 1107 * @ofdev: Pointer to OF device structure 1108 * 1109 * This function probes for the Emaclite device in the device tree. 1110 * It initializes the driver data structure and the hardware, sets the MAC 1111 * address and registers the network device. 1112 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1113 * in the device. 1114 * 1115 * Return: 0, if the driver is bound to the Emaclite device, or 1116 * a negative error if there is failure. 1117 */ 1118 static int xemaclite_of_probe(struct platform_device *ofdev) 1119 { 1120 struct resource *res; 1121 struct net_device *ndev = NULL; 1122 struct net_local *lp = NULL; 1123 struct device *dev = &ofdev->dev; 1124 const void *mac_address; 1125 1126 int rc = 0; 1127 1128 dev_info(dev, "Device Tree Probing\n"); 1129 1130 /* Create an ethernet device instance */ 1131 ndev = alloc_etherdev(sizeof(struct net_local)); 1132 if (!ndev) 1133 return -ENOMEM; 1134 1135 dev_set_drvdata(dev, ndev); 1136 SET_NETDEV_DEV(ndev, &ofdev->dev); 1137 1138 lp = netdev_priv(ndev); 1139 lp->ndev = ndev; 1140 1141 /* Get IRQ for the device */ 1142 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1143 if (!res) { 1144 dev_err(dev, "no IRQ found\n"); 1145 rc = -ENXIO; 1146 goto error; 1147 } 1148 1149 ndev->irq = res->start; 1150 1151 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1152 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1153 if (IS_ERR(lp->base_addr)) { 1154 rc = PTR_ERR(lp->base_addr); 1155 goto error; 1156 } 1157 1158 ndev->mem_start = res->start; 1159 ndev->mem_end = res->end; 1160 1161 spin_lock_init(&lp->reset_lock); 1162 lp->next_tx_buf_to_use = 0x0; 1163 lp->next_rx_buf_to_use = 0x0; 1164 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1165 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1166 mac_address = of_get_mac_address(ofdev->dev.of_node); 1167 1168 if (!IS_ERR(mac_address)) { 1169 /* Set the MAC address. */ 1170 ether_addr_copy(ndev->dev_addr, mac_address); 1171 } else { 1172 dev_warn(dev, "No MAC address found, using random\n"); 1173 eth_hw_addr_random(ndev); 1174 } 1175 1176 /* Clear the Tx CSR's in case this is a restart */ 1177 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1178 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1179 1180 /* Set the MAC address in the EmacLite device */ 1181 xemaclite_update_address(lp, ndev->dev_addr); 1182 1183 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1184 xemaclite_mdio_setup(lp, &ofdev->dev); 1185 1186 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1187 1188 ndev->netdev_ops = &xemaclite_netdev_ops; 1189 ndev->ethtool_ops = &xemaclite_ethtool_ops; 1190 ndev->flags &= ~IFF_MULTICAST; 1191 ndev->watchdog_timeo = TX_TIMEOUT; 1192 1193 /* Finally, register the device */ 1194 rc = register_netdev(ndev); 1195 if (rc) { 1196 dev_err(dev, 1197 "Cannot register network device, aborting\n"); 1198 goto error; 1199 } 1200 1201 dev_info(dev, 1202 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1203 (unsigned int __force)ndev->mem_start, 1204 (unsigned int __force)lp->base_addr, ndev->irq); 1205 return 0; 1206 1207 error: 1208 free_netdev(ndev); 1209 return rc; 1210 } 1211 1212 /** 1213 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1214 * @of_dev: Pointer to OF device structure 1215 * 1216 * This function is called if a device is physically removed from the system or 1217 * if the driver module is being unloaded. It frees any resources allocated to 1218 * the device. 1219 * 1220 * Return: 0, always. 1221 */ 1222 static int xemaclite_of_remove(struct platform_device *of_dev) 1223 { 1224 struct net_device *ndev = platform_get_drvdata(of_dev); 1225 1226 struct net_local *lp = netdev_priv(ndev); 1227 1228 /* Un-register the mii_bus, if configured */ 1229 if (lp->mii_bus) { 1230 mdiobus_unregister(lp->mii_bus); 1231 mdiobus_free(lp->mii_bus); 1232 lp->mii_bus = NULL; 1233 } 1234 1235 unregister_netdev(ndev); 1236 1237 of_node_put(lp->phy_node); 1238 lp->phy_node = NULL; 1239 1240 free_netdev(ndev); 1241 1242 return 0; 1243 } 1244 1245 #ifdef CONFIG_NET_POLL_CONTROLLER 1246 static void 1247 xemaclite_poll_controller(struct net_device *ndev) 1248 { 1249 disable_irq(ndev->irq); 1250 xemaclite_interrupt(ndev->irq, ndev); 1251 enable_irq(ndev->irq); 1252 } 1253 #endif 1254 1255 /* Ioctl MII Interface */ 1256 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1257 { 1258 if (!dev->phydev || !netif_running(dev)) 1259 return -EINVAL; 1260 1261 switch (cmd) { 1262 case SIOCGMIIPHY: 1263 case SIOCGMIIREG: 1264 case SIOCSMIIREG: 1265 return phy_mii_ioctl(dev->phydev, rq, cmd); 1266 default: 1267 return -EOPNOTSUPP; 1268 } 1269 } 1270 1271 static const struct net_device_ops xemaclite_netdev_ops = { 1272 .ndo_open = xemaclite_open, 1273 .ndo_stop = xemaclite_close, 1274 .ndo_start_xmit = xemaclite_send, 1275 .ndo_set_mac_address = xemaclite_set_mac_address, 1276 .ndo_tx_timeout = xemaclite_tx_timeout, 1277 .ndo_do_ioctl = xemaclite_ioctl, 1278 #ifdef CONFIG_NET_POLL_CONTROLLER 1279 .ndo_poll_controller = xemaclite_poll_controller, 1280 #endif 1281 }; 1282 1283 /* Match table for OF platform binding */ 1284 static const struct of_device_id xemaclite_of_match[] = { 1285 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1286 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1287 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1288 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1289 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1290 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1291 { /* end of list */ }, 1292 }; 1293 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1294 1295 static struct platform_driver xemaclite_of_driver = { 1296 .driver = { 1297 .name = DRIVER_NAME, 1298 .of_match_table = xemaclite_of_match, 1299 }, 1300 .probe = xemaclite_of_probe, 1301 .remove = xemaclite_of_remove, 1302 }; 1303 1304 module_platform_driver(xemaclite_of_driver); 1305 1306 MODULE_AUTHOR("Xilinx, Inc."); 1307 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1308 MODULE_LICENSE("GPL"); 1309